1 /* $NetBSD: imx6_ccmreg.h,v 1.3 2024/02/07 04:20:27 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2014 Ryo Shimizu 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 25 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #ifndef _ARM_NXP_IMX6_CCMREG_H 30 #define _ARM_NXP_IMX6_CCMREG_H 31 32 #include <sys/cdefs.h> 33 34 /* 35 * PERIPHCLK_N is an arm root clock divider for MPcore interrupt controller. 36 * PERIPHCLK_N is equal to, or greater than two. 37 * see "Cortex-A9 MPCore Technical Reference Manual" - 38 * Chapter 5: Clocks, Resets, and Power Management, 5.1: Clocks. 39 */ 40 #ifndef IMX6_PERIPHCLK_N 41 #define IMX6_PERIPHCLK_N 2 42 #endif 43 44 #ifndef IMX6_CKIL_FREQ 45 #define IMX6_CKIL_FREQ 32768 46 #endif 47 #ifndef IMX6_CKIH_FREQ 48 #define IMX6_CKIH_FREQ 0 49 #endif 50 #ifndef IMX6_OSC_FREQ 51 #define IMX6_OSC_FREQ (24 * 1000 * 1000) /* 24MHz */ 52 #endif 53 #ifndef IMX6_IPP_DI0_FREQ 54 #define IMX6_IPP_DI0_FREQ 0 55 #endif 56 #ifndef IMX6_IPP_DI1_FREQ 57 #define IMX6_IPP_DI1_FREQ 0 58 #endif 59 #ifndef IMX6_ANACLK1_FREQ 60 #define IMX6_ANACLK1_FREQ 0 61 #endif 62 #ifndef IMX6_ANACLK2_FREQ 63 #define IMX6_ANACLK2_FREQ 0 64 #endif 65 66 #define CCM_CCR 0x00000000 67 #define CCM_CCR_RBC_EN __BIT(27) 68 #define CCM_CCR_REG_BYPASS_COUNT __BITS(26, 21) 69 #define CCM_CCR_WB_COUNT __BITS(18, 16) 70 #define CCM_CCR_COSC_EN __BIT(12) 71 #define CCM_CCR_OSCNT __BITS(7, 0) 72 73 #define CCM_CCDR 0x00000004 74 #define CCM_CSR 0x00000008 75 #define CCM_CCSR 0x0000000c 76 #define CCM_CCSR_PLL3_PFD1_DIS_MASK __BIT(15) 77 #define CCM_CCSR_PLL3_PFD0_DIS_MASK __BIT(14) 78 #define CCM_CCSR_PLL3_PFD3_DIS_MASK __BIT(13) 79 #define CCM_CCSR_PLL3_PFD2_DIS_MASK __BIT(12) 80 #define CCM_CCSR_PLL2_PFD1_594M_DIS_MASK __BIT(11) 81 #define CCM_CCSR_PLL2_PFD0_DIS_MASK __BIT(10) 82 #define CCM_CCSR_PLL2_PFD2_DIS_MASK __BIT(9) 83 #define CCM_CCSR_STEP_SEL __BIT(8) 84 #define CCM_CCSR_PLL1_SW_CLK_SEL __BIT(2) 85 #define CCM_CCSR_PLL3_SW_CLK_SEL __BIT(0) 86 #define CCM_CACRR 0x00000010 87 #define CCM_CACRR_ARM_PODF __BITS(2, 0) 88 89 #define CCM_CBCDR 0x00000014 90 #define CCM_CBCDR_PERIPH_CLK2_PODF __BITS(29, 27) 91 /* source of mmdc_ch1_axi_clk_root */ 92 #define CCM_CBCDR_PERIPH2_CLK_SEL __BIT(26) 93 /* source of mmdc_ch0_axi_clk_root */ 94 #define CCM_CBCDR_PERIPH_CLK_SEL __BIT(25) 95 #define CCM_CBCDR_MMDC_CH0_AXI_PODF __BITS(21, 19) 96 #define CCM_CBCDR_AXI_PODF __BITS(18, 16) 97 #define CCM_CBCDR_AHB_PODF __BITS(12, 10) 98 #define CCM_CBCDR_IPG_PODF __BITS(9, 8) 99 #define CCM_CBCDR_AXI_ALT_SEL __BIT(7) 100 #define CCM_CBCDR_AXI_SEL __BITS(7, 6) 101 #define CCM_CBCDR_MMDC_CH1_AXI_PODF __BITS(5, 3) 102 #define CCM_CBCDR_PERIPH2_CLK2_PODF __BITS(2, 0) 103 104 #define CCM_CBCMR 0x00000018 105 #define CCM_CBCMR_GPU3D_SHADER_PODF __BITS(31, 29) 106 #define CCM_CBCMR_GPU3D_CORE_PODF __BITS(28, 26) 107 #define CCM_CBCMR_GPU2D_CORE_CLK_PODF __BITS(25, 23) 108 #define CCM_CBCMR_PRE_PERIPH2_CLK_SEL __BITS(22, 21) 109 #define CCM_CBCMR_PERIPH2_CLK2_SEL __BIT(20) 110 #define CCM_CBCMR_PRE_PERIPH_CLK_SEL __BITS(19, 18) 111 #define CCM_CBCMR_GPU2D_CLK_SEL __BITS(17, 16) 112 #define CCM_CBCMR_VPU_AXI_CLK_SEL __BITS(15, 14) 113 #define CCM_CBCMR_PERIPH_CLK2_SEL __BITS(13, 12) 114 #define CCM_CBCMR_VDOAXI_CLK_SEL __BIT(11) 115 #define CCM_CBCMR_PCIE_AXI_CLK_SEL __BIT(10) 116 #define CCM_CBCMR_GPU3D_SHADER_CLK_SEL __BITS(9, 8) 117 #define CCM_CBCMR_GPU3D_CORE_CLK_SEL __BITS(5, 4) 118 #define CCM_CBCMR_GPU3D_AXI_CLK_SEL __BIT(1) 119 #define CCM_CBCMR_GPU2D_AXI_CLK_SEL __BIT(0) 120 121 #define CCM_CSCMR1 0x0000001c 122 #define CCM_CSCMR1_ACLK_EIM_SLOW_SEL __BITS(30, 29) 123 #define CCM_CSCMR1_ACLK_SEL __BITS(28, 27) 124 #define CCM_CSCMR1_QSPI1_PODF __BITS(28, 26) /* 6sx */ 125 #define CCM_CSCMR1_ACLK_EIM_SLOW_PODF __BITS(25, 23) 126 #define CCM_CSCMR1_ACLK_PODF __BITS(22, 20) 127 #define CCM_CSCMR1_USDHC4_CLK_SEL __BIT(19) 128 #define CCM_CSCMR1_USDHC3_CLK_SEL __BIT(18) 129 #define CCM_CSCMR1_USDHC2_CLK_SEL __BIT(17) 130 #define CCM_CSCMR1_USDHC1_CLK_SEL __BIT(16) 131 #define CCM_CSCMR1_SSI3_CLK_SEL __BITS(15, 14) 132 #define CCM_CSCMR1_SSI2_CLK_SEL __BITS(13, 12) 133 #define CCM_CSCMR1_SSI1_CLK_SEL __BITS(11, 10) 134 #define CCM_CSCMR1_QSOI1_SEL __BITS(9, 7) /* 6sx */ 135 #define CCM_CSCMR1_PERCLK_SEL __BIT(6) /* 6sx */ 136 #define CCM_CSCMR1_PERCLK_PODF __BITS(5, 0) 137 138 #define CCM_CSCMR2 0x00000020 139 #define CCM_CSCMR2_VID_CLK_PODF __BITS(25, 24) /* 6sx */ 140 #define CCM_CSCMR2_VID_CLK_SEL __BITS(23, 21) /* 6sx */ 141 #define CCM_CSCMR2_ESAI_CLK_SEL __BITS(20, 19) 142 #define CCM_CSCMR2_LDB_DI1_IPU_DIV __BIT(11) 143 #define CCM_CSCMR2_LDB_DI0_IPU_DIV __BIT(10) 144 #define CCM_CSCMR2_CAN_CLK_SEL __BITS(9, 8) /* 6sx */ 145 #define CCM_CSCMR2_CAN_CLK_PODF __BITS(7, 2) 146 147 #define CCM_CSCDR1 0x00000024 148 #define CCM_CSCDR1_VPU_AXI_PODF __BITS(27, 25) 149 #define CCM_CSCDR1_USDHC4_PODF __BITS(24, 22) 150 #define CCM_CSCDR1_USDHC3_PODF __BITS(21, 19) 151 #define CCM_CSCDR1_USDHC2_PODF __BITS(18, 16) 152 #define CCM_CSCDR1_USDHC1_PODF __BITS(13, 11) 153 #define CCM_CSCDR1_UART_CLK_PODF __BITS(5, 0) 154 #define CCM_CSCDR1_UART_CLK_SEL __BIT(6) /* 6sx */ 155 156 #define CCM_CS1CDR 0x00000028 157 #define CCM_CS1CDR_ESAI_CLK_PODF __BITS(27, 25) 158 #define CCM_CS1CDR_SSI3_CLK_PRED __BITS(24, 22) 159 #define CCM_CS1CDR_SSI3_CLK_PODF __BITS(21, 16) 160 #define CCM_CS1CDR_ESAI_CLK_PRED __BITS(11, 9) 161 #define CCM_CS1CDR_SSI1_CLK_PRED __BITS(8, 6) 162 #define CCM_CS1CDR_SSI1_CLK_PODF __BITS(5, 0) 163 164 #define CCM_CS2CDR 0x0000002c 165 #define CCM_CS2CDR_ENFC_CLK_PODF __BITS(26, 21) 166 #define CCM_CS2CDR_ENFC_CLK_PRED __BITS(20, 18) 167 #define CCM_CS2CDR_ENFC_CLK_SEL __BITS(17, 16) 168 #define CCM_CS2CDR_QSPI2_CLK_SEL __BITS(17, 15) /* 6sx */ 169 #define CCM_CS2CDR_LDB_DI1_CLK_SEL __BITS(14, 12) 170 #define CCM_CS2CDR_LDB_DI0_CLK_SEL __BITS(11, 9) 171 #define CCM_CS2CDR_SSI2_CLK_PRED __BITS(8, 6) 172 #define CCM_CS2CDR_SSI2_CLK_PODF __BITS(5, 0) 173 174 #define CCM_CDCDR 0x00000030 175 #define CCM_CDCDR_HSI_TX_PODF __BITS(31, 29) 176 #define CCM_CDCDR_HSI_TX_CLK_SEL __BIT(28) 177 #define CCM_CDCDR_SPDIF0_CLK_PRED __BITS(27, 25) 178 #define CCM_CDCDR_SPDIF0_CLK_PODF __BITS(24, 22) 179 #define CCM_CDCDR_SPDIF0_CLK_SEL __BITS(21, 20) 180 #define CCM_CDCDR_SPDIF1_CLK_PRED __BITS(14, 12) 181 #define CCM_CDCDR_SPDIF1_CLK_PODF __BITS(11, 9) 182 #define CCM_CDCDR_SPDIF1_CLK_SEL __BITS(8, 7) 183 184 #define CCM_CHSCCDR 0x00000034 185 #define CCM_CHSCCDR_ENET_PRE_CLK_SEL __BITS(17, 15) /* 6sx */ 186 #define CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL __BITS(17, 15) 187 #define CCM_CHSCCDR_IPU1_DI1_PODF __BITS(14, 12) 188 #define CCM_CHSCCDR_ENET_CLK_SEL __BITS(11, 9) /* 6sx */ 189 #define CCM_CHSCCDR_IPU1_DI1_CLK_SEL __BITS(11, 9) 190 #define CCM_CHSCCDR_M4_PRE_CLK_SEL __BITS(8, 6) /* 6sx */ 191 #define CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL __BITS(8, 6) 192 #define CCM_CHSCCDR_IPU1_DI0_PODF __BITS(5, 3) 193 #define CCM_CHSCCDR_M4_CLK_SEL __BITS(2, 0) /* 6sx */ 194 #define CCM_CHSCCDR_IPU1_DI0_CLK_SEL __BITS(2, 0) 195 196 #define CCM_CSCDR2 0x00000038 197 #define CCM_CSCDR2_ECSPI_CLK_PODF __BITS(24, 19) 198 #define CCM_CSCDR2_ECSPI_SEL __BIT(18) /* 6sx */ 199 #define CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL __BITS(17, 15) 200 #define CCM_CSCDR2_IPU2_DI1_PODF __BITS(14, 12) 201 #define CCM_CSCDR2_IPU2_DI1_CLK_SEL __BITS(11, 9) 202 #define CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL __BITS(8, 6) 203 #define CCM_CSCDR2_IPU2_DI0_PODF __BITS(5, 3) 204 #define CCM_CSCDR2_IPU2_DI0_CLK_SEL __BITS(2, 0) 205 206 #define CCM_CDHIPR 0x00000048 207 #define CCM_CDHIPR_ARM_PODF_BUSY __BIT(16) 208 #define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY __BIT(5) 209 #define CCM_CDHIPR_MMDC_CH0_PODF_BUSY __BIT(4) 210 #define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY __BIT(3) 211 #define CCM_CDHIPR_MMDC_CH1_PODF_BUSY __BIT(2) 212 #define CCM_CDHIPR_AHB_PODF_BUSY __BIT(1) 213 #define CCM_CDHIPR_AXI_PODF_BUSY __BIT(0) 214 215 #define CCM_CSCDR3 0x0000003c 216 #define CCM_CSCDR3_IPU2_HSP_PODF __BITS(18, 16) 217 #define CCM_CSCDR3_IPU2_HSP_CLK_SEL __BITS(15, 14) 218 #define CCM_CSCDR3_IPU1_HSP_PODF __BITS(13, 11) 219 #define CCM_CSCDR3_IPU1_HSP_CLK_SEL __BITS(10, 9) 220 221 #define CCM_CCOSR 0x00000060 222 #define CCM_CCOSR_CLKO2_EN __BIT(24) 223 #define CCM_CCOSR_CLKO2_DIV __BITS(23, 21) 224 #define CCM_CCOSR_CLKO2_SEL __BITS(20, 16) 225 #define CCM_CCOSR_CLK_OUT_SEL __BIT(8) 226 #define CCM_CCOSR_CLKO1_EN __BIT(7) 227 #define CCM_CCOSR_CLKO1_DIV __BITS(6, 4) 228 #define CCM_CCOSR_CLKO1_SEL __BITS(3, 0) 229 230 #define CCM_CCGR0 0x00000068 231 #define CCM_CCGR0_TZ3_CLK_ENABLE __BITS(31, 30) 232 #define CCM_CCGR0_DTCP_CLK_ENABLE __BITS(29, 28) 233 #define CCM_CCGR0_DCIC2_CLK_ENABLE __BITS(27, 26) 234 #define CCM_CCGR0_DCIC1_CLK_ENABLE __BITS(25, 24) 235 #define CCM_CCGR0_ARM_DBG_CLK_ENABLE __BITS(23, 22) 236 #define CCM_CCGR0_CAN2_SERIAL_CLK_ENABLE __BITS(21, 20) 237 #define CCM_CCGR0_CAN2_CLK_ENABLE __BITS(19, 18) 238 #define CCM_CCGR0_CAN1_SERIAL_CLK_ENABLE __BITS(17, 16) 239 #define CCM_CCGR0_CAN1_CLK_ENABLE __BITS(15, 14) 240 #define CCM_CCGR0_CAAM_WRAPPER_IPG_ENABLE __BITS(13, 12) 241 #define CCM_CCGR0_CAAM_WRAPPER_ACLK_ENABLE __BITS(11, 10) 242 #define CCM_CCGR0_CAAM_SECURE_MEM_CLK_ENABLE __BITS(9, 8) 243 #define CCM_CCGR0_ASRC_CLK_ENABLE __BITS(7, 6) 244 #define CCM_CCGR0_APBHDMA_HCLK_ENABLE __BITS(5, 4) 245 #define CCM_CCGR0_AIPS_TZ2_CLK_ENABLE __BITS(3, 2) 246 #define CCM_CCGR0_AIPS_TZ1_CLK_ENABLE __BITS(1, 0) 247 #define CCM_CCGR1 0x0000006C 248 #define CCM_CCGR1_CANFD_CLK_ENABLE __BITS(31, 30) /* 6sx */ 249 #define CCM_CCGR1_OCRAM_CLK_ENABLE __BITS(29, 28) /* 6sx */ 250 #define CCM_CCGR1_GPU3D_CLK_ENABLE __BITS(27, 26) 251 #define CCM_CCGR1_GPU2D_CLK_ENABLE __BITS(25, 24) 252 #define CCM_CCGR1_GPT_SERIAL_CLK_ENABLE __BITS(23, 22) 253 #define CCM_CCGR1_GPT_CLK_ENABLE __BITS(21, 20) 254 #define CCM_CCGR1_WAKEUP_CLK_ENABLE __BITS(19, 18) /* 6sx */ 255 #define CCM_CCGR1_ESAI_CLK_ENABLE __BITS(17, 16) 256 #define CCM_CCGR1_EPIT2_CLK_ENABLE __BITS(15, 14) 257 #define CCM_CCGR1_EPIT1_CLK_ENABLE __BITS(13, 12) 258 #define CCM_CCGR1_ENET_CLK_ENABLE __BITS(11, 10) 259 #define CCM_CCGR1_I2C4_CLK_ENABLE __BITS(9, 8) /* i.MX6DL */ 260 #define CCM_CCGR1_ECSPI5_CLK_ENABLE __BITS(9, 8) /* i.MX6Q */ 261 #define CCM_CCGR1_ECSPI4_CLK_ENABLE __BITS(7, 6) 262 #define CCM_CCGR1_ECSPI3_CLK_ENABLE __BITS(5, 4) 263 #define CCM_CCGR1_ECSPI2_CLK_ENABLE __BITS(3, 2) 264 #define CCM_CCGR1_ECSPI1_CLK_ENABLE __BITS(1, 0) 265 #define CCM_CCGR2 0x00000070 266 #define CCM_CCGR2_PXP_AXI_CLK_ENABLE __BITS(31, 30) 267 #define CCM_CCGR2_LCDIF_APB_CLK_ENABLE __BITS(29, 28) 268 #define CCM_CCGR2_IPSYNC_VDOA_IPG_CLK_ENABLE __BITS(27, 26) 269 #define CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_CLK_ENABLE __BITS(25, 24) 270 #define CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPG_CLK_ENABLE __BITS(23, 22) 271 #define CCM_CCGR2_IPMUX3_CLK_ENABLE __BITS(21, 20) 272 #define CCM_CCGR2_IPMUX2_CLK_ENABLE __BITS(19, 18) 273 #define CCM_CCGR2_IPMUX1_CLK_ENABLE __BITS(17, 16) 274 #define CCM_CCGR2_IOMUX_IPT_CLK_IO_CLK_ENABLE __BITS(15, 14) 275 #define CCM_CCGR2_IIM_CLK_ENABLE __BITS(13, 12) 276 #define CCM_CCGR2_I2C3_SERIAL_CLK_ENABLE __BITS(11, 10) 277 #define CCM_CCGR2_I2C2_SERIAL_CLK_ENABLE __BITS(9, 8) 278 #define CCM_CCGR2_I2C1_SERIAL_CLK_ENABLE __BITS(7, 6) 279 #define CCM_CCGR2_HDMI_TX_ISFRCLK_ENABLE __BITS(5, 4) 280 #define CCM_CCGR2_CSI_CLK_ENABLE __BITS(3, 2) /* 6sx */ 281 #define CCM_CCGR2_HDMI_TX_IAHBCLK_ENABLE __BITS(1, 0) 282 #define CCM_CCGR3 0x00000074 283 #define CCM_CCGR3_OPENVGAXICLK_CLK_ROOT_ENABLE __BITS(31, 30) 284 #define CCM_CCGR3_OCRAM_CLK_ENABLE __BITS(29, 28) 285 #define CCM_CCGR3_MMDC_P1_IPG_CLK_ENABLE __BITS(27, 26) /* 6sx */ 286 #define CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_ENABLE __BITS(25, 24) 287 #define CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_ENABLE __BITS(23, 22) 288 #define CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_ENABLE __BITS(21, 20) 289 #define CCM_CCGR3_MLB_CLK_ENABLE __BITS(19, 18) 290 #define CCM_CCGR3_MIPI_CORE_CFG_CLK_ENABLE __BITS(17, 16) 291 #define CCM_CCGR3_LDB_DI1_CLK_ENABLE __BITS(15, 14) 292 #define CCM_CCGR3_LDB_DI0_CLK_ENABLE __BITS(13, 12) 293 #define CCM_CCGR3_IPU2_IPU_DI1_CLK_ENABLE __BITS(11, 10) 294 #define CCM_CCGR3_IPU2_IPU_DI0_CLK_ENABLE __BITS(9, 8) 295 #define CCM_CCGR3_IPU2_IPU_CLK_ENABLE __BITS(7, 6) 296 #define CCM_CCGR3_IPU1_IPU_DI1_CLK_ENABLE __BITS(5, 4) 297 #define CCM_CCGR3_IPU1_IPU_DI0_CLK_ENABLE __BITS(3, 2) 298 #define CCM_CCGR3_IPU1_IPU_CLK_ENABLE __BITS(1, 0) 299 #define CCM_CCGR4 0x00000078 300 #define CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_CLK_ENABLE __BITS(31, 30) 301 #define CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_CLK_ENABLE __BITS(29, 28) 302 #define CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_CLK_ENABLE __BITS(27, 26) 303 #define CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_CLK_ENABLE __BITS(25, 24) 304 #define CCM_CCGR4_PWM4_CLK_ENABLE __BITS(23, 22) 305 #define CCM_CCGR4_PWM3_CLK_ENABLE __BITS(21, 20) 306 #define CCM_CCGR4_PWM2_CLK_ENABLE __BITS(19, 18) 307 #define CCM_CCGR4_PWM1_CLK_ENABLE __BITS(17, 16) 308 #define CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE __BITS(15, 14) 309 #define CCM_CCGR4_PL301_MX6QPER1_BCHCLK_ENABLE __BITS(13, 12) 310 #define CCM_CCGR4_QSPI2_ENABLE __BITS(11, 10) /*6sx*/ 311 #define CCM_CCGR4_PL301_MX6QFAST1_S133CLK_ENABLE __BITS(9, 8) 312 #define CCM_CCGR4_PCIE_ROOT_ENABLE __BITS(1, 0) 313 #define CCM_CCGR5 0x0000007c 314 #define CCM_CCGR5_SAI2_ENABLE __BITS(31, 30) /* 6sx */ 315 #define CCM_CCGR5_SAI1_ENABLE __BITS(29, 28) /* 6sx */ 316 #define CCM_CCGR5_UART_SERIAL_CLK_ENABLE __BITS(27, 26) 317 #define CCM_CCGR5_UART_CLK_ENABLE __BITS(25, 24) 318 #define CCM_CCGR5_SSI3_CLK_ENABLE __BITS(23, 22) 319 #define CCM_CCGR5_SSI2_CLK_ENABLE __BITS(21, 20) 320 #define CCM_CCGR5_SSI1_CLK_ENABLE __BITS(19, 18) 321 #define CCM_CCGR5_SPDIF_CLK_ENABLE __BITS(15, 14) 322 #define CCM_CCGR5_SPBA_CLK_ENABLE __BITS(13, 12) 323 #define CCM_CCGR5_SDMA_CLK_ENABLE __BITS(7, 6) 324 #define CCM_CCGR5_SATA_CLK_ENABLE __BITS(5, 4) 325 #define CCM_CCGR5_ROM_CLK_ENABLE __BITS(1, 0) 326 #define CCM_CCGR6 0x00000080 327 #define CCM_CCGR6_PWM7_CLK_ENABLE __BITS(31, 30) /* 6sx */ 328 #define CCM_CCGR6_PWM6_CLK_ENABLE __BITS(29, 28) /* 6sx */ 329 #define CCM_CCGR6_PWM5_CLK_ENABLE __BITS(27, 26) /* 6sx */ 330 #define CCM_CCGR6_I2CS4_CLK_ENABLE __BITS(25, 24) /* 6sx */ 331 #define CCM_CCGR6_GIS_CLK_ENABLE __BITS(23, 22) /* 6sx */ 332 #define CCM_CCGR6_VADC_CLK_ENABLE __BITS(21, 20) /* 6sx */ 333 #define CCM_CCGR6_PWM8_CLK_ENABLE __BITS(17, 16) /* 6sx */ 334 #define CCM_CCGR6_VPU_CLK_ENABLE __BITS(15, 14) 335 #define CCM_CCGR6_VDOAXICLK_CLK_ENABLE __BITS(13, 12) 336 #define CCM_CCGR6_EIM_SLOW_CLK_ENABLE __BITS(11, 10) 337 #define CCM_CCGR6_USDHC4_CLK_ENABLE __BITS(9, 8) 338 #define CCM_CCGR6_USDHC3_CLK_ENABLE __BITS(7, 6) 339 #define CCM_CCGR6_USDHC2_CLK_ENABLE __BITS(5, 4) 340 #define CCM_CCGR6_USDHC1_CLK_ENABLE __BITS(3, 2) 341 #define CCM_CCGR6_USBOH3_CLK_ENABLE __BITS(1, 0) 342 343 #define CCM_ANALOG_BASE 0x00004000 344 #define CCM_ANALOG_SIZE 0x00001000 345 346 #define CCM_ANALOG_PLL_ARM 0x00000000 /* = 020c8000 */ 347 #define CCM_ANALOG_PLL_ARM_SET 0x00000004 348 #define CCM_ANALOG_PLL_ARM_CLR 0x00000008 349 #define CCM_ANALOG_PLL_ARM_TOG 0x0000000c 350 #define CCM_ANALOG_PLL_ARM_LOCK __BIT(31) 351 #define CCM_ANALOG_PLL_ARM_PLL_SEL __BIT(19) 352 #define CCM_ANALOG_PLL_ARM_LVDS_24MHZ_SEL __BIT(18) 353 #define CCM_ANALOG_PLL_ARM_LVDS_SEL __BIT(17) 354 #define CCM_ANALOG_PLL_ARM_BYPASS __BIT(16) 355 #define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC __BITS(15, 14) 356 #define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_6SX __BIT(14) /* 6sx */ 357 #define CCM_ANALOG_PLL_ARM_ENABLE __BIT(13) 358 #define CCM_ANALOG_PLL_ARM_POWERDOWN __BIT(12) 359 #define CCM_ANALOG_PLL_ARM_DIV_SELECT __BITS(6, 0) 360 361 #define CCM_ANALOG_PLL_LOCK __BIT(31) 362 #define CCM_ANALOG_PLL_BYPASS __BIT(16) 363 #define CCM_ANALOG_PLL_BYPASS_CLK_SRC __BITS(15, 14) 364 #define CCM_ANALOG_PLL_BYPASS_CLK_SRC_6SX __BIT(14) 365 #define CCM_ANALOG_PLL_ENABLE __BIT(13) 366 #define CCM_ANALOG_PLL_POWER __BIT(12) 367 #define CCM_ANALOG_PLL_EN_USB_CLK __BIT(6) 368 #define CCM_ANALOG_PLL_DIV_SELECT __BITS(1, 0) 369 370 #define CCM_ANALOG_PLL_USB1 0x00000010 371 #define CCM_ANALOG_PLL_USB1_SET 0x00000014 372 #define CCM_ANALOG_PLL_USB1_CLR 0x00000018 373 #define CCM_ANALOG_PLL_USB1_TOG 0x0000001c 374 #define CCM_ANALOG_PLL_USB1_LOCK __BIT(31) 375 #define CCM_ANALOG_PLL_USB1_RESERVED __BIT(20) 376 #define CCM_ANALOG_PLL_USB1_BYPASS __BIT(16) 377 #define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC __BITS(15, 14) 378 #define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_6SX __BIT(14) 379 #define CCM_ANALOG_PLL_USB1_ENABLE __BIT(13) 380 #define CCM_ANALOG_PLL_USB1_POWER __BIT(12) 381 #define CCM_ANALOG_PLL_USB1_EN_USB_CLK __BIT(6) 382 #define CCM_ANALOG_PLL_USB1_DIV_SELECT __BITS(1, 0) 383 384 #define CCM_ANALOG_PLL_USB2 0x00000020 385 #define CCM_ANALOG_PLL_USB2_SET 0x00000024 386 #define CCM_ANALOG_PLL_USB2_CLR 0x00000028 387 #define CCM_ANALOG_PLL_USB2_TOG 0x0000002c 388 #define CCM_ANALOG_PLL_USB2_LOCK __BIT(31) 389 #define CCM_ANALOG_PLL_USB2_RESERVED __BIT(20) 390 #define CCM_ANALOG_PLL_USB2_BYPASS __BIT(16) 391 #define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC __BITS(15, 14) 392 #define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_6SX __BIT(14) 393 #define CCM_ANALOG_PLL_USB2_ENABLE __BIT(13) 394 #define CCM_ANALOG_PLL_USB2_POWER __BIT(12) 395 #define CCM_ANALOG_PLL_USB2_EN_USB_CLK __BIT(6) 396 #define CCM_ANALOG_PLL_USB2_DIV_SELECT __BITS(1, 0) 397 398 #define CCM_ANALOG_PLL_SYS 0x00000030 399 #define CCM_ANALOG_PLL_SYS_SET 0x00000034 400 #define CCM_ANALOG_PLL_SYS_CLR 0x00000038 401 #define CCM_ANALOG_PLL_SYS_TOG 0x0000003c 402 #define CCM_ANALOG_PLL_SYS_BYPASS __BIT(16) 403 #define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC __BITS(15, 14) 404 #define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_6SX __BIT(14) 405 #define CCM_ANALOG_PLL_SYS_ENABLE __BIT(13) 406 #define CCM_ANALOG_PLL_SYS_POWERDOWN __BIT(12) 407 #define CCM_ANALOG_PLL_SYS_DIV_SELECT __BIT(0) 408 #define CCM_ANALOG_PLL_SYS_SS 0x00000040 409 #define CCM_ANALOG_PLL_SYS_NUM 0x00000050 410 #define CCM_ANALOG_PLL_SYS_DENOM 0x00000060 411 #define CCM_ANALOG_PLL_AUDIO 0x00000070 412 #define CCM_ANALOG_PLL_AUDIO_SET 0x00000074 413 #define CCM_ANALOG_PLL_AUDIO_CLR 0x00000078 414 #define CCM_ANALOG_PLL_AUDIO_TOG 0x0000007c 415 #define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT __BITS(20, 19) 416 #define CCM_ANALOG_PLL_AUDIO_BYPASS __BIT(16) 417 #define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC __BITS(15, 14) 418 #define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_6SX __BIT(14) 419 #define CCM_ANALOG_PLL_AUDIO_ENABLE __BIT(13) 420 #define CCM_ANALOG_PLL_AUDIO_POWERDOWN __BIT(12) 421 #define CCM_ANALOG_PLL_AUDIO_DIV_SELECT __BITS(6, 0) 422 #define CCM_ANALOG_PLL_AUDIO_NUM 0x00000080 423 #define CCM_ANALOG_PLL_AUDIO_DENOM 0x00000090 424 #define CCM_ANALOG_PLL_VIDEO 0x000000a0 425 #define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT __BITS(20, 19) 426 #define CCM_ANALOG_PLL_VIDEO_BYPASS __BIT(16) 427 #define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC __BITS(15, 14) 428 #define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_6SX __BIT(14) 429 #define CCM_ANALOG_PLL_VIDEO_ENABLE __BIT(13) 430 #define CCM_ANALOG_PLL_VIDEO_POWERDOWN __BIT(12) 431 #define CCM_ANALOG_PLL_VIDEO_DIV_SELECT __BITS(6, 0) 432 #define CCM_ANALOG_PLL_VIDEO_SET 0x000000a4 433 #define CCM_ANALOG_PLL_VIDEO_CLR 0x000000a8 434 #define CCM_ANALOG_PLL_VIDEO_TOG 0x000000ac 435 #define CCM_ANALOG_PLL_VIDEO_NUM 0x000000b0 436 #define CCM_ANALOG_PLL_VIDEO_DENOM 0x000000c0 437 #define CCM_ANALOG_PLL_MLB 0x000000d0 438 #define CCM_ANALOG_PLL_MLB_SET 0x000000d4 439 #define CCM_ANALOG_PLL_MLB_CLR 0x000000d8 440 #define CCM_ANALOG_PLL_MLB_TOG 0x000000dc 441 #define CCM_ANALOG_PLL_ENET 0x000000e0 442 #define CCM_ANALOG_PLL_ENET_SET 0x000000e4 443 #define CCM_ANALOG_PLL_ENET_CLR 0x000000e8 444 #define CCM_ANALOG_PLL_ENET_TOG 0x000000ec 445 #define CCM_ANALOG_PLL_ENET_LOCK __BIT(31) 446 #define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN __BIT(21) /* iMX6UL */ 447 #define CCM_ANALOG_PLL_ENET_ENET2_125M_EN __BIT(20) /* iMX6UL */ 448 #define CCM_ANALOG_PLL_ENET_ENABLE_100M __BIT(20) /* SATA */ 449 #define CCM_ANALOG_PLL_ENET_ENABLE_125M __BIT(19) /* PCIe */ 450 #define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN __BIT(18) 451 #define CCM_ANALOG_PLL_ENET_BYPASS __BIT(16) 452 #define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC __BITS(15, 14) 453 #define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_6SX __BIT(14) 454 #define CCM_ANALOG_PLL_ENET_ENET1_125M_EN __BIT(13) /* iMX6UL */ 455 #define CCM_ANALOG_PLL_ENET_ENABLE __BIT(13) /* Ether */ 456 #define CCM_ANALOG_PLL_ENET_POWERDOWN __BIT(12) 457 #define CCM_ANALOG_PLL_ENET_DIV2_SELECT __BITS(3, 2) 458 #define CCM_ANALOG_PLL_ENET_DIV_SELECT __BITS(1, 0) 459 #define CCM_ANALOG_PFD_480 0x000000f0 460 #define CCM_ANALOG_PFD_480_SET 0x000000f4 461 #define CCM_ANALOG_PFD_480_CLR 0x000000f8 462 #define CCM_ANALOG_PFD_480_TOG 0x000000fc 463 #define CCM_ANALOG_PFD_480_PFD3_CLKGATE __BIT(31) 464 #define CCM_ANALOG_PFD_480_PFD3_STABLE __BIT(30) 465 #define CCM_ANALOG_PFD_480_PFD3_FRAC __BITS(29, 24) 466 #define CCM_ANALOG_PFD_480_PFD2_CLKGATE __BIT(23) 467 #define CCM_ANALOG_PFD_480_PFD2_STABLE __BIT(22) 468 #define CCM_ANALOG_PFD_480_PFD2_FRAC __BITS(21, 16) 469 #define CCM_ANALOG_PFD_480_PFD1_CLKGATE __BIT(15) 470 #define CCM_ANALOG_PFD_480_PFD1_STABLE __BIT(14) 471 #define CCM_ANALOG_PFD_480_PFD1_FRAC __BITS(13, 8) 472 #define CCM_ANALOG_PFD_480_PFD0_CLKGATE __BIT(7) 473 #define CCM_ANALOG_PFD_480_PFD0_STABLE __BIT(6) 474 #define CCM_ANALOG_PFD_480_PFD0_FRAC __BITS(5, 0) 475 #define CCM_ANALOG_PFD_528 0x00000100 476 #define CCM_ANALOG_PFD_528_SET 0x00000104 477 #define CCM_ANALOG_PFD_528_CLR 0x00000108 478 #define CCM_ANALOG_PFD_528_TOG 0x0000010c 479 #define CCM_ANALOG_PFD_528_PFD2_CLKGATE __BIT(23) 480 #define CCM_ANALOG_PFD_528_PFD2_STABLE __BIT(22) 481 #define CCM_ANALOG_PFD_528_PFD2_FRAC __BITS(21, 16) 482 #define CCM_ANALOG_PFD_528_PFD1_CLKGATE __BIT(15) 483 #define CCM_ANALOG_PFD_528_PFD1_STABLE __BIT(14) 484 #define CCM_ANALOG_PFD_528_PFD1_FRAC __BITS(13, 8) 485 #define CCM_ANALOG_PFD_528_PFD0_CLKGATE __BIT(7) 486 #define CCM_ANALOG_PFD_528_PFD0_STABLE __BIT(6) 487 #define CCM_ANALOG_PFD_528_PFD0_FRAC __BITS(5, 0) 488 #define CCM_ANALOG_MISC0 0x00000150 489 #define CCM_ANALOG_MISC0_SET 0x00000154 490 #define CCM_ANALOG_MISC0_CLR 0x00000158 491 #define CCM_ANALOG_MISC0_TOG 0x0000015c 492 #define CCM_ANALOG_MISC1 0x00000160 493 #define CCM_ANALOG_MISC1_SET 0x00000164 494 #define CCM_ANALOG_MISC1_CLR 0x00000168 495 #define CCM_ANALOG_MISC1_TOG 0x0000016c 496 #define CCM_ANALOG_MISC1_LVDS_CLK1_SRC __BITS(4, 0) 497 #define CCM_ANALOG_MISC1_LVDS_CLK1_SRC_PCIE __SHIFTIN(0xa, CCM_ANALOG_MISC1_LVDS_CLK1_SRC) 498 #define CCM_ANALOG_MISC1_LVDS_CLK1_SRC_SATA __SHIFTIN(0xb, CCM_ANALOG_MISC1_LVDS_CLK1_SRC) 499 #define CCM_ANALOG_MISC1_LVDS_CLK2_SRC __BITS(9, 5) 500 #define CCM_ANALOG_MISC1_LVDS_CLK1_OBEN __BIT(10) 501 #define CCM_ANALOG_MISC1_LVDS_CLK2_OBEN __BIT(11) 502 #define CCM_ANALOG_MISC1_LVDS_CLK1_IBEN __BIT(12) 503 #define CCM_ANALOG_MISC1_LVDS_CLK2_IBEN __BIT(13) 504 #define CCM_ANALOG_MISC2 0x00000170 505 #define CCM_ANALOG_MISC2_SET 0x00000174 506 #define CCM_ANALOG_MISC2_CLR 0x00000178 507 #define CCM_ANALOG_MISC2_TOG 0x0000017C 508 #define CCM_ANALOG_MISC2_VIDEO_DIV __BITS(31, 30) 509 #define CCM_ANALOG_MISC2_REG2_STEP_TIME __BITS(29, 28) 510 #define CCM_ANALOG_MISC2_REG1_STEP_TIME __BITS(27, 26) 511 #define CCM_ANALOG_MISC2_REG0_STEP_TIME __BITS(25, 24) 512 #define CCM_ANALOG_MISC2_AUDIO_DIV_MSB __BIT(23) 513 #define CCM_ANALOG_MISC2_REG2_OK __BIT(22) 514 #define CCM_ANALOG_MISC2_REG2_ENABLE_BO __BIT(21) 515 #define CCM_ANALOG_MISC2_REG2_BO_STATUS __BIT(19) 516 #define CCM_ANALOG_MISC2_REG2_BO_OFFSET __BITS(18, 16) 517 #define CCM_ANALOG_MISC2_AUDIO_DIV_LSB __BIT(15) 518 #define CCM_ANALOG_MISC2_REG1_ENABLE_BO __BIT(13) 519 #define CCM_ANALOG_MISC2_REG1_BO_STATUS __BIT(11) 520 #define CCM_ANALOG_MISC2_REG1_BO_OFFSET __BITS(10, 8) 521 #define CCM_ANALOG_MISC2_PLL3_DISABLE __BIT(7) 522 #define CCM_ANALOG_MISC2_REG0_ENABLE_BO __BIT(5) 523 #define CCM_ANALOG_MISC2_REG0_BO_STATUS __BIT(3) 524 #define CCM_ANALOG_MISC2_REG0_BO_OFFSET __BITS(2, 0) 525 526 #define CCM_TEMPMON_TEMPSENSE0 0x00000180 527 #define CCM_TEMPMON_TEMPSENSE0_ALARM_VALUE __BIT(31, 30) 528 #define CCM_TEMPMON_TEMPSENSE0_TEMP_CNT __BITS(19, 8) 529 #define CCM_TEMPMON_TEMPSENSE0_FINISHED __BIT(2) 530 #define CCM_TEMPMON_TEMPSENSE0_MEASURE_TEMP __BIT(1) 531 #define CCM_TEMPMON_TEMPSENSE0_POWER_DOWN __BIT(0) 532 #define CCM_TEMPMON_TEMPSENSE1 0x00000180 533 #define CCM_TEMPMON_TEMPSENSE1_MEASURE_FREQ __BITS(15, 0) 534 535 #define USB_ANALOG_USB1_VBUS_DETECT 0x000001a0 536 #define USB_ANALOG_USB1_CHRG_DETECT 0x000001b0 537 #define USB_ANALOG_USB_CHRG_DETECT_EN_B __BIT(20) 538 #define USB_ANALOG_USB_CHRG_DETECT_CHK_CHRG_B __BIT(19) 539 #define USB_ANALOG_USB_CHRG_DETECT_CHK_CHK_CONTACT __BIT(18) 540 #define USB_ANALOG_USB1_VBUS_DETECT_STAT 0x000001c0 541 #define USB_ANALOG_USB1_CHRG_DETECT_STAT 0x000001d0 542 #define USB_ANALOG_USB1_MISC 0x000001f0 543 #define USB_ANALOG_USB2_VBUS_DETECT 0x00000200 544 #define USB_ANALOG_USB2_CHRG_DETECT 0x00000210 545 #define USB_ANALOG_USB2_VBUS_DETECT_STAT 0x00000220 546 #define USB_ANALOG_USB2_CHRG_DETECT_STAT 0x00000230 547 #define USB_ANALOG_USB2_MISC 0x00000250 548 549 #define USB_ANALOG_DIGPROG 0x00000260 550 #define USB_ANALOG_DIGPROG_SOLOLITE 0x00000280 551 #define USB_ANALOG_DIGPROG_MAJOR __BITS(23, 8) 552 #define USB_ANALOG_DIGPROG_MINOR __BITS(7, 0) 553 554 #endif /* _ARM_NXP_IMX6_CCMREG_H */ 555
Indexes created Fri Sep 26 20:09:58 GMT 2025