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    Searched defs:INSTRUCTION (Results 1 - 10 of 10) sorted by relevancy

  /src/external/gpl3/gdb/dist/sim/microblaze/
interp.c 149 fprintf (stderr, "Unknown instruction 0x%04x", inst);
175 #define INSTRUCTION(NAME, OPCODE, TYPE, ACTION) \
181 #undef INSTRUCTION
215 /* For branch instructions handle the instruction in the delay slot */
224 fprintf (stderr, "Unknown instruction 0x%04x", inst);
250 #define INSTRUCTION(NAME, OPCODE, TYPE, ACTION) \
255 #undef INSTRUCTION
  /src/external/gpl3/gdb.old/dist/sim/microblaze/
interp.c 149 fprintf (stderr, "Unknown instruction 0x%04x", inst);
175 #define INSTRUCTION(NAME, OPCODE, TYPE, ACTION) \
181 #undef INSTRUCTION
215 /* For branch instructions handle the instruction in the delay slot */
224 fprintf (stderr, "Unknown instruction 0x%04x", inst);
250 #define INSTRUCTION(NAME, OPCODE, TYPE, ACTION) \
255 #undef INSTRUCTION
  /src/external/apache2/llvm/dist/llvm/lib/IR/
IntrinsicInst.cpp 1 //===-- InstrinsicInst.cpp - Intrinsic Instruction Wrappers ---------------===//
12 // All intrinsic function calls are instances of the call instruction, so these
19 // cast instruction needs to be stripped away.
255 #define INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC) \
266 #define INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC) \
275 #define INSTRUCTION(NAME, NARGS, ROUND_MODE, INTRINSIC) \
363 #define HANDLE_VP_TO_OPC(OPC) FunctionalOC = Instruction::OPC;
376 #define HANDLE_VP_TO_OPC(OPC) case Instruction::OPC:
424 Instruction::BinaryOps BinaryOpIntrinsic::getBinaryOp() const {
430 return Instruction::Add
    [all...]
Function.cpp 32 #include "llvm/IR/Instruction.h"
447 #define INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC) \
451 #undef INSTRUCTION
1676 if (const auto *FI = dyn_cast<Instruction>(FU)) {
1730 for (const Instruction &I : instructions(this))
IRBuilder.cpp 75 Instruction *FMFSource = nullptr,
474 Instruction *IRBuilderBase::CreateNoAliasScopeDeclaration(Value *Scope) {
755 CallInst *IRBuilderBase::CreateGCResult(Instruction *Statepoint,
767 CallInst *IRBuilderBase::CreateGCRelocate(Instruction *Statepoint,
784 Instruction *FMFSource,
793 Instruction *FMFSource,
803 Instruction *FMFSource,
811 Intrinsic::ID ID, Value *L, Value *R, Instruction *FMFSource,
831 if (Instruction::isBinaryOp(Opc)) {
833 return CreateBinOp(static_cast<Instruction::BinaryOps>(Opc)
    [all...]
Verifier.cpp 34 // * It is illegal to have a ret instruction that returns a value that does not
37 // * A landing pad is defined by a landingpad instruction, and can be jumped to
38 // only by the unwind edge of an invoke instruction.
39 // * A landingpad instruction must be the first non-PHI instruction in the
85 #include "llvm/IR/Instruction.h"
155 if (isa<Instruction>(V)) {
289 /// instruction has an operand that is an instruction in the same block.
290 SmallPtrSet<Instruction *, 16> InstsInThisBlock
    [all...]
  /src/external/gpl3/gdb/dist/sim/pru/
interp.c 328 /* Handle XIN instruction addressing the MAC peripheral. */
353 /* Handle XIN instruction. */
400 /* Handle XOUT instruction addressing the MAC peripheral. */
461 /* Handle XOUT instruction. */
492 /* Handle XCHG instruction. */
538 /* Simulate one instruction. */
549 /* Fetch the initial instruction that we'll decode. */
557 sim_io_eprintf (sd, "Unknown instruction 0x%04x\n", inst);
577 #define INSTRUCTION(NAME, ACTION) \
582 #undef INSTRUCTION
    [all...]
  /src/external/gpl3/gdb.old/dist/sim/pru/
interp.c 328 /* Handle XIN instruction addressing the MAC peripheral. */
353 /* Handle XIN instruction. */
400 /* Handle XOUT instruction addressing the MAC peripheral. */
461 /* Handle XOUT instruction. */
492 /* Handle XCHG instruction. */
538 /* Simulate one instruction. */
549 /* Fetch the initial instruction that we'll decode. */
557 sim_io_eprintf (sd, "Unknown instruction 0x%04x\n", inst);
577 #define INSTRUCTION(NAME, ACTION) \
582 #undef INSTRUCTION
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
IRTranslator.cpp 125 /// Verify that every instruction created has the same DILocation as the
126 /// instruction being translated.
128 const Instruction *CurrInst = nullptr;
134 const Instruction *getCurrentInst() const { return CurrInst; }
135 void setCurrentInst(const Instruction *Inst) { CurrInst = Inst; }
142 assert(getCurrentInst() && "Inserted instruction without a current MI");
253 Align IRTranslator::getMemOpAlign(const Instruction &I) {
290 if (isa<Instruction>(U)) {
291 const Instruction &I = cast<Instruction>(U)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
SelectionDAGBuilder.cpp 309 const Instruction *I = dyn_cast_or_null<Instruction>(V);
1103 void SelectionDAGBuilder::visit(const Instruction &I) {
1109 // Increase the SDNodeOrder if dealing with a non-debug instruction.
1132 default: llvm_unreachable("Unknown instruction type encountered!");
1133 // Build the switch statement using the Instruction.def file.
1135 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
1136 #include "llvm/IR/Instruction.def"
1272 // a non-instruction is seen, such as a constant expression or global
1274 while (isa<Instruction>(V))
    [all...]

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