1 /* $NetBSD: s3c2xx0reg.h,v 1.7 2014/03/17 10:27:46 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2002, 2003 Fujitsu Component Limited 5 * Copyright (c) 2002, 2003 Genetec Corporation 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Neither the name of The Fujitsu Component Limited nor the name of 17 * Genetec corporation may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC 21 * CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 22 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC 25 * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 29 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 */ 34 35 36 /* 37 * Register definitions common to S3C2800 and S3C24[01]0 38 */ 39 #ifndef _ARM_S3C2XX0_S3C2XX0REG_H_ 40 #define _ARM_S3C2XX0_S3C2XX0REG_H_ 41 42 /* UART */ 43 /* 44 * S3C2800, 2410 and 2400 have a common built-in UART block. However, 45 * there are small diffs in bit position of some registers. 46 * Following definitions can be found in s3c{2800,24x0}reg.h for 47 * that reason. 48 * 49 * UMCON_AFC (Auto flow control) 50 * UMSTAT_DCTS (CTS change) 51 */ 52 53 #define SSCOM_ULCON 0x00 /* UART line control */ 54 #define ULCON_IR (1<<6) 55 #define ULCON_PARITY_SHIFT 3 56 #define ULCON_PARITY_NONE (0<<ULCON_PARITY_SHIFT) 57 #define ULCON_PARITY_ODD (4<<ULCON_PARITY_SHIFT) 58 #define ULCON_PARITY_EVEN (5<<ULCON_PARITY_SHIFT) 59 #define ULCON_PARITY_ONE (6<<ULCON_PARITY_SHIFT) 60 #define ULCON_PARITY_ZERO (7<<ULCON_PARITY_SHIFT) 61 #define ULCON_STOP (1<<2) 62 #define ULCON_LENGTH_5 0 63 #define ULCON_LENGTH_6 1 64 #define ULCON_LENGTH_7 2 65 #define ULCON_LENGTH_8 3 66 #define SSCOM_UCON 0x04 /* UART control */ 67 #define UCON_TXINT_TYPE (1<<9) /* Tx interrupt. 0=pulse,1=level */ 68 #define UCON_TXINT_TYPE_LEVEL UCON_TXINT_TYPE 69 #define UCON_TXINT_TYPE_PULSE 0 70 #define UCON_RXINT_TYPE (1<<8) /* Rx interrupt */ 71 #define UCON_RXINT_TYPE_LEVEL UCON_RXINT_TYPE 72 #define UCON_RXINT_TYPE_PULSE 0 73 #define UCON_TOINT (1<<7) /* Rx timeout interrupt */ 74 #define UCON_ERRINT (1<<6) /* receive error interrupt */ 75 #define UCON_LOOP (1<<5) /* loopback */ 76 #define UCON_SBREAK (1<<4) /* send break */ 77 #define UCON_TXMODE_DISABLE (0<<2) 78 #define UCON_TXMODE_INT (1<<2) 79 #define UCON_TXMODE_DMA (2<<2) 80 #define UCON_TXMODE_MASK (3<<2) 81 #define UCON_RXMODE_DISABLE (0<<0) 82 #define UCON_RXMODE_INT (1<<0) 83 #define UCON_RXMODE_DMA (2<<0) 84 #define UCON_RXMODE_MASK (3<<0) 85 #define SSCOM_UFCON 0x08 /* FIFO control */ 86 #define UFCON_TXTRIGGER_0 (0<<6) 87 #define UFCON_TXTRIGGER_4 (1<<6) 88 #define UFCON_TXTRIGGER_8 (2<<6) 89 #define UFCON_TXTRIGGER_16 (3<<6) 90 #define UFCON_RXTRIGGER_4 (0<<4) 91 #define UFCON_RXTRIGGER_8 (1<<4) 92 #define UFCON_RXTRIGGER_12 (2<<4) 93 #define UFCON_RXTRIGGER_16 (3<<4) 94 #define UFCON_TXFIFO_RESET (1<<2) 95 #define UFCON_RXFIFO_RESET (1<<1) 96 #define UFCON_FIFO_ENABLE (1<<0) 97 #define SSCOM_UMCON 0x0c /* MODEM control */ 98 /* UMCON_AFC is defined in s3c{2800,24x0}reg.h */ 99 #define UMCON_RTS (1<<0) /* Request to send */ 100 #define SSCOM_UTRSTAT 0x10 /* Status register */ 101 #define UTRSTAT_TXSHIFTER_EMPTY (1<<2) 102 #define UTRSTAT_TXEMPTY (1<<1) /* TX fifo or buffer empty */ 103 #define UTRSTAT_RXREADY (1<<0) /* RX fifo or buffer is not empty */ 104 #define SSCOM_UERSTAT 0x14 /* Error status register */ 105 #define UERSTAT_BREAK (1<<3) /* Break signal */ 106 #define UERSTAT_FRAME (1<<2) /* Frame error */ 107 #define UERSTAT_PARITY (1<<1) /* Parity error */ 108 #define UERSTAT_OVERRUN (1<<0) /* Overrun */ 109 #define UERSTAT_ALL_ERRORS (UERSTAT_OVERRUN|UERSTAT_BREAK|UERSTAT_FRAME|UERSTAT_PARITY) 110 #define SSCOM_UFSTAT 0x18 /* Fifo status register */ 111 #define UFSTAT_TXFULL (1<<9) /* Tx fifo full */ 112 #define UFSTAT_RXFULL (1<<8) /* Rx fifo full */ 113 #define UFSTAT_TXCOUNT_SHIFT 4 /* TX FIFO count */ 114 #define UFSTAT_TXCOUNT (0x0f<<UFSTAT_TXCOUNT_SHIFT) 115 #define UFSTAT_RXCOUNT_SHIFT 0 /* RX FIFO count */ 116 #define UFSTAT_RXCOUNT (0x0f<<UFSTAT_RXCOUNT_SHIFT) 117 #define SSCOM_UMSTAT 0x1c /* Modem status register */ 118 /* UMSTAT_DCTS is defined in s3c{2800,24x0}reg.h */ 119 #define UMSTAT_CTS (1<<0) /* Clear to send */ 120 #if _BYTE_ORDER == _LITTLE_ENDIAN 121 #define SSCOM_UTXH 0x20 /* Transmit data register */ 122 #define SSCOM_URXH 0x24 /* Receive data register */ 123 #else 124 #define SSCOM_UTXH 0x23 /* Transmit data register */ 125 #define SSCOM_URXH 0x27 /* Receive data register */ 126 #endif 127 #define SSCOM_UBRDIV 0x28 /* baud-reate divisor */ 128 #define SSCOM_SIZE 0x2c 129 130 /* Interrupt controller (Common to S3c2800/2400X/2410X) */ 131 #define INTCTL_SRCPND 0x00 /* Interrupt request status */ 132 #define INTCTL_INTMOD 0x04 /* Interrupt mode (FIQ/IRQ) */ 133 #define INTCTL_INTMSK 0x08 /* Interrupt mask */ 134 135 #endif /* _ARM_S3C2XX0_S3C2XX0REG_H_ */ 136
Indexes created Tue Sep 23 07:09:52 GMT 2025