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      1 /* $NetBSD: imx51reg.h,v 1.8 2019/08/19 11:41:36 hkenken Exp $ */
      2 /*-
      3  * Copyright (c) 2007 The NetBSD Foundation, Inc.
      4  * All rights reserved.
      5  *
      6  * This code is derived from software contributed to The NetBSD Foundation
      7  * by Matt Thomas.
      8  *
      9  * Redistribution and use in source and binary forms, with or without
     10  * modification, are permitted provided that the following conditions
     11  * are met:
     12  * 1. Redistributions of source code must retain the above copyright
     13  *    notice, this list of conditions and the following disclaimer.
     14  * 2. Redistributions in binary form must reproduce the above copyright
     15  *    notice, this list of conditions and the following disclaimer in the
     16  *    documentation and/or other materials provided with the distribution.
     17  *
     18  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     19  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     20  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     21  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     22  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     23  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     24  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     25  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     26  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     27  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     28  * POSSIBILITY OF SUCH DAMAGE.
     29  */
     30 
     31 #ifndef _ARM_IMX_IMX51REG_H_
     32 #define	_ARM_IMX_IMX51REG_H_
     33 
     34 #ifdef IMX50
     35 #define	TZIC_BASE	0x0fffc000
     36 #define	APB_BASE	0x40000000
     37 #define	AIPSTZ1_BASE	0x50000000
     38 #define	AIPSTZ2_BASE	0x60000000
     39 #define	CSD0DDR_BASE	0x70000000
     40 #else
     41 #define	TZIC_BASE	0xe0000000
     42 #define	AIPSTZ1_BASE	0x70000000
     43 #define	AIPSTZ2_BASE	0x80000000
     44 #define	CSD0DDR_BASE	0x90000000
     45 #define	CSD1DDR_BASE	0xa0000000
     46 #define	CSDDDR_SIZE	0x10000000	/* 256MiB */
     47 #define	CS0_BASE	0xb0000000
     48 #define	CS0_SIZE	0x08000000	/* 128MiB */
     49 #define	CS1_BASE	0xb8000000
     50 #define	CS1_SIZE	0x08000000	/* 128MiB */
     51 #define	CS2_BASE	0xc0000000
     52 #define	CS2_SIZE	0x08000000	/* 128MiB */
     53 #define	CS3_BASE	0xc8000000
     54 #define	CS3_SIZE	0x04000000	/* 64MiB */
     55 #define	CS4_BASE	0xcc000000
     56 #define	CS4_SIZE	0x02000000	/* 32MiB */
     57 #define	CS5_BASE	0xcefe0000
     58 #define	CS5_SIZE	0x00010000	/* 32MiB */
     59 #define	NAND_FLASH_BASE	0xcfff0000	/* internal buffer */
     60 #define	NAND_FLASH_SIZE	0x00010000
     61 
     62 #define	GPU2D_BASE	0xd0000000
     63 #define	GPU2D_SIZE	0x10000000
     64 #endif
     65 
     66 #define	BOOTROM_BASE	0x00000000
     67 #define	BOOTROM_SIZE	0x9000
     68 
     69 #define	SCCRAM_BASE	0x1ffe0000
     70 #define	SCCRAM_SIZE	0x20000
     71 
     72 #define	GPUMEM_BASE	0x20000000
     73 #define	GPUMEM_SIZE	0x20000
     74 
     75 #define	GPU_BASE	0x30000000
     76 #define	GPU_SIZE	0x10000000
     77 
     78 #ifdef IMX50
     79 #define EPDC_BASE	(APB_BASE + 0x01010000)
     80 #define EPDC_SIZE	0x2000
     81 #endif
     82 
     83 /* Image Prossasing Unit */
     84 #define	IPU_BASE	0x40000000
     85 #define	IPU_CM_BASE	(IPU_BASE + 0x1e000000)
     86 #define	IPU_CM_SIZE	0x8000
     87 #define	IPU_IDMAC_BASE	(IPU_BASE + 0x1e008000)
     88 #define	IPU_IDMAC_SIZE	0x8000
     89 #define	IPU_DP_BASE	(IPU_BASE + 0x1e018000)
     90 #define	IPU_DP_SIZE	0x8000
     91 #define	IPU_IC_BASE	(IPU_BASE + 0x1e020000)
     92 #define	IPU_IC_SIZE	0x8000
     93 #define	IPU_IRT_BASE	(IPU_BASE + 0x1e028000)
     94 #define	IPU_IRT_SIZE	0x8000
     95 #define	IPU_CSI0_BASE	(IPU_BASE + 0x1e030000)
     96 #define	IPU_CSI0_SIZE	0x8000
     97 #define	IPU_CSI1_BASE	(IPU_BASE + 0x1e038000)
     98 #define	IPU_CSI1_SIZE	0x8000
     99 #define	IPU_DI0_BASE	(IPU_BASE + 0x1e040000)
    100 #define	IPU_DI0_SIZE	0x8000
    101 #define	IPU_DI1_BASE	(IPU_BASE + 0x1e048000)
    102 #define	IPU_DI1_SIZE	0x8000
    103 #define	IPU_SMFC_BASE	(IPU_BASE + 0x1e050000)
    104 #define	IPU_SMFC_SIZE	0x8000
    105 #define	IPU_DC_BASE	(IPU_BASE + 0x1e058000)
    106 #define	IPU_DC_SIZE	0x8000
    107 #define	IPU_DMFC_BASE	(IPU_BASE + 0x1e060000)
    108 #define	IPU_DMFC_SIZE	0x8000
    109 #define	IPU_VDI_BASE	(IPU_BASE + 0x1e068000)
    110 #define	IPU_VDI_SIZE	0x8000
    111 #define	IPU_CPMEM_BASE	(IPU_BASE + 0x1f000000)
    112 #define	IPU_CPMEM_SIZE	0x20000
    113 #define	IPU_LUT_BASE	(IPU_BASE + 0x1f020000)
    114 #define	IPU_LUT_SIZE	0x20000
    115 #define	IPU_SRM_BASE	(IPU_BASE + 0x1f040000)
    116 #define	IPU_SRM_SIZE	0x20000
    117 #define	IPU_TPM_BASE	(IPU_BASE + 0x1f060000)
    118 #define	IPU_TPM_SIZE	0x20000
    119 #define	IPU_DCTMPL_BASE	(IPU_BASE + 0x1f080000)
    120 #define	IPU_DCTMPL_SIZE	0x20000
    121 
    122 #define	DEBUGROM_BASE	0x60000000
    123 #define	DEBUGROM_SIZE	0x1000
    124 
    125 #define	ESDHC1_BASE	(AIPSTZ1_BASE + 0x00004000)
    126 #define	ESDHC2_BASE	(AIPSTZ1_BASE + 0x00008000)
    127 #define	ESDHC3_BASE	(AIPSTZ1_BASE + 0x00020000)
    128 #define	ESDHC4_BASE	(AIPSTZ1_BASE + 0x00024000)
    129 #define	ESDHC_SIZE	0x4000
    130 
    131 #define PWM1_BASE	(AIPSTZ1_BASE + 0x03fb4000)
    132 #define PWM2_BASE	(AIPSTZ1_BASE + 0x03fb8000)
    133 
    134 #define	UART1_BASE	(AIPSTZ1_BASE + 0x03fbc000)
    135 #define	UART2_BASE	(AIPSTZ1_BASE + 0x03fc0000)
    136 #define	UART3_BASE	(AIPSTZ1_BASE + 0x0000c000)
    137 /* register definitions in imxuartreg.h */
    138 
    139 #define	CCMC_BASE	(AIPSTZ1_BASE + 0x03fd4000)
    140 
    141 #define	ECSPI1_BASE	(AIPSTZ1_BASE + 0x00010000)
    142 #define	ECSPI2_BASE	(AIPSTZ2_BASE + 0x03fac000)
    143 
    144 #define	SSI1_BASE	(AIPSTZ2_BASE + 0x03fcc000)
    145 #define	SSI2_BASE	(AIPSTZ1_BASE + 0x00014000)
    146 #define	SSI3_BASE	(AIPSTZ2_BASE + 0x03fe8000)
    147 /* register definitions in imxssireg.h */
    148 
    149 #define	SPDIF_BASE	(AIPSTZ1_BASE + 0x00028000)
    150 #define	SPDIF_SIZE	0x4000
    151 
    152 #define	PATA_UDMA_BASE	(AIPSTZ1_BASE + 0x00030000)
    153 #define	PATA_UDMA_SIZE	0x4000
    154 #define	PATA_PIO_BASE	(AIPSTZ2_BASE + 0x03fe0000)
    155 #define	PATA_PIO_SIZE	0x4000
    156 
    157 #define	SLM_BASE	(AIPSTZ1_BASE + 0x00034000)
    158 #define	SLM_SIZE	0x4000
    159 
    160 #ifdef IMX50
    161 #define	I2C3_BASE	(AIPSTZ1_BASE + 0x00038000)
    162 #define	I2C3_SIZE	0x4000
    163 #else
    164 #define	HSI2C_BASE	(AIPSTZ1_BASE + 0x00038000)
    165 #define	HSI2C_SIZE	0x4000
    166 #endif
    167 
    168 #define	SPBA_BASE	(AIPSTZ1_BASE + 0x0003c000)
    169 #define	SPBA_SIZE	0x4000
    170 
    171 #define	USBOH3_BASE	(AIPSTZ1_BASE + 0x03f80000)
    172 #define	USBOH3_PL301_BASE	(AIPSTZ1_BASE + 0x03fc4000)
    173 #define	USBOH3_EHCI_SIZE	0x200
    174 #define	USBOH3_OTG	0x000
    175 #define	USBOH3_EHCI(n)	(USBOH3_EHCI_SIZE*(n))	/* n=1,2,3 */
    176 
    177 /* USB_CTRL register */
    178 #define	USBOH3_USBCTRL			0x800
    179 #define	 USBCTRL_OWIR			__BIT(31)	/* OTG Wakeup interrupt request */
    180 #define	 USBCTRL_OSIC			__BITS(29,30)	/* OTG Serial interface configuration */
    181 #define	 USBCTRL_OUIE			__BIT(28)	/* OTG Wake-up interrupt enable */
    182 #define	 USBCTRL_OBPAL			__BITS(25,26)	/* OTG Bypass value */
    183 #define	 USBCTRL_OPM			__BIT(24)	/* OTG Power Mask */
    184 #define	 USBCTRL_ICVOL			__BIT(23)	/* Host1 IC_USB voltage status */
    185 #define	 USBCTRL_ICTPIE			__BIT(19)	/* IC USB TP interrupt enable */
    186 #define	 USBCTRL_UBPCKE			__BIT(18)	/* Bypass clock enable */
    187 #define	 USBCTRL_H1TCKOEN		__BIT(17)	/* Host1 ULPO PHY clock enable */
    188 #define	 USBCTRL_ICTPC			__BIT(16)	/* Clear IC TP interrupt flag */
    189 #define	 USBCTRL_H1WIR			__BIT(15)	/* Host1 wakeup interrupt request */
    190 #define	 USBCTRL_H1SIC			__BITS(13,14)	/* Host1 serial interface config */
    191 #define	 USBCTRL_H1UIE			__BIT(12)	/* Host1 ILPI interrupt enable */
    192 #define	 USBCTRL_H1WIE			__BIT(11)	/* Host1 wakeup interrupt enable */
    193 #define	 USBCTRL_H1BPVAL		__BITS(9,10)	/* Host1 bypass value */
    194 #define	 USBCTRL_H1PM			__BIT(8)	/* Host1 power mask */
    195 #define	 USBCTRL_OHSTLL			__BIT(7)	/* OTG ULPI TLL enable */
    196 #define	 USBCTRL_H1HSTLL		__BIT(6)	/* Host1 ULPI TLL enable */
    197 #define	 USBCTRL_H1DISFSTTL		__BIT(4)	/* Host1 serial TLL disable */
    198 #define	 USBCTRL_OTCKOEN		__BIT(1)	/* OTG ULPI PHY clock enable */
    199 #define	 USBCTRL_BPE			__BIT(0)	/* Bypass enable */
    200 #define	USBOH3_OTGMIRROR		0x804
    201 #define	USBOH3_PHYCTRL0			0x808
    202 #define	 PHYCTRL0_VLOAD			__BIT(31)
    203 #define	 PHYCTRL0_VCONTROL		__BITS(27,30)
    204 #define	 PHYCTRL0_CONF2			__BIT(26)
    205 #define	 PHYCTRL0_CONF3			__BIT(25)
    206 #define	 PHYCTRL0_CHGRDETEN		__BIT(24)
    207 #define	 PHYCTRL0_CHGRDETON		__BIT(23)
    208 #define	 PHYCTRL0_VSTATUS		__BITS(15,22)
    209 #define	 PHYCTRL0_SUSPENDM		__BIT(12)
    210 #define	 PHYCTRL0_RESET			__BIT(11)
    211 #define	 PHYCTRL0_UTMI_ON_CLOCK		__BIT(10)
    212 #define	 PHYCTRL0_OTG_OVER_CUR_POL	__BIT(9)
    213 #define	 PHYCTRL0_OTG_OVER_CUR_DIS	__BIT(8)
    214 #define	 PHYCTRL0_OTG_XCVR_CLK_SEL	__BIT(7)
    215 #define	 PHYCTRL0_H1_OVER_CUR_POL	__BIT(6)
    216 #define	 PHYCTRL0_H1_OVER_CUR_DIS	__BIT(5)
    217 #define	 PHYCTRL0_H1_XCVR_CLK_SEL	__BIT(4)
    218 #define	 PHYCTRL0_PWR_POL		__BIT(3)
    219 #define	 PHYCTRL0_CHRGDET		__BIT(2)
    220 #define	 PHYCTRL0_CHRGDET_INT_EN	__BIT(1)
    221 #define	 PHYCTRL0_CHRGDET_INT_FLG	__BIT(0)
    222 #define	USBOH3_PHYCTRL1			0x80c
    223 #define	 PHYCTRL1_PLLDIVVALUE_MASK	__BITS(0,1)
    224 #define	 PHYCTRL1_PLLDIVVALUE_19MHZ	0	/* 19.2MHz */
    225 #define	 PHYCTRL1_PLLDIVVALUE_24MHZ	1
    226 #define	 PHYCTRL1_PLLDIVVALUE_26MHZ	2
    227 #define	 PHYCTRL1_PLLDIVVALUE_27MHZ	3
    228 #define	USBOH3_USBCTRL1			0x810
    229 #define	 USBCTRL1_UH3_EXT_CLK_EN	__BIT(27)
    230 #define	 USBCTRL1_UH2_EXT_CLK_EN	__BIT(26)
    231 #define	 USBCTRL1_UH1_EXT_CLK_EN	__BIT(25)
    232 #define	 USBCTRL1_OTG_EXT_CLK_EN	__BIT(24)
    233 #define	USBOH3_USBCTRL2			0x814
    234 #define	USBOH3_USBCTRL3			0x818
    235 #define	USBOH3_UH1_PHY_CTRL_0		0x81c
    236 #define	USBOH3_UH1_PHY_CTRL_1		0x820
    237 #define	USBOH3_USB_CLKONOFF_CTRL  	0x824
    238 #define	 USB_CLKONOFF_CTRL_H1_AHBCLK_OFF	__BIT(18)
    239 #define	 USB_CLKONOFF_CTRL_OTG_AHBCLK_OFF	__BIT(17)
    240 
    241 #define	USBOH3_SIZE	0x4000
    242 
    243 /* GPIO module */
    244 
    245 #define	GPIO_BASE(n)				      \
    246 	(AIPSTZ1_BASE + (((n) <= 4) ?		      \
    247 	    0x03f84000 + 0x4000 * ((n) - 1) :	      \
    248 	    0x03fdc000 + 0x4000 * ((n) - 5)))
    249 
    250 #define	GPIO1_BASE	GPIO_BASE(1)
    251 #define	GPIO2_BASE	GPIO_BASE(2)
    252 #define	GPIO3_BASE	GPIO_BASE(3)
    253 #define	GPIO4_BASE	GPIO_BASE(4)
    254 #define	GPIO5_BASE	GPIO_BASE(5)
    255 #define	GPIO6_BASE	GPIO_BASE(6)
    256 
    257 #ifdef IMX50
    258 #define	GPIO_NGROUPS		6
    259 #else
    260 #define	GPIO_NGROUPS		4
    261 #endif
    262 
    263 #define	KPP_BASE	(AIPSTZ1_BASE + 0x03f94000)
    264 /* register definitions in imxkppreg.h */
    265 
    266 #define	WDOG1_BASE	(AIPSTZ1_BASE + 0x03f98000)
    267 #define	WDOG2_BASE	(AIPSTZ1_BASE + 0x03f9c000)
    268 #define	WDOG_SIZE	0x4000
    269 
    270 #define	GPT_BASE	(AIPSTZ1_BASE + 0x03fa0000)
    271 #define	GPT_SIZE	0x4000
    272 
    273 #define	SRTC_BASE	(AIPSTZ1_BASE + 0x03fa4000)
    274 #define	SRTC_SIZE	0x4000
    275 
    276 /* IO multiplexor */
    277 #define	IOMUXC_BASE	(AIPSTZ1_BASE + 0x03fa8000)
    278 #define	IOMUXC_SIZE	0x4000
    279 
    280 #define	IOMUXC_MUX_CTL		0x001c		/* multiprex control */
    281 #define	 IOMUX_CONFIG_SION	__BIT(4)
    282 #define	 IOMUX_CONFIG_ALT0	(0)
    283 #define	 IOMUX_CONFIG_ALT1	(1)
    284 #define	 IOMUX_CONFIG_ALT2	(2)
    285 #define	 IOMUX_CONFIG_ALT3	(3)
    286 #define	 IOMUX_CONFIG_ALT4	(4)
    287 #define	 IOMUX_CONFIG_ALT5	(5)
    288 #define	 IOMUX_CONFIG_ALT6	(6)
    289 #define	 IOMUX_CONFIG_ALT7	(7)
    290 #define	IOMUXC_PAD_CTL		0x03f0		/* pad control */
    291 #define	 PAD_CTL_HVE		__BIT(13)
    292 #define	 PAD_CTL_DDR_INPUT	__BIT(9)
    293 #define	 PAD_CTL_HYS		__BIT(8)
    294 #define	 PAD_CTL_PKE		__BIT(7)
    295 #define	 PAD_CTL_PUE		__BIT(6)
    296 #define	 PAD_CTL_PULL		(PAD_CTL_PKE|PAD_CTL_PUE)
    297 #define	 PAD_CTL_KEEPER		(PAD_CTL_PKE|0)
    298 #define	 PAD_CTL_PUS_MASK	__BITS(5, 4)
    299 #define	 PAD_CTL_PUS_100K_PD	__SHIFTIN(0x0, PAD_CTL_PUS_MASK)
    300 #define	 PAD_CTL_PUS_47K_PU	__SHIFTIN(0x1, PAD_CTL_PUS_MASK)
    301 #define	 PAD_CTL_PUS_100K_PU	__SHIFTIN(0x2, PAD_CTL_PUS_MASK)
    302 #define	 PAD_CTL_PUS_22K_PU	__SHIFTIN(0x3, PAD_CTL_PUS_MASK)
    303 #define	 PAD_CTL_ODE		__BIT(3)	/* opendrain */
    304 #define	 PAD_CTL_DSE_MASK	__BITS(2, 1)
    305 #define	 PAD_CTL_DSE_LOW	__SHIFTIN(0x0, PAD_CTL_DSE_MASK)
    306 #define	 PAD_CTL_DSE_MID	__SHIFTIN(0x1, PAD_CTL_DSE_MASK)
    307 #define	 PAD_CTL_DSE_HIGH	__SHIFTIN(0x2, PAD_CTL_DSE_MASK)
    308 #define	 PAD_CTL_DSE_MAX	__SHIFTIN(0x3, PAD_CTL_DSE_MASK)
    309 #define	 PAD_CTL_SRE		__BIT(0)
    310 #define	IOMUXC_INPUT_CTL	0x08c4		/* input control */
    311 #define	 INPUT_DAISY_0		0
    312 #define	 INPUT_DAISY_1		1
    313 #define	 INPUT_DAISY_2		2
    314 #define	 INPUT_DAISY_3		3
    315 #define	 INPUT_DAISY_4		4
    316 #define	 INPUT_DAISY_5		5
    317 #define	 INPUT_DAISY_6		6
    318 #define	 INPUT_DAISY_7		7
    319 
    320 /*
    321  * IOMUX index
    322  */
    323 #define	IOMUX_PIN_TO_MUX_ADDRESS(pin)	(((pin) >> 16) & 0xffff)
    324 #define	IOMUX_PIN_TO_PAD_ADDRESS(pin)	(((pin) >>  0) & 0xffff)
    325 
    326 #define	IOMUX_PIN(mux_adr, pad_adr)			\
    327 	(((mux_adr) << 16) | (((pad_adr) << 0)))
    328 #define	IOMUX_MUX_NONE	0xffff
    329 #define	IOMUX_PAD_NONE	0xffff
    330 
    331 /* EPIT */
    332 #define	EPIT1_BASE	(AIPSTZ1_BASE + 0x03FAC000)
    333 #define	EPIT2_BASE	(AIPSTZ1_BASE + 0x03FB0000)
    334 /* register definitions in imxepitreg.h */
    335 
    336 #define	PWM1_BASE	(AIPSTZ1_BASE + 0x03fb4000)
    337 #define	PWM2_BASE	(AIPSTZ1_BASE + 0x03fb8000)
    338 #define	PWM_SIZE	0x4000
    339 
    340 #define	SRC_BASE	(AIPSTZ1_BASE + 0x03fd0000)
    341 #define	SRC_SIZE	0x4000
    342 
    343 #define	CCM_BASE	(AIPSTZ1_BASE + 0x03fd4000)
    344 #define	CCM_SIZE	0x4000
    345 
    346 #define	GPC_BASE	(AIPSTZ1_BASE + 0x03fd8000)
    347 #define	GPC_SIZE	0x4000
    348 
    349 #define	AHBMAX_BASE	(AIPSTZ2_BASE + 0x03f94000)
    350 #define	AHBMAX_SIZE	0x4000
    351 
    352 #define	IIM_BASE	(AIPSTZ2_BASE + 0x03f98000)
    353 #define	IIM_SIZE	0x4000
    354 
    355 #define	CSU_BASE	(AIPSTZ2_BASE + 0x03f9c000)
    356 #define	CSU_SIZE	0x4000
    357 
    358 #define	OWIRE_BASE	(AIPSTZ2_BASE + 0x03fa4000)
    359 #define	OWIRE_SIZE	0x4000
    360 
    361 #define	FIRI_BASE	(AIPSTZ2_BASE + 0x03fa8000)
    362 #define	FIRI_SIZE	0x4000
    363 
    364 
    365 #define	SDMA_BASE	(AIPSTZ2_BASE + 0x03fb0000)
    366 #define	SDMA_SIZE	0x4000
    367 /* see imxsdmareg.h for register definitions */
    368 
    369 #define	SCC_BASE	(AIPSTZ2_BASE + 0x03fb4000)
    370 #define	SCC_SIZE	0x4000
    371 
    372 #define	ROMCP_BASE	(AIPSTZ2_BASE + 0x03fb8000)
    373 #define	ROMCP_SIZE	0x4000
    374 
    375 #define	RTIC_BASE	(AIPSTZ2_BASE + 0x03fbc000)
    376 #define	RTIC_SIZE	0x4000
    377 
    378 #define	CSPI_BASE	(AIPSTZ2_BASE + 0x03fc0000)
    379 #define	CSPI_SIZE	0x4000
    380 
    381 #define	I2C1_BASE	(AIPSTZ2_BASE + 0x03fc8000)
    382 #define	I2C2_BASE	(AIPSTZ2_BASE + 0x03fc4000)
    383 #define	I2C_SIZE	0x4000
    384 
    385 #define	AUDMUX_BASE	(AIPSTZ2_BASE + 0x03fd0000)
    386 #define	AUDMUX_SIZE	0x4000
    387 #define	AUDMUX_PTCR(n)	((n - 1) * 0x8)
    388 #define	 PTCR_TFSDIR	(1 << 31)
    389 #define	 PTCR_TFSEL(x)	(((x) & 0x7) << 27)
    390 #define	 PTCR_TCLKDIR	(1 << 26)
    391 #define	 PTCR_TCSEL(x)	(((x) & 0x7) << 22)
    392 #define	 PTCR_RFSDIR	(1 << 21)
    393 #define	 PTCR_RFSEL(x)	(((x) & 0x7) << 17)
    394 #define	 PTCR_RCLKDIR	(1 << 16)
    395 #define	 PTCR_RCSEL(x)	(((x) & 0x7) << 12)
    396 #define	 PTCR_SYN	(1 << 11)
    397 
    398 #define	AUDMUX_PDCR(n)	((n - 1) * 0x8 + 0x4)
    399 #define	 PDCR_RXDSEL(x)	(((x) & 0x7) << 13)
    400 #define	 PDCR_TXRXEN	(1 << 12)
    401 #define	 PDCR_MODE(x)	(((x) & 0x3) << 8)
    402 #define	 PDCR_INMMASK(x)	(((x) & 0xff) << 0)
    403 #define	AUDMUX_CNMCR	0x38
    404 
    405 #define	EMI_BASE	(AIPSTZ2_BASE + 0x03fd8000)
    406 #define	EMI_SIZE	0x4000
    407 
    408 #define	SIM_BASE	(AIPSTZ2_BASE + 0x03fe4000)
    409 #define	SIM_SIZE	0x4000
    410 
    411 #define	FEC_BASE	(AIPSTZ2_BASE + 0x03fec000)
    412 #define	FEC_SIZE	0x4000
    413 #define	TVE_BASE	(AIPSTZ2_BASE + 0x03ff0000)
    414 #define	TVE_SIZE	0x4000
    415 #define	VPU_BASE	(AIPSTZ2_BASE + 0x03ff4000)
    416 #define	VPU_SIZE	0x4000
    417 #define	SAHARA_BASE	(AIPSTZ2_BASE + 0x03ff8000)
    418 #define	SAHARA_SIZE	0x4000
    419 
    420 #define	DPLL_BASE(n)	((AIPSTZ2_BASE + 0x03F80000 + (0x4000 * ((n)-1))))
    421 #define	DPLL_SIZE	0x4000
    422 
    423 #endif /* _ARM_IMX_IMX51REG_H_ */
    424