1 /* 2 * Copyright 2017 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 #ifndef IRIS_CONTEXT_H 24 #define IRIS_CONTEXT_H 25 26 #include "pipe/p_context.h" 27 #include "pipe/p_state.h" 28 #include "util/set.h" 29 #include "util/slab.h" 30 #include "util/u_debug.h" 31 #include "util/u_threaded_context.h" 32 #include "intel/blorp/blorp.h" 33 #include "intel/dev/intel_debug.h" 34 #include "intel/common/intel_l3_config.h" 35 #include "intel/compiler/brw_compiler.h" 36 #include "iris_batch.h" 37 #include "iris_binder.h" 38 #include "iris_fence.h" 39 #include "iris_resource.h" 40 #include "iris_screen.h" 41 42 struct iris_bo; 43 struct iris_context; 44 struct blorp_batch; 45 struct blorp_params; 46 47 #define IRIS_MAX_TEXTURE_BUFFER_SIZE (1 << 27) 48 #define IRIS_MAX_TEXTURE_SAMPLERS 32 49 /* IRIS_MAX_ABOS and IRIS_MAX_SSBOS must be the same. */ 50 #define IRIS_MAX_ABOS 16 51 #define IRIS_MAX_SSBOS 16 52 #define IRIS_MAX_VIEWPORTS 16 53 #define IRIS_MAX_CLIP_PLANES 8 54 #define IRIS_MAX_GLOBAL_BINDINGS 32 55 56 enum iris_param_domain { 57 BRW_PARAM_DOMAIN_BUILTIN = 0, 58 BRW_PARAM_DOMAIN_IMAGE, 59 }; 60 61 enum { 62 DRI_CONF_BO_REUSE_DISABLED, 63 DRI_CONF_BO_REUSE_ALL 64 }; 65 66 #define BRW_PARAM(domain, val) (BRW_PARAM_DOMAIN_##domain << 24 | (val)) 67 #define BRW_PARAM_DOMAIN(param) ((uint32_t)(param) >> 24) 68 #define BRW_PARAM_VALUE(param) ((uint32_t)(param) & 0x00ffffff) 69 #define BRW_PARAM_IMAGE(idx, offset) BRW_PARAM(IMAGE, ((idx) << 8) | (offset)) 70 #define BRW_PARAM_IMAGE_IDX(value) (BRW_PARAM_VALUE(value) >> 8) 71 #define BRW_PARAM_IMAGE_OFFSET(value)(BRW_PARAM_VALUE(value) & 0xf) 72 73 /** 74 * Dirty flags. When state changes, we flag some combination of these 75 * to indicate that particular GPU commands need to be re-emitted. 76 * 77 * Each bit typically corresponds to a single 3DSTATE_* command packet, but 78 * in rare cases they map to a group of related packets that need to be 79 * emitted together. 80 * 81 * See iris_upload_render_state(). 82 */ 83 #define IRIS_DIRTY_COLOR_CALC_STATE (1ull << 0) 84 #define IRIS_DIRTY_POLYGON_STIPPLE (1ull << 1) 85 #define IRIS_DIRTY_SCISSOR_RECT (1ull << 2) 86 #define IRIS_DIRTY_WM_DEPTH_STENCIL (1ull << 3) 87 #define IRIS_DIRTY_CC_VIEWPORT (1ull << 4) 88 #define IRIS_DIRTY_SF_CL_VIEWPORT (1ull << 5) 89 #define IRIS_DIRTY_PS_BLEND (1ull << 6) 90 #define IRIS_DIRTY_BLEND_STATE (1ull << 7) 91 #define IRIS_DIRTY_RASTER (1ull << 8) 92 #define IRIS_DIRTY_CLIP (1ull << 9) 93 #define IRIS_DIRTY_SBE (1ull << 10) 94 #define IRIS_DIRTY_LINE_STIPPLE (1ull << 11) 95 #define IRIS_DIRTY_VERTEX_ELEMENTS (1ull << 12) 96 #define IRIS_DIRTY_MULTISAMPLE (1ull << 13) 97 #define IRIS_DIRTY_VERTEX_BUFFERS (1ull << 14) 98 #define IRIS_DIRTY_SAMPLE_MASK (1ull << 15) 99 #define IRIS_DIRTY_URB (1ull << 16) 100 #define IRIS_DIRTY_DEPTH_BUFFER (1ull << 17) 101 #define IRIS_DIRTY_WM (1ull << 18) 102 #define IRIS_DIRTY_SO_BUFFERS (1ull << 19) 103 #define IRIS_DIRTY_SO_DECL_LIST (1ull << 20) 104 #define IRIS_DIRTY_STREAMOUT (1ull << 21) 105 #define IRIS_DIRTY_VF_SGVS (1ull << 22) 106 #define IRIS_DIRTY_VF (1ull << 23) 107 #define IRIS_DIRTY_VF_TOPOLOGY (1ull << 24) 108 #define IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES (1ull << 25) 109 #define IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES (1ull << 26) 110 #define IRIS_DIRTY_VF_STATISTICS (1ull << 27) 111 #define IRIS_DIRTY_PMA_FIX (1ull << 28) 112 #define IRIS_DIRTY_DEPTH_BOUNDS (1ull << 29) 113 #define IRIS_DIRTY_RENDER_BUFFER (1ull << 30) 114 #define IRIS_DIRTY_STENCIL_REF (1ull << 31) 115 #define IRIS_DIRTY_VERTEX_BUFFER_FLUSHES (1ull << 32) 116 #define IRIS_DIRTY_RENDER_MISC_BUFFER_FLUSHES (1ull << 33) 117 #define IRIS_DIRTY_COMPUTE_MISC_BUFFER_FLUSHES (1ull << 34) 118 119 #define IRIS_ALL_DIRTY_FOR_COMPUTE (IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES | \ 120 IRIS_DIRTY_COMPUTE_MISC_BUFFER_FLUSHES) 121 122 #define IRIS_ALL_DIRTY_FOR_RENDER (~IRIS_ALL_DIRTY_FOR_COMPUTE) 123 124 /** 125 * Per-stage dirty flags. When state changes, we flag some combination of 126 * these to indicate that particular GPU commands need to be re-emitted. 127 * Unlike the IRIS_DIRTY_* flags these are shader stage-specific and can be 128 * indexed by shifting the mask by the shader stage index. 129 * 130 * See iris_upload_render_state(). 131 */ 132 #define IRIS_STAGE_DIRTY_SAMPLER_STATES_VS (1ull << 0) 133 #define IRIS_STAGE_DIRTY_SAMPLER_STATES_TCS (1ull << 1) 134 #define IRIS_STAGE_DIRTY_SAMPLER_STATES_TES (1ull << 2) 135 #define IRIS_STAGE_DIRTY_SAMPLER_STATES_GS (1ull << 3) 136 #define IRIS_STAGE_DIRTY_SAMPLER_STATES_PS (1ull << 4) 137 #define IRIS_STAGE_DIRTY_SAMPLER_STATES_CS (1ull << 5) 138 #define IRIS_STAGE_DIRTY_UNCOMPILED_VS (1ull << 6) 139 #define IRIS_STAGE_DIRTY_UNCOMPILED_TCS (1ull << 7) 140 #define IRIS_STAGE_DIRTY_UNCOMPILED_TES (1ull << 8) 141 #define IRIS_STAGE_DIRTY_UNCOMPILED_GS (1ull << 9) 142 #define IRIS_STAGE_DIRTY_UNCOMPILED_FS (1ull << 10) 143 #define IRIS_STAGE_DIRTY_UNCOMPILED_CS (1ull << 11) 144 #define IRIS_STAGE_DIRTY_VS (1ull << 12) 145 #define IRIS_STAGE_DIRTY_TCS (1ull << 13) 146 #define IRIS_STAGE_DIRTY_TES (1ull << 14) 147 #define IRIS_STAGE_DIRTY_GS (1ull << 15) 148 #define IRIS_STAGE_DIRTY_FS (1ull << 16) 149 #define IRIS_STAGE_DIRTY_CS (1ull << 17) 150 #define IRIS_SHIFT_FOR_STAGE_DIRTY_CONSTANTS 18 151 #define IRIS_STAGE_DIRTY_CONSTANTS_VS (1ull << 18) 152 #define IRIS_STAGE_DIRTY_CONSTANTS_TCS (1ull << 19) 153 #define IRIS_STAGE_DIRTY_CONSTANTS_TES (1ull << 20) 154 #define IRIS_STAGE_DIRTY_CONSTANTS_GS (1ull << 21) 155 #define IRIS_STAGE_DIRTY_CONSTANTS_FS (1ull << 22) 156 #define IRIS_STAGE_DIRTY_CONSTANTS_CS (1ull << 23) 157 #define IRIS_SHIFT_FOR_STAGE_DIRTY_BINDINGS 24 158 #define IRIS_STAGE_DIRTY_BINDINGS_VS (1ull << 24) 159 #define IRIS_STAGE_DIRTY_BINDINGS_TCS (1ull << 25) 160 #define IRIS_STAGE_DIRTY_BINDINGS_TES (1ull << 26) 161 #define IRIS_STAGE_DIRTY_BINDINGS_GS (1ull << 27) 162 #define IRIS_STAGE_DIRTY_BINDINGS_FS (1ull << 28) 163 #define IRIS_STAGE_DIRTY_BINDINGS_CS (1ull << 29) 164 165 #define IRIS_ALL_STAGE_DIRTY_FOR_COMPUTE (IRIS_STAGE_DIRTY_CS | \ 166 IRIS_STAGE_DIRTY_SAMPLER_STATES_CS | \ 167 IRIS_STAGE_DIRTY_UNCOMPILED_CS | \ 168 IRIS_STAGE_DIRTY_CONSTANTS_CS | \ 169 IRIS_STAGE_DIRTY_BINDINGS_CS) 170 171 #define IRIS_ALL_STAGE_DIRTY_FOR_RENDER (~IRIS_ALL_STAGE_DIRTY_FOR_COMPUTE) 172 173 #define IRIS_ALL_STAGE_DIRTY_BINDINGS_FOR_RENDER (IRIS_STAGE_DIRTY_BINDINGS_VS | \ 174 IRIS_STAGE_DIRTY_BINDINGS_TCS | \ 175 IRIS_STAGE_DIRTY_BINDINGS_TES | \ 176 IRIS_STAGE_DIRTY_BINDINGS_GS | \ 177 IRIS_STAGE_DIRTY_BINDINGS_FS) 178 179 #define IRIS_ALL_STAGE_DIRTY_BINDINGS (IRIS_ALL_STAGE_DIRTY_BINDINGS_FOR_RENDER | \ 180 IRIS_STAGE_DIRTY_BINDINGS_CS) 181 182 /** 183 * Non-orthogonal state (NOS) dependency flags. 184 * 185 * Shader programs may depend on non-orthogonal state. These flags are 186 * used to indicate that a shader's key depends on the state provided by 187 * a certain Gallium CSO. Changing any CSOs marked as a dependency will 188 * cause the driver to re-compute the shader key, possibly triggering a 189 * shader recompile. 190 */ 191 enum iris_nos_dep { 192 IRIS_NOS_FRAMEBUFFER, 193 IRIS_NOS_DEPTH_STENCIL_ALPHA, 194 IRIS_NOS_RASTERIZER, 195 IRIS_NOS_BLEND, 196 IRIS_NOS_LAST_VUE_MAP, 197 198 IRIS_NOS_COUNT, 199 }; 200 201 /** @{ 202 * 203 * Program cache keys for state based recompiles. 204 */ 205 206 struct iris_base_prog_key { 207 unsigned program_string_id; 208 }; 209 210 /** 211 * Note, we need to take care to have padding explicitly declared 212 * for key since we will directly memcmp the whole struct. 213 */ 214 struct iris_vue_prog_key { 215 struct iris_base_prog_key base; 216 217 unsigned nr_userclip_plane_consts:4; 218 unsigned padding:28; 219 }; 220 221 struct iris_vs_prog_key { 222 struct iris_vue_prog_key vue; 223 }; 224 225 struct iris_tcs_prog_key { 226 struct iris_vue_prog_key vue; 227 228 uint16_t tes_primitive_mode; 229 230 uint8_t input_vertices; 231 232 bool quads_workaround; 233 234 /** A bitfield of per-patch outputs written. */ 235 uint32_t patch_outputs_written; 236 237 /** A bitfield of per-vertex outputs written. */ 238 uint64_t outputs_written; 239 }; 240 241 struct iris_tes_prog_key { 242 struct iris_vue_prog_key vue; 243 244 /** A bitfield of per-patch inputs read. */ 245 uint32_t patch_inputs_read; 246 247 /** A bitfield of per-vertex inputs read. */ 248 uint64_t inputs_read; 249 }; 250 251 struct iris_gs_prog_key { 252 struct iris_vue_prog_key vue; 253 }; 254 255 struct iris_fs_prog_key { 256 struct iris_base_prog_key base; 257 258 unsigned nr_color_regions:5; 259 bool flat_shade:1; 260 bool alpha_test_replicate_alpha:1; 261 bool alpha_to_coverage:1; 262 bool clamp_fragment_color:1; 263 bool persample_interp:1; 264 bool multisample_fbo:1; 265 bool force_dual_color_blend:1; 266 bool coherent_fb_fetch:1; 267 268 uint8_t color_outputs_valid; 269 uint64_t input_slots_valid; 270 }; 271 272 struct iris_cs_prog_key { 273 struct iris_base_prog_key base; 274 }; 275 276 union iris_any_prog_key { 277 struct iris_base_prog_key base; 278 struct iris_vue_prog_key vue; 279 struct iris_vs_prog_key vs; 280 struct iris_tcs_prog_key tcs; 281 struct iris_tes_prog_key tes; 282 struct iris_gs_prog_key gs; 283 struct iris_fs_prog_key fs; 284 struct iris_cs_prog_key cs; 285 }; 286 287 /** @} */ 288 289 struct iris_depth_stencil_alpha_state; 290 291 /** 292 * Cache IDs for the in-memory program cache (ice->shaders.cache). 293 */ 294 enum iris_program_cache_id { 295 IRIS_CACHE_VS = MESA_SHADER_VERTEX, 296 IRIS_CACHE_TCS = MESA_SHADER_TESS_CTRL, 297 IRIS_CACHE_TES = MESA_SHADER_TESS_EVAL, 298 IRIS_CACHE_GS = MESA_SHADER_GEOMETRY, 299 IRIS_CACHE_FS = MESA_SHADER_FRAGMENT, 300 IRIS_CACHE_CS = MESA_SHADER_COMPUTE, 301 IRIS_CACHE_BLORP, 302 }; 303 304 /** @{ 305 * 306 * Defines for PIPE_CONTROL operations, which trigger cache flushes, 307 * synchronization, pipelined memory writes, and so on. 308 * 309 * The bits here are not the actual hardware values. The actual fields 310 * move between various generations, so we just have flags for each 311 * potential operation, and use genxml to encode the actual packet. 312 */ 313 enum pipe_control_flags 314 { 315 PIPE_CONTROL_FLUSH_LLC = (1 << 1), 316 PIPE_CONTROL_LRI_POST_SYNC_OP = (1 << 2), 317 PIPE_CONTROL_STORE_DATA_INDEX = (1 << 3), 318 PIPE_CONTROL_CS_STALL = (1 << 4), 319 PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET = (1 << 5), 320 PIPE_CONTROL_SYNC_GFDT = (1 << 6), 321 PIPE_CONTROL_TLB_INVALIDATE = (1 << 7), 322 PIPE_CONTROL_MEDIA_STATE_CLEAR = (1 << 8), 323 PIPE_CONTROL_WRITE_IMMEDIATE = (1 << 9), 324 PIPE_CONTROL_WRITE_DEPTH_COUNT = (1 << 10), 325 PIPE_CONTROL_WRITE_TIMESTAMP = (1 << 11), 326 PIPE_CONTROL_DEPTH_STALL = (1 << 12), 327 PIPE_CONTROL_RENDER_TARGET_FLUSH = (1 << 13), 328 PIPE_CONTROL_INSTRUCTION_INVALIDATE = (1 << 14), 329 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE = (1 << 15), 330 PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE = (1 << 16), 331 PIPE_CONTROL_NOTIFY_ENABLE = (1 << 17), 332 PIPE_CONTROL_FLUSH_ENABLE = (1 << 18), 333 PIPE_CONTROL_DATA_CACHE_FLUSH = (1 << 19), 334 PIPE_CONTROL_VF_CACHE_INVALIDATE = (1 << 20), 335 PIPE_CONTROL_CONST_CACHE_INVALIDATE = (1 << 21), 336 PIPE_CONTROL_STATE_CACHE_INVALIDATE = (1 << 22), 337 PIPE_CONTROL_STALL_AT_SCOREBOARD = (1 << 23), 338 PIPE_CONTROL_DEPTH_CACHE_FLUSH = (1 << 24), 339 PIPE_CONTROL_TILE_CACHE_FLUSH = (1 << 25), 340 PIPE_CONTROL_FLUSH_HDC = (1 << 26), 341 }; 342 343 #define PIPE_CONTROL_CACHE_FLUSH_BITS \ 344 (PIPE_CONTROL_DEPTH_CACHE_FLUSH | \ 345 PIPE_CONTROL_DATA_CACHE_FLUSH | \ 346 PIPE_CONTROL_TILE_CACHE_FLUSH | \ 347 PIPE_CONTROL_RENDER_TARGET_FLUSH) 348 349 #define PIPE_CONTROL_CACHE_INVALIDATE_BITS \ 350 (PIPE_CONTROL_STATE_CACHE_INVALIDATE | \ 351 PIPE_CONTROL_CONST_CACHE_INVALIDATE | \ 352 PIPE_CONTROL_VF_CACHE_INVALIDATE | \ 353 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \ 354 PIPE_CONTROL_INSTRUCTION_INVALIDATE) 355 356 enum iris_predicate_state { 357 /* The first two states are used if we can determine whether to draw 358 * without having to look at the values in the query object buffer. This 359 * will happen if there is no conditional render in progress, if the query 360 * object is already completed or if something else has already added 361 * samples to the preliminary result. 362 */ 363 IRIS_PREDICATE_STATE_RENDER, 364 IRIS_PREDICATE_STATE_DONT_RENDER, 365 366 /* In this case whether to draw or not depends on the result of an 367 * MI_PREDICATE command so the predicate enable bit needs to be checked. 368 */ 369 IRIS_PREDICATE_STATE_USE_BIT, 370 }; 371 372 /** @} */ 373 374 /** 375 * An uncompiled, API-facing shader. This is the Gallium CSO for shaders. 376 * It primarily contains the NIR for the shader. 377 * 378 * Each API-facing shader can be compiled into multiple shader variants, 379 * based on non-orthogonal state dependencies, recorded in the shader key. 380 * 381 * See iris_compiled_shader, which represents a compiled shader variant. 382 */ 383 struct iris_uncompiled_shader { 384 struct pipe_reference ref; 385 386 /** 387 * NIR for the shader. 388 * 389 * Even for shaders that originate as TGSI, this pointer will be non-NULL. 390 */ 391 struct nir_shader *nir; 392 393 struct pipe_stream_output_info stream_output; 394 395 /* A SHA1 of the serialized NIR for the disk cache. */ 396 unsigned char nir_sha1[20]; 397 398 unsigned program_id; 399 400 /** Bitfield of (1 << IRIS_NOS_*) flags. */ 401 unsigned nos; 402 403 /** Have any shader variants been compiled yet? */ 404 bool compiled_once; 405 406 /* Whether shader uses atomic operations. */ 407 bool uses_atomic_load_store; 408 409 /** Size (in bytes) of the kernel input data */ 410 unsigned kernel_input_size; 411 412 /** Size (in bytes) of the local (shared) data passed as kernel inputs */ 413 unsigned kernel_shared_size; 414 415 /** List of iris_compiled_shader variants */ 416 struct list_head variants; 417 418 /** Lock for the variants list */ 419 simple_mtx_t lock; 420 421 /** For parallel shader compiles */ 422 struct util_queue_fence ready; 423 }; 424 425 enum iris_surface_group { 426 IRIS_SURFACE_GROUP_RENDER_TARGET, 427 IRIS_SURFACE_GROUP_RENDER_TARGET_READ, 428 IRIS_SURFACE_GROUP_CS_WORK_GROUPS, 429 IRIS_SURFACE_GROUP_TEXTURE, 430 IRIS_SURFACE_GROUP_IMAGE, 431 IRIS_SURFACE_GROUP_UBO, 432 IRIS_SURFACE_GROUP_SSBO, 433 434 IRIS_SURFACE_GROUP_COUNT, 435 }; 436 437 enum { 438 /* Invalid value for a binding table index. */ 439 IRIS_SURFACE_NOT_USED = 0xa0a0a0a0, 440 }; 441 442 struct iris_binding_table { 443 uint32_t size_bytes; 444 445 /** Number of surfaces in each group, before compacting. */ 446 uint32_t sizes[IRIS_SURFACE_GROUP_COUNT]; 447 448 /** Initial offset of each group. */ 449 uint32_t offsets[IRIS_SURFACE_GROUP_COUNT]; 450 451 /** Mask of surfaces used in each group. */ 452 uint64_t used_mask[IRIS_SURFACE_GROUP_COUNT]; 453 }; 454 455 /** 456 * A compiled shader variant, containing a pointer to the GPU assembly, 457 * as well as program data and other packets needed by state upload. 458 * 459 * There can be several iris_compiled_shader variants per API-level shader 460 * (iris_uncompiled_shader), due to state-based recompiles (brw_*_prog_key). 461 */ 462 struct iris_compiled_shader { 463 struct pipe_reference ref; 464 465 /** Link in the iris_uncompiled_shader::variants list */ 466 struct list_head link; 467 468 /** Key for this variant (but not for BLORP programs) */ 469 union iris_any_prog_key key; 470 471 /** 472 * Is the variant fully compiled and ready? 473 * 474 * Variants are added to \c iris_uncompiled_shader::variants before 475 * compilation actually occurs. This signals that compilation has 476 * completed. 477 */ 478 struct util_queue_fence ready; 479 480 /** Variant is ready, but compilation failed. */ 481 bool compilation_failed; 482 483 /** Reference to the uploaded assembly. */ 484 struct iris_state_ref assembly; 485 486 /** Pointer to the assembly in the BO's map. */ 487 void *map; 488 489 /** The program data (owned by the program cache hash table) */ 490 struct brw_stage_prog_data *prog_data; 491 492 /** A list of system values to be uploaded as uniforms. */ 493 enum brw_param_builtin *system_values; 494 unsigned num_system_values; 495 496 /** Size (in bytes) of the kernel input data */ 497 unsigned kernel_input_size; 498 499 /** Number of constbufs expected by the shader. */ 500 unsigned num_cbufs; 501 502 /** 503 * Derived 3DSTATE_STREAMOUT and 3DSTATE_SO_DECL_LIST packets 504 * (the VUE-based information for transform feedback outputs). 505 */ 506 uint32_t *streamout; 507 508 struct iris_binding_table bt; 509 510 /** 511 * Shader packets and other data derived from prog_data. These must be 512 * completely determined from prog_data. 513 */ 514 uint8_t derived_data[0]; 515 }; 516 517 /** 518 * API context state that is replicated per shader stage. 519 */ 520 struct iris_shader_state { 521 /** Uniform Buffers */ 522 struct pipe_shader_buffer constbuf[PIPE_MAX_CONSTANT_BUFFERS]; 523 struct iris_state_ref constbuf_surf_state[PIPE_MAX_CONSTANT_BUFFERS]; 524 525 bool sysvals_need_upload; 526 527 /** Shader Storage Buffers */ 528 struct pipe_shader_buffer ssbo[PIPE_MAX_SHADER_BUFFERS]; 529 struct iris_state_ref ssbo_surf_state[PIPE_MAX_SHADER_BUFFERS]; 530 531 /** Shader Storage Images (image load store) */ 532 struct iris_image_view image[PIPE_MAX_SHADER_IMAGES]; 533 534 struct iris_state_ref sampler_table; 535 struct iris_sampler_state *samplers[IRIS_MAX_TEXTURE_SAMPLERS]; 536 struct iris_sampler_view *textures[IRIS_MAX_TEXTURE_SAMPLERS]; 537 538 /** Bitfield of which constant buffers are bound (non-null). */ 539 uint32_t bound_cbufs; 540 uint32_t dirty_cbufs; 541 542 /** Bitfield of which image views are bound (non-null). */ 543 uint32_t bound_image_views; 544 545 /** Bitfield of which sampler views are bound (non-null). */ 546 uint32_t bound_sampler_views; 547 548 /** Bitfield of which shader storage buffers are bound (non-null). */ 549 uint32_t bound_ssbos; 550 551 /** Bitfield of which shader storage buffers are writable. */ 552 uint32_t writable_ssbos; 553 }; 554 555 /** 556 * Gallium CSO for stream output (transform feedback) targets. 557 */ 558 struct iris_stream_output_target { 559 struct pipe_stream_output_target base; 560 561 /** Storage holding the offset where we're writing in the buffer */ 562 struct iris_state_ref offset; 563 564 /** Stride (bytes-per-vertex) during this transform feedback operation */ 565 uint16_t stride; 566 567 /** Does the next 3DSTATE_SO_BUFFER need to zero the offsets? */ 568 bool zero_offset; 569 }; 570 571 /** 572 * A pool containing SAMPLER_BORDER_COLOR_STATE entries. 573 * 574 * See iris_border_color.c for more information. 575 */ 576 struct iris_border_color_pool { 577 struct iris_bo *bo; 578 void *map; 579 unsigned insert_point; 580 581 /** Map from border colors to offsets in the buffer. */ 582 struct hash_table *ht; 583 }; 584 585 /** 586 * The API context (derived from pipe_context). 587 * 588 * Most driver state is tracked here. 589 */ 590 struct iris_context { 591 struct pipe_context ctx; 592 struct threaded_context *thrctx; 593 594 /** A debug callback for KHR_debug output. */ 595 struct pipe_debug_callback dbg; 596 597 /** A device reset status callback for notifying that the GPU is hosed. */ 598 struct pipe_device_reset_callback reset; 599 600 /** A set of dmabuf resources dirtied beyond their default aux-states. */ 601 struct set *dirty_dmabufs; 602 603 /** Slab allocator for iris_transfer_map objects. */ 604 struct slab_child_pool transfer_pool; 605 606 /** Slab allocator for threaded_context's iris_transfer_map objects */ 607 struct slab_child_pool transfer_pool_unsync; 608 609 struct blorp_context blorp; 610 611 struct iris_batch batches[IRIS_BATCH_COUNT]; 612 613 struct u_upload_mgr *query_buffer_uploader; 614 615 struct { 616 struct { 617 /** 618 * Either the value of BaseVertex for indexed draw calls or the value 619 * of the argument <first> for non-indexed draw calls. 620 */ 621 int firstvertex; 622 int baseinstance; 623 } params; 624 625 /** 626 * Are the above values the ones stored in the draw_params buffer? 627 * If so, we can compare them against new values to see if anything 628 * changed. If not, we need to assume they changed. 629 */ 630 bool params_valid; 631 632 /** 633 * Resource and offset that stores draw_parameters from the indirect 634 * buffer or to the buffer that stures the previous values for non 635 * indirect draws. 636 */ 637 struct iris_state_ref draw_params; 638 639 struct { 640 /** 641 * The value of DrawID. This always comes in from it's own vertex 642 * buffer since it's not part of the indirect draw parameters. 643 */ 644 int drawid; 645 646 /** 647 * Stores if an indexed or non-indexed draw (~0/0). Useful to 648 * calculate BaseVertex as an AND of firstvertex and is_indexed_draw. 649 */ 650 int is_indexed_draw; 651 } derived_params; 652 653 /** 654 * Resource and offset used for GL_ARB_shader_draw_parameters which 655 * contains parameters that are not present in the indirect buffer as 656 * drawid and is_indexed_draw. They will go in their own vertex element. 657 */ 658 struct iris_state_ref derived_draw_params; 659 } draw; 660 661 struct { 662 struct iris_uncompiled_shader *uncompiled[MESA_SHADER_STAGES]; 663 struct iris_compiled_shader *prog[MESA_SHADER_STAGES]; 664 struct iris_compiled_shader *last_vue_shader; 665 struct { 666 unsigned size[4]; 667 unsigned entries[4]; 668 unsigned start[4]; 669 bool constrained; 670 } urb; 671 672 /** Uploader for shader assembly from the driver thread */ 673 struct u_upload_mgr *uploader_driver; 674 /** Uploader for shader assembly from the threaded context */ 675 struct u_upload_mgr *uploader_unsync; 676 struct hash_table *cache; 677 678 /** Is a GS or TES outputting points or lines? */ 679 bool output_topology_is_points_or_lines; 680 681 /** 682 * Scratch buffers for various sizes and stages. 683 * 684 * Indexed by the "Per-Thread Scratch Space" field's 4-bit encoding, 685 * and shader stage. 686 */ 687 struct iris_bo *scratch_bos[1 << 4][MESA_SHADER_STAGES]; 688 689 /** 690 * Scratch buffer surface states on Gfx12.5+ 691 */ 692 struct iris_state_ref scratch_surfs[1 << 4]; 693 } shaders; 694 695 struct intel_perf_context *perf_ctx; 696 697 /** Frame number for debug prints */ 698 uint32_t frame; 699 700 struct { 701 uint64_t dirty; 702 uint64_t stage_dirty; 703 uint64_t stage_dirty_for_nos[IRIS_NOS_COUNT]; 704 705 unsigned num_viewports; 706 unsigned sample_mask; 707 struct iris_blend_state *cso_blend; 708 struct iris_rasterizer_state *cso_rast; 709 struct iris_depth_stencil_alpha_state *cso_zsa; 710 struct iris_vertex_element_state *cso_vertex_elements; 711 struct pipe_blend_color blend_color; 712 struct pipe_poly_stipple poly_stipple; 713 struct pipe_viewport_state viewports[IRIS_MAX_VIEWPORTS]; 714 struct pipe_scissor_state scissors[IRIS_MAX_VIEWPORTS]; 715 struct pipe_stencil_ref stencil_ref; 716 struct pipe_framebuffer_state framebuffer; 717 struct pipe_clip_state clip_planes; 718 719 float default_outer_level[4]; 720 float default_inner_level[2]; 721 722 /** Bitfield of which vertex buffers are bound (non-null). */ 723 uint64_t bound_vertex_buffers; 724 725 uint8_t patch_vertices; 726 bool primitive_restart; 727 unsigned cut_index; 728 enum pipe_prim_type prim_mode:8; 729 bool prim_is_points_or_lines; 730 uint8_t vertices_per_patch; 731 732 bool window_space_position; 733 734 /** The last compute group size */ 735 uint32_t last_block[3]; 736 737 /** The last compute grid size */ 738 uint32_t last_grid[3]; 739 /** Reference to the BO containing the compute grid size */ 740 struct iris_state_ref grid_size; 741 /** Reference to the SURFACE_STATE for the compute grid resource */ 742 struct iris_state_ref grid_surf_state; 743 744 /** 745 * Array of aux usages for drawing, altered to account for any 746 * self-dependencies from resources bound for sampling and rendering. 747 */ 748 enum isl_aux_usage draw_aux_usage[BRW_MAX_DRAW_BUFFERS]; 749 750 /** Aux usage of the fb's depth buffer (which may or may not exist). */ 751 enum isl_aux_usage hiz_usage; 752 753 enum intel_urb_deref_block_size urb_deref_block_size; 754 755 /** Are depth writes enabled? (Depth buffer may or may not exist.) */ 756 bool depth_writes_enabled; 757 758 /** Are stencil writes enabled? (Stencil buffer may or may not exist.) */ 759 bool stencil_writes_enabled; 760 761 /** GenX-specific current state */ 762 struct iris_genx_state *genx; 763 764 struct iris_shader_state shaders[MESA_SHADER_STAGES]; 765 766 /** Do vertex shader uses shader draw parameters ? */ 767 bool vs_uses_draw_params; 768 bool vs_uses_derived_draw_params; 769 bool vs_needs_sgvs_element; 770 771 /** Do vertex shader uses edge flag ? */ 772 bool vs_needs_edge_flag; 773 774 /** Do any samplers need border color? One bit per shader stage. */ 775 uint8_t need_border_colors; 776 777 /** Global resource bindings */ 778 struct pipe_resource *global_bindings[IRIS_MAX_GLOBAL_BINDINGS]; 779 780 struct pipe_stream_output_target *so_target[PIPE_MAX_SO_BUFFERS]; 781 bool streamout_active; 782 783 bool statistics_counters_enabled; 784 785 /** Current conditional rendering mode */ 786 enum iris_predicate_state predicate; 787 788 /** 789 * Query BO with a MI_PREDICATE_RESULT snapshot calculated on the 790 * render context that needs to be uploaded to the compute context. 791 */ 792 struct iris_bo *compute_predicate; 793 794 /** Is a PIPE_QUERY_PRIMITIVES_GENERATED query active? */ 795 bool prims_generated_query_active; 796 797 /** 3DSTATE_STREAMOUT and 3DSTATE_SO_DECL_LIST packets */ 798 uint32_t *streamout; 799 800 /** The SURFACE_STATE for a 1x1x1 null surface. */ 801 struct iris_state_ref unbound_tex; 802 803 /** The SURFACE_STATE for a framebuffer-sized null surface. */ 804 struct iris_state_ref null_fb; 805 806 struct u_upload_mgr *surface_uploader; 807 struct u_upload_mgr *bindless_uploader; 808 struct u_upload_mgr *dynamic_uploader; 809 810 struct iris_binder binder; 811 812 struct iris_border_color_pool border_color_pool; 813 814 /** The high 16-bits of the last VBO/index buffer addresses */ 815 uint16_t last_vbo_high_bits[33]; 816 uint16_t last_index_bo_high_bits; 817 818 /** 819 * Resources containing streamed state which our render context 820 * currently points to. Used to re-add these to the validation 821 * list when we start a new batch and haven't resubmitted commands. 822 */ 823 struct { 824 struct pipe_resource *cc_vp; 825 struct pipe_resource *sf_cl_vp; 826 struct pipe_resource *color_calc; 827 struct pipe_resource *scissor; 828 struct pipe_resource *blend; 829 struct pipe_resource *index_buffer; 830 struct pipe_resource *cs_thread_ids; 831 struct pipe_resource *cs_desc; 832 } last_res; 833 834 /** Records the size of variable-length state for INTEL_DEBUG=bat */ 835 struct hash_table_u64 *sizes; 836 837 /** Last rendering scale argument provided to genX(emit_hashing_mode). */ 838 unsigned current_hash_scale; 839 } state; 840 }; 841 842 #define perf_debug(dbg, ...) do { \ 843 if (INTEL_DEBUG(DEBUG_PERF)) \ 844 dbg_printf(__VA_ARGS__); \ 845 if (unlikely(dbg)) \ 846 pipe_debug_message(dbg, PERF_INFO, __VA_ARGS__); \ 847 } while(0) 848 849 struct pipe_context * 850 iris_create_context(struct pipe_screen *screen, void *priv, unsigned flags); 851 void iris_destroy_context(struct pipe_context *ctx); 852 853 void iris_lost_context_state(struct iris_batch *batch); 854 855 void iris_mark_dirty_dmabuf(struct iris_context *ice, 856 struct pipe_resource *res); 857 void iris_flush_dirty_dmabufs(struct iris_context *ice); 858 859 void iris_init_blit_functions(struct pipe_context *ctx); 860 void iris_init_clear_functions(struct pipe_context *ctx); 861 void iris_init_program_functions(struct pipe_context *ctx); 862 void iris_init_screen_program_functions(struct pipe_screen *pscreen); 863 void iris_init_resource_functions(struct pipe_context *ctx); 864 void iris_init_perfquery_functions(struct pipe_context *ctx); 865 void iris_update_compiled_shaders(struct iris_context *ice); 866 void iris_update_compiled_compute_shader(struct iris_context *ice); 867 void iris_fill_cs_push_const_buffer(struct brw_cs_prog_data *cs_prog_data, 868 unsigned threads, 869 uint32_t *dst); 870 871 872 /* iris_blit.c */ 873 void iris_blorp_surf_for_resource(struct isl_device *isl_dev, 874 struct blorp_surf *surf, 875 struct pipe_resource *p_res, 876 enum isl_aux_usage aux_usage, 877 unsigned level, 878 bool is_render_target); 879 void iris_copy_region(struct blorp_context *blorp, 880 struct iris_batch *batch, 881 struct pipe_resource *dst, 882 unsigned dst_level, 883 unsigned dstx, unsigned dsty, unsigned dstz, 884 struct pipe_resource *src, 885 unsigned src_level, 886 const struct pipe_box *src_box); 887 888 /* iris_draw.c */ 889 890 void iris_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info, 891 unsigned drawid_offset, 892 const struct pipe_draw_indirect_info *indirect, 893 const struct pipe_draw_start_count_bias *draws, 894 unsigned num_draws); 895 void iris_launch_grid(struct pipe_context *, const struct pipe_grid_info *); 896 897 /* iris_pipe_control.c */ 898 899 void iris_emit_pipe_control_flush(struct iris_batch *batch, 900 const char *reason, uint32_t flags); 901 void iris_emit_pipe_control_write(struct iris_batch *batch, 902 const char *reason, uint32_t flags, 903 struct iris_bo *bo, uint32_t offset, 904 uint64_t imm); 905 void iris_emit_end_of_pipe_sync(struct iris_batch *batch, 906 const char *reason, uint32_t flags); 907 void iris_emit_buffer_barrier_for(struct iris_batch *batch, 908 struct iris_bo *bo, 909 enum iris_domain access); 910 void iris_flush_all_caches(struct iris_batch *batch); 911 912 #define iris_handle_always_flush_cache(batch) \ 913 if (unlikely(batch->screen->driconf.always_flush_cache)) \ 914 iris_flush_all_caches(batch); 915 916 void iris_init_flush_functions(struct pipe_context *ctx); 917 918 /* iris_border_color.c */ 919 920 void iris_init_border_color_pool(struct iris_context *ice); 921 void iris_destroy_border_color_pool(struct iris_context *ice); 922 void iris_border_color_pool_reserve(struct iris_context *ice, unsigned count); 923 uint32_t iris_upload_border_color(struct iris_context *ice, 924 union pipe_color_union *color); 925 926 /* iris_program.c */ 927 void iris_upload_ubo_ssbo_surf_state(struct iris_context *ice, 928 struct pipe_shader_buffer *buf, 929 struct iris_state_ref *surf_state, 930 isl_surf_usage_flags_t usage); 931 const struct shader_info *iris_get_shader_info(const struct iris_context *ice, 932 gl_shader_stage stage); 933 struct iris_bo *iris_get_scratch_space(struct iris_context *ice, 934 unsigned per_thread_scratch, 935 gl_shader_stage stage); 936 const struct iris_state_ref *iris_get_scratch_surf(struct iris_context *ice, 937 unsigned per_thread_scratch); 938 uint32_t iris_group_index_to_bti(const struct iris_binding_table *bt, 939 enum iris_surface_group group, 940 uint32_t index); 941 uint32_t iris_bti_to_group_index(const struct iris_binding_table *bt, 942 enum iris_surface_group group, 943 uint32_t bti); 944 945 /* iris_disk_cache.c */ 946 947 void iris_disk_cache_store(struct disk_cache *cache, 948 const struct iris_uncompiled_shader *ish, 949 const struct iris_compiled_shader *shader, 950 const void *prog_key, 951 uint32_t prog_key_size); 952 bool 953 iris_disk_cache_retrieve(struct iris_screen *screen, 954 struct u_upload_mgr *uploader, 955 struct iris_uncompiled_shader *ish, 956 struct iris_compiled_shader *shader, 957 const void *prog_key, 958 uint32_t prog_key_size); 959 960 /* iris_program_cache.c */ 961 962 void iris_init_program_cache(struct iris_context *ice); 963 void iris_destroy_program_cache(struct iris_context *ice); 964 struct iris_compiled_shader *iris_find_cached_shader(struct iris_context *ice, 965 enum iris_program_cache_id, 966 uint32_t key_size, 967 const void *key); 968 969 struct iris_compiled_shader *iris_create_shader_variant(const struct iris_screen *, 970 void *mem_ctx, 971 enum iris_program_cache_id cache_id, 972 uint32_t key_size, 973 const void *key); 974 975 void iris_finalize_program(struct iris_compiled_shader *shader, 976 struct brw_stage_prog_data *prog_data, 977 uint32_t *streamout, 978 enum brw_param_builtin *system_values, 979 unsigned num_system_values, 980 unsigned kernel_input_size, 981 unsigned num_cbufs, 982 const struct iris_binding_table *bt); 983 984 void iris_upload_shader(struct iris_screen *screen, 985 struct iris_uncompiled_shader *, 986 struct iris_compiled_shader *, 987 struct hash_table *driver_ht, 988 struct u_upload_mgr *uploader, 989 enum iris_program_cache_id, 990 uint32_t key_size, 991 const void *key, 992 const void *assembly); 993 void iris_delete_shader_variant(struct iris_compiled_shader *shader); 994 995 void iris_destroy_shader_state(struct pipe_context *ctx, void *state); 996 997 static inline void 998 iris_uncompiled_shader_reference(struct pipe_context *ctx, 999 struct iris_uncompiled_shader **dst, 1000 struct iris_uncompiled_shader *src) 1001 { 1002 if (*dst == src) 1003 return; 1004 1005 struct iris_uncompiled_shader *old_dst = *dst; 1006 1007 if (pipe_reference(old_dst != NULL ? &old_dst->ref : NULL, 1008 src != NULL ? &src->ref : NULL)) { 1009 iris_destroy_shader_state(ctx, *dst); 1010 } 1011 1012 *dst = src; 1013 } 1014 1015 static inline void 1016 iris_shader_variant_reference(struct iris_compiled_shader **dst, 1017 struct iris_compiled_shader *src) 1018 { 1019 struct iris_compiled_shader *old_dst = *dst; 1020 1021 if (pipe_reference(old_dst ? &old_dst->ref: NULL, src ? &src->ref : NULL)) 1022 iris_delete_shader_variant(old_dst); 1023 1024 *dst = src; 1025 } 1026 1027 bool iris_blorp_lookup_shader(struct blorp_batch *blorp_batch, 1028 const void *key, 1029 uint32_t key_size, 1030 uint32_t *kernel_out, 1031 void *prog_data_out); 1032 bool iris_blorp_upload_shader(struct blorp_batch *blorp_batch, uint32_t stage, 1033 const void *key, uint32_t key_size, 1034 const void *kernel, uint32_t kernel_size, 1035 const struct brw_stage_prog_data *prog_data, 1036 uint32_t prog_data_size, 1037 uint32_t *kernel_out, 1038 void *prog_data_out); 1039 1040 /* iris_resolve.c */ 1041 1042 void iris_predraw_resolve_inputs(struct iris_context *ice, 1043 struct iris_batch *batch, 1044 bool *draw_aux_buffer_disabled, 1045 gl_shader_stage stage, 1046 bool consider_framebuffer); 1047 void iris_predraw_resolve_framebuffer(struct iris_context *ice, 1048 struct iris_batch *batch, 1049 bool *draw_aux_buffer_disabled); 1050 void iris_predraw_flush_buffers(struct iris_context *ice, 1051 struct iris_batch *batch, 1052 gl_shader_stage stage); 1053 void iris_postdraw_update_resolve_tracking(struct iris_context *ice, 1054 struct iris_batch *batch); 1055 void iris_cache_flush_for_render(struct iris_batch *batch, 1056 struct iris_bo *bo, 1057 enum isl_aux_usage aux_usage); 1058 int iris_get_driver_query_info(struct pipe_screen *pscreen, unsigned index, 1059 struct pipe_driver_query_info *info); 1060 int iris_get_driver_query_group_info(struct pipe_screen *pscreen, 1061 unsigned index, 1062 struct pipe_driver_query_group_info *info); 1063 1064 /* iris_state.c */ 1065 void gfx9_toggle_preemption(struct iris_context *ice, 1066 struct iris_batch *batch, 1067 const struct pipe_draw_info *draw); 1068 1069 1070 1071 #ifdef genX 1072 # include "iris_genx_protos.h" 1073 #else 1074 # define genX(x) gfx4_##x 1075 # include "iris_genx_protos.h" 1076 # undef genX 1077 # define genX(x) gfx5_##x 1078 # include "iris_genx_protos.h" 1079 # undef genX 1080 # define genX(x) gfx6_##x 1081 # include "iris_genx_protos.h" 1082 # undef genX 1083 # define genX(x) gfx7_##x 1084 # include "iris_genx_protos.h" 1085 # undef genX 1086 # define genX(x) gfx75_##x 1087 # include "iris_genx_protos.h" 1088 # undef genX 1089 # define genX(x) gfx8_##x 1090 # include "iris_genx_protos.h" 1091 # undef genX 1092 # define genX(x) gfx9_##x 1093 # include "iris_genx_protos.h" 1094 # undef genX 1095 # define genX(x) gfx11_##x 1096 # include "iris_genx_protos.h" 1097 # undef genX 1098 # define genX(x) gfx12_##x 1099 # include "iris_genx_protos.h" 1100 # undef genX 1101 # define genX(x) gfx125_##x 1102 # include "iris_genx_protos.h" 1103 # undef genX 1104 #endif 1105 1106 #endif 1107
Indexes created Tue Jul 21 00:24:56 UTC 2026