1 /* 2 * Copyright 2017 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 #ifndef IRIS_RESOURCE_H 24 #define IRIS_RESOURCE_H 25 26 #include "pipe/p_state.h" 27 #include "util/u_inlines.h" 28 #include "util/u_range.h" 29 #include "util/u_threaded_context.h" 30 #include "intel/isl/isl.h" 31 #include "iris_bufmgr.h" 32 33 struct iris_batch; 34 struct iris_context; 35 struct shader_info; 36 37 #define IRIS_MAX_MIPLEVELS 15 38 39 struct iris_format_info { 40 enum isl_format fmt; 41 struct isl_swizzle swizzle; 42 }; 43 44 #define IRIS_RESOURCE_FLAG_SHADER_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 0) 45 #define IRIS_RESOURCE_FLAG_SURFACE_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 1) 46 #define IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 2) 47 #define IRIS_RESOURCE_FLAG_BINDLESS_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 3) 48 #define IRIS_RESOURCE_FLAG_DEVICE_MEM (PIPE_RESOURCE_FLAG_DRV_PRIV << 4) 49 50 /** 51 * Resources represent a GPU buffer object or image (mipmap tree). 52 * 53 * They contain the storage (BO) and layout information (ISL surface). 54 */ 55 struct iris_resource { 56 struct threaded_resource base; 57 enum pipe_format internal_format; 58 59 /** 60 * The ISL surface layout information for this resource. 61 * 62 * This is not filled out for PIPE_BUFFER resources, but is guaranteed 63 * to be zeroed. Note that this also guarantees that res->surf.tiling 64 * will be ISL_TILING_LINEAR, so it's safe to check that. 65 */ 66 struct isl_surf surf; 67 68 /** Backing storage for the resource */ 69 struct iris_bo *bo; 70 71 /** offset at which data starts in the BO */ 72 uint64_t offset; 73 74 /** 75 * A bitfield of PIPE_BIND_* indicating how this resource was bound 76 * in the past. Only meaningful for PIPE_BUFFER; used for flushing. 77 */ 78 unsigned bind_history; 79 80 /** 81 * A bitfield of MESA_SHADER_* stages indicating where this resource 82 * was bound. 83 */ 84 unsigned bind_stages; 85 86 /** 87 * For PIPE_BUFFER resources, a range which may contain valid data. 88 * 89 * This is a conservative estimate of what part of the buffer contains 90 * valid data that we have to preserve. The rest of the buffer is 91 * considered invalid, and we can promote writes to that region to 92 * be unsynchronized writes, avoiding blit copies. 93 */ 94 struct util_range valid_buffer_range; 95 96 /** 97 * Auxiliary buffer information (CCS, MCS, or HiZ). 98 */ 99 struct { 100 /** The surface layout for the auxiliary buffer. */ 101 struct isl_surf surf; 102 103 /** The buffer object containing the auxiliary data. */ 104 struct iris_bo *bo; 105 106 /** Offset into 'bo' where the auxiliary surface starts. */ 107 uint32_t offset; 108 109 struct { 110 struct isl_surf surf; 111 112 /** Offset into 'bo' where the auxiliary surface starts. */ 113 uint32_t offset; 114 } extra_aux; 115 116 /** 117 * When importing resources with a clear color, we may not know the 118 * clear color on the CPU at first. 119 */ 120 bool clear_color_unknown; 121 122 /** 123 * Fast clear color for this surface. For depth surfaces, the clear 124 * value is stored as a float32 in the red component. 125 * 126 * Do not rely on this value if clear_color_unknown is set. 127 */ 128 union isl_color_value clear_color; 129 130 /** Buffer object containing the indirect clear color. */ 131 struct iris_bo *clear_color_bo; 132 133 /** Offset into bo where the clear color can be found. */ 134 uint64_t clear_color_offset; 135 136 /** 137 * \brief The type of auxiliary compression used by this resource. 138 * 139 * This describes the type of auxiliary compression that is intended to 140 * be used by this resource. An aux usage of ISL_AUX_USAGE_NONE means 141 * that auxiliary compression is permanently disabled. An aux usage 142 * other than ISL_AUX_USAGE_NONE does not imply that auxiliary 143 * compression will always be enabled for this surface. 144 */ 145 enum isl_aux_usage usage; 146 147 /** 148 * A bitfield of ISL_AUX_* modes that might this resource might use. 149 * 150 * For example, a surface might use both CCS_E and CCS_D at times. 151 */ 152 unsigned possible_usages; 153 154 /** 155 * Same as possible_usages, but only with modes supported for sampling. 156 */ 157 unsigned sampler_usages; 158 159 /** 160 * \brief Maps miptree slices to their current aux state. 161 * 162 * This two-dimensional array is indexed as [level][layer] and stores an 163 * aux state for each slice. 164 */ 165 enum isl_aux_state **state; 166 } aux; 167 168 /** 169 * For external surfaces, this is format that was used to create or import 170 * the surface. For internal surfaces, this will always be 171 * PIPE_FORMAT_NONE. 172 */ 173 enum pipe_format external_format; 174 175 /** 176 * For external surfaces, this is DRM format modifier that was used to 177 * create or import the surface. For internal surfaces, this will always 178 * be DRM_FORMAT_MOD_INVALID. 179 */ 180 const struct isl_drm_modifier_info *mod_info; 181 182 /** 183 * The screen the resource was originally created with, stored for refcounting. 184 */ 185 struct pipe_screen *orig_screen; 186 }; 187 188 /** 189 * A simple <resource, offset> tuple for storing a reference to a 190 * piece of state stored in a GPU buffer object. 191 */ 192 struct iris_state_ref { 193 struct pipe_resource *res; 194 uint32_t offset; 195 }; 196 197 /** 198 * The SURFACE_STATE descriptors for a resource. 199 */ 200 struct iris_surface_state { 201 /** 202 * CPU-side copy of the packed SURFACE_STATE structures, already 203 * aligned so they can be uploaded as a contiguous pile of bytes. 204 * 205 * This can be updated and re-uploaded if (e.g.) addresses need to change. 206 */ 207 uint32_t *cpu; 208 209 /** 210 * How many states are there? (Each aux mode has its own state.) 211 */ 212 unsigned num_states; 213 214 /** 215 * Address of the resource (res->bo->address). Note that "Surface 216 * Base Address" may be offset from this value. 217 */ 218 uint64_t bo_address; 219 220 /** A reference to the GPU buffer holding our uploaded SURFACE_STATE */ 221 struct iris_state_ref ref; 222 }; 223 224 /** 225 * Gallium CSO for sampler views (texture views). 226 * 227 * In addition to the normal pipe_resource, this adds an ISL view 228 * which may reinterpret the format or restrict levels/layers. 229 * 230 * These can also be linear texture buffers. 231 */ 232 struct iris_sampler_view { 233 struct pipe_sampler_view base; 234 struct isl_view view; 235 236 union isl_color_value clear_color; 237 238 /* A short-cut (not a reference) to the actual resource being viewed. 239 * Multi-planar (or depth+stencil) images may have multiple resources 240 * chained together; this skips having to traverse base->texture->*. 241 */ 242 struct iris_resource *res; 243 244 /** The resource (BO) holding our SURFACE_STATE. */ 245 struct iris_surface_state surface_state; 246 }; 247 248 /** 249 * Image view representation. 250 */ 251 struct iris_image_view { 252 struct pipe_image_view base; 253 254 /** The resource (BO) holding our SURFACE_STATE. */ 255 struct iris_surface_state surface_state; 256 }; 257 258 /** 259 * Gallium CSO for surfaces (framebuffer attachments). 260 * 261 * A view of a surface that can be bound to a color render target or 262 * depth/stencil attachment. 263 */ 264 struct iris_surface { 265 struct pipe_surface base; 266 struct isl_view view; 267 struct isl_view read_view; 268 union isl_color_value clear_color; 269 270 /** The resource (BO) holding our SURFACE_STATE. */ 271 struct iris_surface_state surface_state; 272 /** The resource (BO) holding our SURFACE_STATE for read. */ 273 struct iris_surface_state surface_state_read; 274 }; 275 276 /** 277 * Transfer object - information about a buffer mapping. 278 */ 279 struct iris_transfer { 280 struct threaded_transfer base; 281 struct pipe_debug_callback *dbg; 282 void *buffer; 283 void *ptr; 284 285 /** A linear staging resource for GPU-based copy_region transfers. */ 286 struct pipe_resource *staging; 287 struct blorp_context *blorp; 288 struct iris_batch *batch; 289 290 bool dest_had_defined_contents; 291 292 void (*unmap)(struct iris_transfer *); 293 }; 294 295 /** 296 * Memory Object 297 */ 298 struct iris_memory_object { 299 struct pipe_memory_object b; 300 struct iris_bo *bo; 301 uint64_t format; 302 unsigned stride; 303 }; 304 305 /** 306 * Unwrap a pipe_resource to get the underlying iris_bo (for convenience). 307 */ 308 static inline struct iris_bo * 309 iris_resource_bo(struct pipe_resource *p_res) 310 { 311 struct iris_resource *res = (void *) p_res; 312 return res->bo; 313 } 314 315 static inline uint32_t 316 iris_mocs(const struct iris_bo *bo, 317 const struct isl_device *dev, 318 isl_surf_usage_flags_t usage) 319 { 320 return isl_mocs(dev, usage, bo && iris_bo_is_external(bo)); 321 } 322 323 struct iris_format_info iris_format_for_usage(const struct intel_device_info *, 324 enum pipe_format pf, 325 isl_surf_usage_flags_t usage); 326 327 struct pipe_resource *iris_resource_get_separate_stencil(struct pipe_resource *); 328 329 void iris_get_depth_stencil_resources(struct pipe_resource *res, 330 struct iris_resource **out_z, 331 struct iris_resource **out_s); 332 bool iris_resource_set_clear_color(struct iris_context *ice, 333 struct iris_resource *res, 334 union isl_color_value color); 335 336 void iris_replace_buffer_storage(struct pipe_context *ctx, 337 struct pipe_resource *dst, 338 struct pipe_resource *src, 339 unsigned num_rebinds, 340 uint32_t rebind_mask, 341 uint32_t delete_buffer_id); 342 343 344 void iris_init_screen_resource_functions(struct pipe_screen *pscreen); 345 346 void iris_dirty_for_history(struct iris_context *ice, 347 struct iris_resource *res); 348 uint32_t iris_flush_bits_for_history(struct iris_context *ice, 349 struct iris_resource *res); 350 351 void iris_flush_and_dirty_for_history(struct iris_context *ice, 352 struct iris_batch *batch, 353 struct iris_resource *res, 354 uint32_t extra_flags, 355 const char *reason); 356 357 unsigned iris_get_num_logical_layers(const struct iris_resource *res, 358 unsigned level); 359 360 void iris_resource_disable_aux(struct iris_resource *res); 361 362 #define INTEL_REMAINING_LAYERS UINT32_MAX 363 #define INTEL_REMAINING_LEVELS UINT32_MAX 364 365 void 366 iris_hiz_exec(struct iris_context *ice, 367 struct iris_batch *batch, 368 struct iris_resource *res, 369 unsigned int level, unsigned int start_layer, 370 unsigned int num_layers, enum isl_aux_op op, 371 bool update_clear_depth); 372 373 /** 374 * Prepare a miptree for access 375 * 376 * This function should be called prior to any access to miptree in order to 377 * perform any needed resolves. 378 * 379 * \param[in] start_level The first mip level to be accessed 380 * 381 * \param[in] num_levels The number of miplevels to be accessed or 382 * INTEL_REMAINING_LEVELS to indicate every level 383 * above start_level will be accessed 384 * 385 * \param[in] start_layer The first array slice or 3D layer to be accessed 386 * 387 * \param[in] num_layers The number of array slices or 3D layers be 388 * accessed or INTEL_REMAINING_LAYERS to indicate 389 * every layer above start_layer will be accessed 390 * 391 * \param[in] aux_supported Whether or not the access will support the 392 * miptree's auxiliary compression format; this 393 * must be false for uncompressed miptrees 394 * 395 * \param[in] fast_clear_supported Whether or not the access will support 396 * fast clears in the miptree's auxiliary 397 * compression format 398 */ 399 void 400 iris_resource_prepare_access(struct iris_context *ice, 401 struct iris_resource *res, 402 uint32_t start_level, uint32_t num_levels, 403 uint32_t start_layer, uint32_t num_layers, 404 enum isl_aux_usage aux_usage, 405 bool fast_clear_supported); 406 407 /** 408 * Complete a write operation 409 * 410 * This function should be called after any operation writes to a miptree. 411 * This will update the miptree's compression state so that future resolves 412 * happen correctly. Technically, this function can be called before the 413 * write occurs but the caller must ensure that they don't interlace 414 * iris_resource_prepare_access and iris_resource_finish_write calls to 415 * overlapping layer/level ranges. 416 * 417 * \param[in] level The mip level that was written 418 * 419 * \param[in] start_layer The first array slice or 3D layer written 420 * 421 * \param[in] num_layers The number of array slices or 3D layers 422 * written or INTEL_REMAINING_LAYERS to indicate 423 * every layer above start_layer was written 424 * 425 * \param[in] written_with_aux Whether or not the write was done with 426 * auxiliary compression enabled 427 */ 428 void 429 iris_resource_finish_write(struct iris_context *ice, 430 struct iris_resource *res, uint32_t level, 431 uint32_t start_layer, uint32_t num_layers, 432 enum isl_aux_usage aux_usage); 433 434 /** Get the auxiliary compression state of a miptree slice */ 435 enum isl_aux_state 436 iris_resource_get_aux_state(const struct iris_resource *res, 437 uint32_t level, uint32_t layer); 438 439 /** 440 * Set the auxiliary compression state of a miptree slice range 441 * 442 * This function directly sets the auxiliary compression state of a slice 443 * range of a miptree. It only modifies data structures and does not do any 444 * resolves. This should only be called by code which directly performs 445 * compression operations such as fast clears and resolves. Most code should 446 * use iris_resource_prepare_access or iris_resource_finish_write. 447 */ 448 void 449 iris_resource_set_aux_state(struct iris_context *ice, 450 struct iris_resource *res, uint32_t level, 451 uint32_t start_layer, uint32_t num_layers, 452 enum isl_aux_state aux_state); 453 454 /** 455 * Prepare a miptree for raw access 456 * 457 * This helper prepares the miptree for access that knows nothing about any 458 * sort of compression whatsoever. This is useful when mapping the surface or 459 * using it with the blitter. 460 */ 461 static inline void 462 iris_resource_access_raw(struct iris_context *ice, 463 struct iris_resource *res, 464 uint32_t level, uint32_t layer, 465 uint32_t num_layers, 466 bool write) 467 { 468 iris_resource_prepare_access(ice, res, level, 1, layer, num_layers, 469 ISL_AUX_USAGE_NONE, false); 470 if (write) { 471 iris_resource_finish_write(ice, res, level, layer, num_layers, 472 ISL_AUX_USAGE_NONE); 473 } 474 } 475 476 enum isl_aux_usage iris_resource_texture_aux_usage(struct iris_context *ice, 477 const struct iris_resource *res, 478 enum isl_format view_fmt); 479 void iris_resource_prepare_texture(struct iris_context *ice, 480 struct iris_resource *res, 481 enum isl_format view_format, 482 uint32_t start_level, uint32_t num_levels, 483 uint32_t start_layer, uint32_t num_layers); 484 485 enum isl_aux_usage iris_image_view_aux_usage(struct iris_context *ice, 486 const struct pipe_image_view *pview, 487 const struct shader_info *info); 488 enum isl_format iris_image_view_get_format(struct iris_context *ice, 489 const struct pipe_image_view *img); 490 491 bool iris_has_invalid_primary(const struct iris_resource *res, 492 unsigned start_level, unsigned num_levels, 493 unsigned start_layer, unsigned num_layers); 494 495 void iris_resource_check_level_layer(const struct iris_resource *res, 496 uint32_t level, uint32_t layer); 497 498 bool iris_resource_level_has_hiz(const struct iris_resource *res, 499 uint32_t level); 500 501 bool iris_sample_with_depth_aux(const struct intel_device_info *devinfo, 502 const struct iris_resource *res); 503 504 bool iris_can_sample_mcs_with_clear(const struct intel_device_info *devinfo, 505 const struct iris_resource *res); 506 507 bool iris_has_color_unresolved(const struct iris_resource *res, 508 unsigned start_level, unsigned num_levels, 509 unsigned start_layer, unsigned num_layers); 510 511 bool iris_render_formats_color_compatible(enum isl_format a, 512 enum isl_format b, 513 union isl_color_value color, 514 bool clear_color_unknown); 515 enum isl_aux_usage iris_resource_render_aux_usage(struct iris_context *ice, 516 struct iris_resource *res, 517 uint32_t level, 518 enum isl_format render_fmt, 519 bool draw_aux_disabled); 520 void iris_resource_prepare_render(struct iris_context *ice, 521 struct iris_resource *res, uint32_t level, 522 uint32_t start_layer, uint32_t layer_count, 523 enum isl_aux_usage aux_usage); 524 void iris_resource_finish_render(struct iris_context *ice, 525 struct iris_resource *res, uint32_t level, 526 uint32_t start_layer, uint32_t layer_count, 527 enum isl_aux_usage aux_usage); 528 #endif 529
Indexes created Wed Jul 22 00:25:13 UTC 2026