1 /* $NetBSD: gtintrreg.h,v 1.6 2021/08/02 12:56:24 andvar Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project by 18 * Allegro Networks, Inc., and Wasabi Systems, Inc. 19 * 4. The name of Allegro Networks, Inc. may not be used to endorse 20 * or promote products derived from this software without specific prior 21 * written permission. 22 * 5. The name of Wasabi Systems, Inc. may not be used to endorse 23 * or promote products derived from this software without specific prior 24 * written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND 27 * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 28 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY 29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * gt64260intr.h: defines for GT-64260 system controller interrupts 42 * 43 * creation Sun Jan 7 18:05:59 PST 2001 cliff 44 * 45 * NOTE: 46 * Galileo GT-64260 manual bit defines assume Little Endian 47 * ordering of bits within bytes, i.e. 48 * bit #0 --> 0x01 49 * vs. Motorola Big Endian bit numbering where 50 * bit #0 --> 0x80 51 * Consequently we define bits in Little Endian format and plan 52 * to swizzle bytes during programmed I/O by using lwbrx/swbrx 53 * to load/store GT-64260 registers. 54 */ 55 56 57 #ifndef _DISCOVERY_GT64260INTR_H 58 #define _DISCOVERY_GT64260INTR_H 59 60 61 /* 62 * GT-64260 Interrupt Controller Register Map 63 */ 64 #define ICR_MIC_LO 0xc18 /* main interrupt cause low */ 65 #define ICR_MIC_HI 0xc68 /* main interrupt cause high */ 66 #define ICR_CIM_LO 0xc1c /* CPU interrupt mask low */ 67 #define ICR_CIM_HI 0xc6c /* CPU interrupt mask high */ 68 #define ICR_CSC 0xc70 /* CPU select cause */ 69 #define ICR_P0IM_LO 0xc24 /* PCI_0 interrupt mask low */ 70 #define ICR_P0IM_HI 0xc64 /* PCI_0 interrupt mask high */ 71 #define ICR_P0SC 0xc74 /* PCI_0 select cause */ 72 #define ICR_P1IM_LO 0xca4 /* PCI_1 interrupt mask low */ 73 #define ICR_P1IM_HI 0xce4 /* PCI_1 interrupt mask high */ 74 #define ICR_P1SC 0xcf4 /* PCI_1 select cause */ 75 #define ICR_CI0M 0xe60 /* CPU int[0] mask */ 76 #define ICR_CI1M 0xe64 /* CPU int[1] mask */ 77 #define ICR_CI2M 0xe68 /* CPU int[2] mask */ 78 #define ICR_CI3M 0xe6c /* CPU int[3] mask */ 79 80 #define IRQ_DEV 1 /* device interface interrupt */ 81 #define IRQ_DMA 2 /* DMA address error interrupt */ 82 #define IRQ_CPU 3 /* CPU interface interrupt */ 83 #define IRQ_IDMA0_1 4 /* IDMA ch. 0..1 complete interrupt */ 84 #define IRQ_IDMA2_3 5 /* IDMA ch. 2..3 complete interrupt */ 85 #define IRQ_IDMA4_5 6 /* IDMA ch. 4..5 complete interrupt */ 86 #define IRQ_IDMA6_7 7 /* IDMA ch. 6..7 complete interrupt */ 87 #define IRQ_TIME0_1 8 /* Timer 0..1 interrupt */ 88 #define IRQ_TIME2_3 9 /* Timer 2..3 interrupt */ 89 #define IRQ_TIME4_5 10 /* Timer 4..5 interrupt */ 90 #define IRQ_TIME6_7 11 /* Timer 6..7 interrupt */ 91 #define IRQ_PCI0_0 12 /* PCI 0 interrupt 0 summary */ 92 #define IRQ_PCI0_1 13 /* PCI 0 interrupt 1 summary */ 93 #define IRQ_PCI0_2 14 /* PCI 0 interrupt 2 summary */ 94 #define IRQ_PCI0_3 15 /* PCI 0 interrupt 3 summary */ 95 #define IRQ_PCI1_0 16 /* PCI 1 interrupt 0 summary */ 96 #define IRQ_ECC 17 /* ECC error interrupt */ 97 #define IRQ_PCI1_1 18 /* PCI 1 interrupt 1 summary */ 98 #define IRQ_PCI1_2 19 /* PCI 1 interrupt 2 summary */ 99 #define IRQ_PCI1_3 20 /* PCI 1 interrupt 3 summary */ 100 #define IRQ_PCI0OUT_LO 21 /* PCI 0 outbound interrupt summary */ 101 #define IRQ_PCI0OUT_HI 22 /* PCI 0 outbound interrupt summary */ 102 #define IRQ_PCI1OUT_LO 23 /* PCI 1 outbound interrupt summary */ 103 #define IRQ_PCI1OUT_HI 24 /* PCI 1 outbound interrupt summary */ 104 #define IRQ_PCI0IN_LO 26 /* PCI 0 inbound interrupt summary */ 105 #define IRQ_PCI0IN_HI 27 /* PCI 0 inbound interrupt summary */ 106 #define IRQ_PCI1IN_LO 28 /* PCI 1 inbound interrupt summary */ 107 #define IRQ_PCI1IN_HI 29 /* PCI 1 inbound interrupt summary */ 108 #define IRQ_ETH0 32 /* Ethernet controller 0 interrupt */ 109 #define IRQ_ETH1 33 /* Ethernet controller 1 interrupt */ 110 #define IRQ_ETH2 34 /* Ethernet controller 2 interrupt */ 111 #define IRQ_SDMA 36 /* SDMA interrupt */ 112 #define IRQ_I2C 37 /* I2C interrupt */ 113 #define IRQ_BRG 39 /* Baud Rate Generator interrupt */ 114 #define IRQ_MPSC0 40 /* MPSC 0 interrupt */ 115 #define IRQ_MPSC1 42 /* MPSC 1 interrupt */ 116 #define IRQ_COMM 43 /* Comm unit interrupt */ 117 #define IRQ_GPP7_0 56 /* GPP[7..0] interrupt */ 118 #define IRQ_GPP15_8 57 /* GPP[15..8] interrupt */ 119 #define IRQ_GPP23_16 58 /* GPP[23..16] interrupt */ 120 #define IRQ_GPP31_24 59 /* GPP[31..24] interrupt */ 121 122 #endif /* _DISCOVERY_GT64260INTR_H */ 123
Indexes created Tue Sep 23 07:09:52 GMT 2025