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    Searched defs:ISD (Results 1 - 12 of 12) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
CostTable.h 25 int ISD;
32 int ISD, MVT Ty) {
34 return ISD == Entry.ISD && Ty == Entry.Type;
45 int ISD;
55 int ISD, MVT Dst, MVT Src) {
57 return ISD == Entry.ISD && Src == Entry.Src && Dst == Entry.Dst;
TargetCallingConv.h 25 namespace ISD {
259 } // end namespace ISD
BasicTTIImpl.h 176 static ISD::MemIndexedMode getISDIndexedMode(TTI::MemIndexedMode M) {
179 return ISD::UNINDEXED;
181 return ISD::PRE_INC;
183 return ISD::PRE_DEC;
185 return ISD::POST_INC;
187 return ISD::POST_DEC;
431 return TLI->isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
432 TLI->isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
464 TLI->isOperationLegalOrCustom(ISD::FSQRT, VT);
476 if (TLI->isOperationLegalOrCustomOrPromote(ISD::FADD, VT)
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ISDOpcodes.h 20 /// ISD namespace - This namespace contains an enum which represents all of the
23 namespace ISD {
26 /// ISD::NodeType enum - This enum defines the target-independent operators
1250 /// For example ISD::AND for ISD::VECREDUCE_AND.
1328 /// ISD::CondCode enum - These are ordered carefully to make the bitfields
1430 } // namespace ISD
SelectionDAGNodes.h 84 namespace ISD {
122 /// specified node are ISD::UNDEF.
125 } // end namespace ISD
519 // LSBaseSDNode => enum ISD::MemIndexedMode
520 // MaskedLoadStoreBaseSDNode => enum ISD::MemIndexedMode
521 // MaskedGatherScatterSDNode => enum ISD::MemIndexType
533 uint16_t ExtTy : 2; // enum ISD::LoadExtType
619 /// are the opcode values in the ISD and <target>ISD namespaces. For
624 /// \<target\>ISD namespace)
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  /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/
LanaiTargetTransformInfo.h 92 int ISD = TLI->InstructionOpcodeToISD(Opcode);
94 switch (ISD) {
99 case ISD::MUL:
100 case ISD::SDIV:
101 case ISD::UDIV:
102 case ISD::UREM:
  /src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/
NVPTXTargetTransformInfo.cpp 380 int ISD = TLI->InstructionOpcodeToISD(Opcode);
382 switch (ISD) {
387 case ISD::ADD:
388 case ISD::MUL:
389 case ISD::XOR:
390 case ISD::OR:
391 case ISD::AND:
  /src/external/apache2/llvm/dist/llvm/lib/MC/
MCMachOStreamer.cpp 302 IndirectSymbolData ISD;
303 ISD.Symbol = Symbol;
304 ISD.Section = getCurrentSectionOnly();
305 getAssembler().getIndirectSymbols().push_back(ISD);
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCTargetTransformInfo.cpp 493 continue; // ISD::FCOPYSIGN is never a library call.
494 case Intrinsic::fma: Opcode = ISD::FMA; break;
495 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
496 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
497 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
498 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
499 case Intrinsic::rint: Opcode = ISD::FRINT; break;
500 case Intrinsic::lrint: Opcode = ISD::LRINT; break;
501 case Intrinsic::llrint: Opcode = ISD::LLRINT; break;
502 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break
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  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64TargetTransformInfo.cpp 582 int ISD = TLI->InstructionOpcodeToISD(Opcode);
583 assert(ISD && "Invalid opcode");
621 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 },
622 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 },
623 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 },
624 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 },
627 { ISD::TRUNCATE, MVT::nxv2i1, MVT::nxv2i16, 1 },
628 { ISD::TRUNCATE, MVT::nxv2i1, MVT::nxv2i32, 1 },
629 { ISD::TRUNCATE, MVT::nxv2i1, MVT::nxv2i64, 1 },
630 { ISD::TRUNCATE, MVT::nxv4i1, MVT::nxv4i16, 1 }
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  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMTargetTransformInfo.cpp 401 int ISD = TLI->InstructionOpcodeToISD(Opcode);
402 assert(ISD && "Invalid opcode");
441 {ISD::SIGN_EXTEND, MVT::i32, MVT::i16, 0},
442 {ISD::ZERO_EXTEND, MVT::i32, MVT::i16, 0},
443 {ISD::SIGN_EXTEND, MVT::i32, MVT::i8, 0},
444 {ISD::ZERO_EXTEND, MVT::i32, MVT::i8, 0},
445 {ISD::SIGN_EXTEND, MVT::i16, MVT::i8, 0},
446 {ISD::ZERO_EXTEND, MVT::i16, MVT::i8, 0},
447 {ISD::SIGN_EXTEND, MVT::i64, MVT::i32, 1},
448 {ISD::ZERO_EXTEND, MVT::i64, MVT::i32, 1}
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86TargetTransformInfo.cpp 206 int ISD = TLI->InstructionOpcodeToISD(Opcode);
207 assert(ISD && "Invalid opcode");
210 { ISD::FDIV, MVT::f32, 18 }, // divss
211 { ISD::FDIV, MVT::v4f32, 35 }, // divps
212 { ISD::FDIV, MVT::f64, 33 }, // divsd
213 { ISD::FDIV, MVT::v2f64, 65 }, // divpd
217 if (const auto *Entry = CostTableLookup(GLMCostTable, ISD,
222 { ISD::MUL, MVT::v4i32, 11 }, // pmulld
223 { ISD::MUL, MVT::v8i16, 2 }, // pmullw
224 { ISD::FMUL, MVT::f64, 2 }, // muls
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