1 /* $NetBSD: openpicreg.h,v 1.7 2014/12/27 16:19:33 nonaka Exp $ */ 2 /*- 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 9 * 10 * This material is based upon work supported by the Defense Advanced Research 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 12 * Contract No. N66001-09-C-2073. 13 * Approved for Public Release, Distribution Unlimited 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #ifndef _POWERPC_BOOKE_OPENPICREG_H_ 38 #define _POWERPC_BOOKE_OPENPICREG_H_ 39 40 /* 41 * Common definition of VPR registers (IPIVPR, GTVPR, ...) 42 */ 43 #define VPR_MSK 0x80000000 /* Mask */ 44 #define VPR_A 0x40000000 /* Activity */ 45 #define VPR_P 0x00800000 /* Polatity */ 46 #define VPR_P_HIGH 0x00800000 /* Active High */ 47 #define VPR_S 0x00400000 /* Sense */ 48 #define VPR_S_LEVEL 0x00400000 /* Level Sensitive */ 49 #define VPR_PRIORITY 0x000f0000 /* Priority */ 50 #define VPR_PRIORITY_GET(n) (((n) >> 16) & 0x000f) 51 #define VPR_PRIORITY_MAKE(n) (((n) & 0x000f) << 16) 52 #define VPR_VECTOR 0x0000ffff /* Vector */ 53 #define VPR_VECTOR_GET(n) (((n) >> 0) & 0xffff) 54 #define VPR_VECTOR_MAKE(n) (((n) & 0xffff) << 0) 55 56 #define VPR_LEVEL_LOW (VPR_S_LEVEL) 57 #define VPR_LEVEL_HIGH (VPR_S_LEVEL | VPR_P_HIGH) 58 59 /* 60 * Common definition of DR registers (IPIVPR, GTVPR, ...) 61 */ 62 #define DR_EP 0x80000000 /* external signal */ 63 #define DR_CI(n) (1 << (30 - (n))) /* critical intr cpu n */ 64 #define DR_P(n) (1 << (n)) /* intr cpu n */ 65 66 67 #define OPENPIC_BRR1 0x0000 /* Block Revision 1 */ 68 #define BRR1_IPID(n) (((n) >> 16) & 0xffff) 69 #define BRR1_IPMJ(n) (((n) >> 8) & 0x00ff) 70 #define BRR1_IPMN(n) (((n) >> 0) & 0x00ff) 71 #define OPENPIC_BRR2 0x0010 /* Block Revision 2 */ 72 #define BRR2_IPINT0(n) (((n) >> 16) & 0xff) 73 #define BRR2_IPCFG0(n) (((n) >> 0) & 0xff) 74 75 #define OPENPIC_IPIDR(n) (0x0040 + 0x10 * (n)) 76 77 #define OPENPIC_CTPR 0x0080 78 #define OPENPIC_WHOAMI 0x0090 79 #define OPENPIC_IACK 0x00a0 80 #define OPENPIC_EOI 0x00b0 81 82 #define OPENPIC_FRR 0x1000 /* Feature Reporting */ 83 #define FRR_NIRQ_GET(n) (((n) >> 16) & 0x7ff) /* intr sources - 1 */ 84 #define FRR_NCPU_GET(n) (((n) >> 8) & 0x01f) /* cpus - 1 */ 85 #define FRR_VID_GET(n) (((n) >> 0) & 0x0ff) /* version id */ 86 #define OPENPIC_GCR 0x1020 /* Global Configuration */ 87 #define GCR_RST 0x80000000 /* Reset */ 88 #define GCR_M 0x20000000 /* Mixed Mode */ 89 #define OPENPIC_VIR 0x1080 /* Vendor Identification */ 90 #define OPENPIC_PIR 0x1090 /* Processor Initialization */ 91 92 #define OPENPIC_IPIVPR(n) (0x10a0 + 0x10 * (n)) 93 #define OPENPIC_SVR 0x10e0 94 #define SVR_VECTOR 0x0000ffff /* Vector */ 95 #define SVR_VECTOR_GET(n) (((n) >> 0) & 0xffff) 96 #define SVR_VECTOR_MAKE(n) (((n) & 0xffff) << 0) 97 98 #define OPENPIC_TFRR 0x10f0 99 #define OPENPIC_GTCCR(cpu, n) (0x1100 + 0x40 * (n) + 0x1000 * (cpu)) 100 #define GTCCR_TOG 0x80000000 101 #define GTCCR_COUNT 0x7fffffff 102 #define OPENPIC_GTBCR(cpu, n) (0x1110 + 0x40 * (n) + 0x1000 * (cpu)) 103 #define GTBCR_CI 0x80000000 /* Count Inhibit */ 104 #define GTBCR_BASECNT 0x7fffffff /* Base Count */ 105 #define OPENPIC_GTVPR(cpu, n) (0x1120 + 0x40 * (n) + 0x1000 * (cpu)) 106 #define OPENPIC_GTDR(cpu, n) (0x1130 + 0x40 * (n) + 0x1000 * (cpu)) 107 #define OPENPIC_TCR 0x1300 108 #define TCR_ROVR(n) (1 << (24 + (n))) /* timer n rollover */ 109 #define TCR_RTM 0x00010000 /* real time source */ 110 #define TCR_CLKR 0x00000300 /* clock ratio */ 111 #define TCR_CLKR_64 0x00000300 /* divide by .. */ 112 #define TCR_CLKR_32 0x00000200 /* divide by .. */ 113 #define TCR_CLKR_16 0x00000100 /* divide by .. */ 114 #define TCR_CLKR_8 0x00000000 /* divide by .. */ 115 #define TCR_CASC 0x00000007 /* cascase timers */ 116 #define TCR_CASC_0123 0x00000007 117 #define TCR_CASC_123 0x00000006 118 #define TCR_CASC_01_23 0x00000005 119 #define TCR_CASC_23 0x00000004 120 #define TCR_CASC_012 0x00000003 121 #define TCR_CASC_12 0x00000002 122 #define TCR_CASC_01 0x00000001 123 #define TCR_CASC_OFF 0x00000000 124 125 #define OPENPIC_ERQSR 0x1308 /* ext. intr summary */ 126 #define ERQSR_A(n) (1 << (31 - (n))) /* intr <n> active */ 127 #define OPENPIC_IRQSR0 0x1310 /* irq out summary 0 */ 128 #define IRSR0_MSI_A(n) (1 << (31 - (n))) /* msg sig intr <n> */ 129 #define IRSR0_MSG_A(n) (1 << (20 - ((n) ^ 4))) /* shared msg intr */ 130 #define IRSR0_EXT_A(n) (1 << (11 - (n))) /* ext int <n> active */ 131 #define OPENPIC_IRQSR1 0x1320 /* irq out summary 1 */ 132 #define IRQSR1_A(n) (1 << (31 - ((n) - 0))) /* intr <n> active */ 133 #define OPENPIC_IRQSR2 0x1324 /* irq out summary 2 */ 134 #define IRQSR2_A(n) (1 << (31 - ((n) - 32))) /* intr <n> active */ 135 #define OPENPIC_CISR0 0x1330 136 #define OPENPIC_CISR1 0x1340 137 #define CISR1_A(n) (1 << (31 - ((n) - 0))) /* intr <n> active */ 138 #define OPENPIC_CISR2 0x1344 139 #define CISR2_A(n) (1 << (31 - ((n) - 32))) /* intr <n> active */ 140 141 /* 142 * Performance Monitor Mask Registers 143 */ 144 #define OPENPIC_PMMR0(n) (0x1350 + 0x20 * (n)) 145 #define PMMR0_MShl(n) (1 << (31 - (n))) 146 #define PMMR0_IPI(n) (1 << (24 - (n))) 147 #define PMMR0_TIMER(n) (1 << (20 - (n))) 148 #define PMMR0_MSG(n) (1 << (16 - ((n) & 7))) 149 #define PMMR0_EXT(n) (1 << (12 - (n))) 150 #define OPENPIC_PMMR1(n) (0x1360 + 0x20 * (n)) 151 #define PMMR1_INT(n) (1 << (31 - ((n) - 0))) /* intr <n> active */ 152 #define OPENPIC_PMMR2(n) (0x1364 + 0x20 * (n)) 153 #define PMMR2_INT(n) (1 << (31 - ((n) - 32))) /* intr <n> active */ 154 155 /* 156 * Message Registers 157 */ 158 #define OPENPIC_MSGR(cpu, n) (0x1400 + 0x1000 * (cpu) + 0x10 * (n)) 159 #define OPENPIC_MER(cpu) (0x1500 + 0x1000 * (cpu)) 160 #define MER_MSG(n) (1 << (n)) 161 #define OPENPIC_MSR(cpu) (0x1510 + 0x1000 * (cpu)) 162 #define MSR_MSG(n) (1 << (n)) 163 164 #define OPENPIC_MSIR(n) (0x1600 + 0x10 * (n)) 165 #define OPENPIC_MSISR 0x1720 166 #define MSIR_SR(n) (1 << (n)) 167 #define OPENPIC_MSIIR 0x1740 168 #define MSIIR_BIT(srs, ibs) (((srs) << 29) | ((ibs) << 24)) 169 170 /* 171 * Interrupt Source Configuration Registers 172 */ 173 #define OPENPIC_EIVPR(n) (0x10000 + 0x20 * (n)) 174 #define OPENPIC_EIDR(n) (0x10010 + 0x20 * (n)) 175 #define OPENPIC_IIVPR(n) (0x10200 + 0x20 * (n)) 176 #define OPENPIC_IIDR(n) (0x10210 + 0x20 * (n)) 177 #define OPENPIC_MIVPR(n) (0x11600 + 0x20 * (n)) 178 #define OPENPIC_MIDR(n) (0x11610 + 0x20 * (n)) 179 #define OPENPIC_MSIVPR(n) (0x11c00 + 0x20 * (n)) 180 #define OPENPIC_MSIDR(n) (0x11c10 + 0x20 * (n)) 181 182 #define MPC8536_EXTERNALSOURCES 12 183 #define MPC8536_ONCHIPSOURCES 64 184 #define MPC8536_ONCHIPBITMAP { 0xfe07ffff, 0x05501c00 } 185 #define MPC8536_IPISOURCES 8 186 #define MPC8536_TIMERSOURCES 8 187 #define MPC8536_MISOURCES 4 188 #define MPC8536_MSIGROUPSOURCES 8 189 #define MPC8536_NCPUS 1 190 #define MPC8536_SOURCES /* 104 */ \ 191 (MPC8536_EXTERNALSOURCES \ 192 + MPC8536_ONCHIPSOURCES \ 193 + MPC8536_MSIGROUPSOURCES \ 194 + MPC8536_NCPUS*(MPC8536_IPISOURCES \ 195 + MPC8536_TIMERSOURCES \ 196 + MPC8536_MISOURCES)) 197 198 #define MPC8544_EXTERNALSOURCES 12 199 #define MPC8544_ONCHIPSOURCES 48 200 #define MPC8544_ONCHIPBITMAP { 0x3c07efff, 0x00000000 } 201 #define MPC8544_IPISOURCES 4 202 #define MPC8544_TIMERSOURCES 4 203 #define MPC8544_MISOURCES 4 204 #define MPC8544_MSIGROUPSOURCES 8 205 #define MPC8544_NCPUS 1 206 #define MPC8544_SOURCES /* 80 */ \ 207 (MPC8544_EXTERNALSOURCES \ 208 + MPC8544_ONCHIPSOURCES \ 209 + MPC8544_MSIGROUPSOURCES \ 210 + MPC8544_NCPUS*(MPC8544_IPISOURCES \ 211 + MPC8544_TIMERSOURCES \ 212 + MPC8544_MISOURCES)) 213 214 #define MPC8548_EXTERNALSOURCES 12 215 #define MPC8548_ONCHIPSOURCES 48 216 #define MPC8548_ONCHIPBITMAP { 0x3dffffff, 0x000000f3 } 217 #define MPC8548_IPISOURCES 4 218 #define MPC8548_TIMERSOURCES 4 219 #define MPC8548_MISOURCES 4 220 #define MPC8548_MSIGROUPSOURCES 8 221 #define MPC8548_NCPUS 1 222 #define MPC8548_SOURCES /* 80 */ \ 223 (MPC8548_EXTERNALSOURCES \ 224 + MPC8548_ONCHIPSOURCES \ 225 + MPC8548_MSIGROUPSOURCES \ 226 + MPC8548_NCPUS*(MPC8548_IPISOURCES \ 227 + MPC8548_TIMERSOURCES \ 228 + MPC8548_MISOURCES)) 229 230 #define MPC8555_EXTERNALSOURCES 12 231 #define MPC8555_ONCHIPSOURCES 32 232 #define MPC8555_ONCHIPBITMAP { 0x7d1c63ff, 0 } 233 #define MPC8555_IPISOURCES 4 234 #define MPC8555_TIMERSOURCES 4 235 #define MPC8555_MISOURCES 4 236 #define MPC8555_MSIGROUPSOURCES 0 237 #define MPC8555_NCPUS 1 238 #define MPC8555_SOURCES /* 56 */ \ 239 (MPC8555_EXTERNALSOURCES \ 240 + MPC8555_ONCHIPSOURCES \ 241 + MPC8555_MSIGROUPSOURCES \ 242 + MPC8555_NCPUS*(MPC8555_IPISOURCES \ 243 + MPC8555_TIMERSOURCES \ 244 + MPC8555_MISOURCES)) 245 246 #define MPC8568_EXTERNALSOURCES 12 247 #define MPC8568_ONCHIPSOURCES 48 248 #define MPC8568_ONCHIPBITMAP { 0xfd1c65ff, 0x000b9e7 } 249 #define MPC8568_IPISOURCES 4 250 #define MPC8568_TIMERSOURCES 4 251 #define MPC8568_MISOURCES 4 252 #define MPC8568_MSIGROUPSOURCES 8 253 #define MPC8568_NCPUS 1 254 #define MPC8568_SOURCES /* 80 */ \ 255 (MPC8568_EXTERNALSOURCES \ 256 + MPC8568_ONCHIPSOURCES \ 257 + MPC8568_MSIGROUPSOURCES \ 258 + MPC8568_NCPUS*(MPC8568_IPISOURCES \ 259 + MPC8568_TIMERSOURCES \ 260 + MPC8568_MISOURCES)) 261 262 #define MPC8572_EXTERNALSOURCES 12 263 #define MPC8572_ONCHIPSOURCES 64 264 #define MPC8572_ONCHIPBITMAP { 0xdeffffff, 0xf8ff93f3 } 265 #define MPC8572_IPISOURCES 4 266 #define MPC8572_TIMERSOURCES 4 267 #define MPC8572_MISOURCES 4 268 #define MPC8572_MSIGROUPSOURCES 8 269 #define MPC8572_NCPUS 2 270 #define MPC8572_SOURCES /* 108 */ \ 271 (MPC8572_EXTERNALSOURCES \ 272 + MPC8572_ONCHIPSOURCES \ 273 + MPC8572_MSIGROUPSOURCES \ 274 + MPC8572_NCPUS*(MPC8572_IPISOURCES \ 275 + MPC8572_TIMERSOURCES \ 276 + MPC8572_MISOURCES)) 277 278 #define P1023_EXTERNALSOURCES 12 279 #define P1023_ONCHIPSOURCES 64 280 #define P1023_ONCHIPBITMAP { 0xbc07f5f9, 0xf0000e00 } 281 #define P1023_IPISOURCES 4 282 #define P1023_TIMERSOURCES 4/*8?*/ 283 #define P1023_MISOURCES 4/*8?*/ 284 #define P1023_MSIGROUPSOURCES 8 285 #define P1023_NCPUS 2 286 #define P1023_SOURCES /* 116 */ \ 287 (P1023_EXTERNALSOURCES \ 288 + P1023_ONCHIPSOURCES \ 289 + P1023_MSIGROUPSOURCES \ 290 + P1023_NCPUS*(P1023_IPISOURCES \ 291 + P1023_TIMERSOURCES \ 292 + P1023_MISOURCES)) 293 #define P1017_NCPUS 1 294 #define P1017_SOURCES \ 295 (P1023_EXTERNALSOURCES \ 296 + P1023_ONCHIPSOURCES \ 297 + P1023_MSIGROUPSOURCES \ 298 + P1017_NCPUS*(P1023_IPISOURCES \ 299 + P1023_TIMERSOURCES \ 300 + P1023_MISOURCES)) 301 302 #define P1025_EXTERNALSOURCES 6 303 #define P1025_ONCHIPSOURCES 64 304 #define P1025_ONCHIPBITMAP { 0xbd1fffff, 0x01789c18 } 305 #define P1025_IPISOURCES 4 306 #define P1025_TIMERSOURCES 4 307 #define P1025_MISOURCES 4 308 #define P1025_MSIGROUPSOURCES 8 309 #define P1025_NCPUS 2 310 #define P1025_SOURCES /* 102 */ \ 311 (P1025_EXTERNALSOURCES \ 312 + P1025_ONCHIPSOURCES \ 313 + P1025_MSIGROUPSOURCES \ 314 + P1025_NCPUS*(P1025_IPISOURCES \ 315 + P1025_TIMERSOURCES \ 316 + P1025_MISOURCES)) 317 #define P1016_NCPUS 1 318 #define P1016_SOURCES \ 319 (P1025_EXTERNALSOURCES \ 320 + P1025_ONCHIPSOURCES \ 321 + P1025_MSIGROUPSOURCES \ 322 + P1016_NCPUS*(P1025_IPISOURCES \ 323 + P1025_TIMERSOURCES \ 324 + P1025_MISOURCES)) 325 326 #define P20x0_EXTERNALSOURCES 12 327 #define P20x0_ONCHIPSOURCES 64 328 #define P20x0_ONCHIPBITMAP { 0xbd1ff7ff, 0xf17005e7 } 329 #define P20x0_IPISOURCES 4 330 #define P20x0_TIMERSOURCES 4 331 #define P20x0_MISOURCES 4 332 #define P20x0_MSIGROUPSOURCES 8 333 #define P2020_NCPUS 2 334 #define P2020_SOURCES /* 108 */ \ 335 (P20x0_EXTERNALSOURCES \ 336 + P20x0_ONCHIPSOURCES \ 337 + P20x0_MSIGROUPSOURCES \ 338 + P2020_NCPUS*(P20x0_IPISOURCES \ 339 + P20x0_TIMERSOURCES \ 340 + P20x0_MISOURCES)) 341 #define P2010_NCPUS 1 342 #define P2010_SOURCES \ 343 (P20x0_EXTERNALSOURCES \ 344 + P20x0_ONCHIPSOURCES \ 345 + P20x0_MSIGROUPSOURCES \ 346 + P2010_NCPUS*(P20x0_IPISOURCES \ 347 + P20x0_TIMERSOURCES \ 348 + P20x0_MISOURCES)) 349 350 /* 351 * Per-CPU Registers 352 */ 353 #define OPENPIC_IPIDRn(cpu, n) (0x20040 + 0x1000 * (cpu) + 0x10 * (n)) 354 #define OPENPIC_CTPRn(cpu) (0x20080 + 0x1000 * (cpu)) 355 #define OPENPIC_WHOAMIn(cpu) (0x20090 + 0x1000 * (cpu)) 356 #define OPENPIC_IACKn(cpu) (0x200a0 + 0x1000 * (cpu)) 357 #define OPENPIC_EOIn(cpu) (0x200b0 + 0x1000 * (cpu)) 358 359 #define IRQ_SPURIOUS 0xffff 360 361 #define ISOURCE_L2 0 362 #define ISOURCE_ERROR 0 363 #define ISOURCE_ECM 1 364 #define ISOURCE_ETSEC1_G1_TX 1 /* P1025 */ 365 #define ISOURCE_DDR 2 366 #define ISOURCE_ETSEC1_G1_RX 2 /* P1025 */ 367 #define ISOURCE_LBC 3 368 #define ISOURCE_DMA_CHAN1 4 369 #define ISOURCE_DMA_CHAN2 5 370 #define ISOURCE_DMA_CHAN3 6 371 #define ISOURCE_DMA_CHAN4 7 372 #define ISOURCE_PCIEX3_MPC8572 8 /* MPC8572/P20x0/P1025 */ 373 #define ISOURCE_PCI1 8 /* MPC8548/MPC8544/MPC8536/MPC8555 */ 374 #define ISOURCE_ETSEC1_G1_ERR 8 /* P1025 */ 375 #define ISOURCE_FMAN 8 /* P1023 */ 376 #define ISOURCE_PCI2 9 /* MPC8548 */ 377 #define ISOURCE_PCIEX2 9 /* MPC8544/MPC8572/MPC8536/P20x0 */ 378 #define ISOURCE_ETSEC3_G1_TX 9 /* P1025 */ 379 #define ISOURCE_PCIEX 10 380 #define ISOURCE_ETSEC3_G1_RX 10 /* P1025 */ 381 #define ISOURCE_MDIO 10 /* P1023 */ 382 #define ISOURCE_PCIEX3 11 /* MPC8544/MPC8536 */ 383 #define ISOURCE_ETSEC3_G1_ERR 11 /* P1025 */ 384 #define ISOURCE_USB1 12 /* MPC8536/P20x0/P1025/P1023 */ 385 #define ISOURCE_ETSEC1_TX 13 386 #define ISOURCE_QMAN0 13 /* P1023 */ 387 #define ISOURCE_ETSEC1_RX 14 388 #define ISOURCE_BMAN0 14 /* P1023 */ 389 #define ISOURCE_ETSEC3_TX 15 390 #define ISOURCE_QMAN1 15 /* P1023 */ 391 #define ISOURCE_ETSEC3_RX 16 392 #define ISOURCE_BMAN1 16 /* P1023 */ 393 #define ISOURCE_ETSEC3_ERR 17 394 #define ISOURCE_QMAN2 17 /* P1023 */ 395 #define ISOURCE_ETSEC1_ERR 18 396 #define ISOURCE_BMAN2 18 /* P1023 */ 397 #define ISOURCE_ETSEC2_TX 19 /* !MPC8544/!MPC8536/!P1025 */ 398 #define ISOURCE_ETSEC2_RX 20 /* !MPC8544/!MPC8536/!P1025 */ 399 #define ISOURCE_ETSEC4_TX 21 /* !MPC8544/!MPC8536/!P20x0/!P1025 */ 400 #define ISOURCE_ETSEC4_RX 22 /* !MPC8544/!MPC8536/!P20x0/!P1025 */ 401 #define ISOURCE_ETSEC4_ERR 23 /* !MPC8544/!MPC8536/!P20x0/!P1025 */ 402 #define ISOURCE_ETSEC2_ERR 24 /* !MPC8544/!MPC8536 */ 403 #define ISOURCE_FEC 25 /* MPC8572 */ 404 #define ISOURCE_SATA2 25 /* MPC8536 */ 405 #define ISOURCE_DUART 26 406 #define ISOURCE_I2C 27 407 #define ISOURCE_PERFMON 28 408 #define ISOURCE_SECURITY1 29 409 #define ISOURCE_CPM 30 /* MPC8555 */ 410 #define ISOURCE_QEB_LOW 30 /* MPC8568 */ 411 #define ISOURCE_USB2 30 /* MPC8536 */ 412 #define ISOURCE_GPIO 31 /* MPC8572/!MPC8548 */ 413 #define ISOURCE_QEB_PORT 31 /* MPC8568/P1025 */ 414 #define ISOURCE_SRIO_EWPU 32 /* !MPC8548&!P20x0&!P1025 */ 415 #define ISOURCE_SRIO_ODBELL 33 /* !MPC8548&!P20x0&!P1025 */ 416 #define ISOURCE_SRIO_IDBELL 34 /* !MPC8548&!P20x0&!P1025 */ 417 #define ISOURCE_ETSEC2_G1_TX 35 /* P1025 */ 418 #define ISOURCE_ETSEC2_G1_RX 36 /* P1025 */ 419 #define ISOURCE_SRIO_OMU1 37 /* !MPC8548&!P20x0&!P1025 */ 420 #define ISOURCE_SRIO_IMU1 38 /* !MPC8548&!P20x0&!P1025 */ 421 #define ISOURCE_SRIO_OMU2 39 /* !MPC8548&!P20x0&!P1025 */ 422 #define ISOURCE_SRIO_IMU2 40 /* !MPC8548&!P20x0&!P1025 */ 423 #define ISOURCE_PME_GENERAL 41 /* MPC8572 */ 424 #define ISOURCE_SECURITY2_P1023 41 /* P1023 */ 425 #define ISOURCE_SECURITY2 42 /* MPC8572|MPC8536|P20x0|P1025 */ 426 #define ISOURCE_SEC_GENERAL 42 /* P1023 */ 427 #define ISOURCE_SPI 43 /* MPC8536|P20x0|P1025 */ 428 #define ISOURCE_QEB_IECC 43 /* MPC8568 */ 429 #define ISOURCE_USB3 44 /* MPC8536 */ 430 #define ISOURCE_QEB_MUECC 44 /* MPC8568|P1025 */ 431 #define ISOURCE_TLU1 45 /* MPC8568/MPC8572 */ 432 #define ISOURCE_46 46 433 #define ISOURCE_QEB_HIGH 47 /* MPC8548|P1025 */ 434 #define ISOURCE_PME_CHAN1 48 /* MPC8572 */ 435 #define ISOURCE_PME_CHAN2 49 /* MPC8572 */ 436 #define ISOURCE_PME_CHAN3 50 /* MPC8572 */ 437 #define ISOURCE_PME_CHAN4 51 /* MPC8572 */ 438 #define ISOURCE_ETSEC2_G1_ERR 51 /* P1025 */ 439 #define ISOURCE_ETSEC1_PTP 52 /* MPC8572|MPC8536|P20x0|P1025 */ 440 #define ISOURCE_ETSEC2_PTP 53 /* MPC8572|P20x0|P1025 */ 441 #define ISOURCE_ETSEC3_PTP 54 /* MPC8572|MPC8536|P20x0|P1025 */ 442 #define ISOURCE_ETSEC4_PTP 55 /* MPC8572 */ 443 #define ISOURCE_ESDHC 56 /* MPC8536|P20x0|P1025 */ 444 #define ISOURCE_57 57 445 #define ISOURCE_SATA1 58 /* MPC8536 */ 446 #define ISOURCE_TLU2 59 /* MPC8572 */ 447 #define ISOURCE_DMA2_CHAN1 60 /* MPC8572|P20x0|P1023 */ 448 #define ISOURCE_DMA2_CHAN2 61 /* MPC8572|P20x0|P1023 */ 449 #define ISOURCE_DMA2_CHAN3 62 /* MPC8572|P20x0|P1023 */ 450 #define ISOURCE_DMA2_CHAN4 63 /* MPC8572|P20x0|P1023 */ 451 452 #endif /* _POWERPC_BOOKE_OPENPICREG_H_ */ 453
Indexes created Sat Sep 20 22:09:52 GMT 2025