1 2 /************************************************************************** 3 4 Copyright 1998-1999 Precision Insight, Inc., Cedar Park, Texas. 5 Copyright 2002 David Dawes 6 7 All Rights Reserved. 8 9 Permission is hereby granted, free of charge, to any person obtaining a 10 copy of this software and associated documentation files (the 11 "Software"), to deal in the Software without restriction, including 12 without limitation the rights to use, copy, modify, merge, publish, 13 distribute, sub license, and/or sell copies of the Software, and to 14 permit persons to whom the Software is furnished to do so, subject to 15 the following conditions: 16 17 The above copyright notice and this permission notice (including the 18 next paragraph) shall be included in all copies or substantial portions 19 of the Software. 20 21 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 22 OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 23 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 24 IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR 25 ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 26 TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 27 SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 28 29 **************************************************************************/ 30 31 /* 32 * Authors: 33 * Keith Whitwell <keith (at) tungstengraphics.com> 34 * David Dawes <dawes (at) xfree86.org> 35 * 36 */ 37 38 #ifndef _INTEL_COMMON_H_ 39 #define _INTEL_COMMON_H_ 40 41 /* Provide substitutes for gcc's __FUNCTION__ on other compilers */ 42 #if !defined(__GNUC__) && !defined(__FUNCTION__) 43 # if defined(__STDC__) && (__STDC_VERSION__>=199901L) /* C99 */ 44 # define __FUNCTION__ __func__ 45 # else 46 # define __FUNCTION__ "" 47 # endif 48 #endif 49 50 51 #define PFX __FILE__,__LINE__,__FUNCTION__ 52 #define FUNCTION_NAME __FUNCTION__ 53 54 #ifdef I830DEBUG 55 #define MARKER() ErrorF("\n### %s:%d: >>> %s <<< ###\n\n", \ 56 __FILE__, __LINE__,__FUNCTION__) 57 #define DPRINTF I830DPRINTF 58 #else /* #ifdef I830DEBUG */ 59 #define MARKER() 60 #define DPRINTF I830DPRINTF_stub 61 static inline void 62 I830DPRINTF_stub(const char *filename, int line, const char *function, 63 const char *fmt, ...) 64 { 65 } 66 #endif /* #ifdef I830DEBUG */ 67 68 #define KB(x) ((x) * 1024) 69 #define MB(x) ((x) * KB(1024)) 70 71 /* Using usleep() makes things noticably slow. */ 72 #if 0 73 #define DELAY(x) usleep(x) 74 #else 75 #define DELAY(x) do {;} while (0) 76 #endif 77 78 #ifndef REG_DUMPER 79 /* I830 hooks for the I810 driver setup/probe. */ 80 extern const OptionInfoRec *I830AvailableOptions(int chipid, int busid); 81 extern void I830InitpScrn(ScrnInfoPtr pScrn); 82 83 /* Symbol lists shared by the i810 and i830 parts. */ 84 extern int I830EntityIndex; 85 86 extern void I830DPRINTF_stub(const char *filename, int line, 87 const char *function, const char *fmt, ...); 88 89 #ifdef _I830_H_ 90 #define PrintErrorState i830_dump_error_state 91 #define WaitRingFunc I830WaitLpRing 92 #define RecPtr pI830 93 #else 94 #define PrintErrorState I810PrintErrorState 95 #define WaitRingFunc I810WaitLpRing 96 #define RecPtr pI810 97 #endif 98 99 static inline void memset_volatile(volatile void *b, int c, size_t len) 100 { 101 int i; 102 103 for (i = 0; i < len; i++) 104 ((volatile char *)b)[i] = c; 105 } 106 107 static inline void memcpy_volatile(volatile void *dst, const void *src, 108 size_t len) 109 { 110 int i; 111 112 for (i = 0; i < len; i++) 113 ((volatile char *)dst)[i] = ((volatile char *)src)[i]; 114 } 115 116 /* Memory mapped register access macros */ 117 #define INREG8(addr) *(volatile uint8_t *)(RecPtr->MMIOBase + (addr)) 118 #define INREG16(addr) *(volatile uint16_t *)(RecPtr->MMIOBase + (addr)) 119 #define INREG(addr) *(volatile uint32_t *)(RecPtr->MMIOBase + (addr)) 120 #define INGTT(addr) *(volatile uint32_t *)(RecPtr->GTTBase + (addr)) 121 #define POSTING_READ(addr) (void)INREG(addr) 122 123 #define OUTREG8(addr, val) do { \ 124 *(volatile uint8_t *)(RecPtr->MMIOBase + (addr)) = (val); \ 125 if (I810_DEBUG&DEBUG_VERBOSE_OUTREG) { \ 126 ErrorF("OUTREG8(0x%lx, 0x%lx) in %s\n", (unsigned long)(addr), \ 127 (unsigned long)(val), FUNCTION_NAME); \ 128 } \ 129 } while (0) 130 131 #define OUTREG16(addr, val) do { \ 132 *(volatile uint16_t *)(RecPtr->MMIOBase + (addr)) = (val); \ 133 if (I810_DEBUG&DEBUG_VERBOSE_OUTREG) { \ 134 ErrorF("OUTREG16(0x%lx, 0x%lx) in %s\n", (unsigned long)(addr), \ 135 (unsigned long)(val), FUNCTION_NAME); \ 136 } \ 137 } while (0) 138 139 #define OUTREG(addr, val) do { \ 140 *(volatile uint32_t *)(RecPtr->MMIOBase + (addr)) = (val); \ 141 if (I810_DEBUG&DEBUG_VERBOSE_OUTREG) { \ 142 ErrorF("OUTREG(0x%lx, 0x%lx) in %s\n", (unsigned long)(addr), \ 143 (unsigned long)(val), FUNCTION_NAME); \ 144 } \ 145 } while (0) 146 147 /* To remove all debugging, make sure I810_DEBUG is defined as a 148 * preprocessor symbol, and equal to zero. 149 */ 150 #if 1 151 #define I810_DEBUG 0 152 #endif 153 #ifndef I810_DEBUG 154 #warning "Debugging enabled - expect reduced performance" 155 extern int I810_DEBUG; 156 #endif 157 158 #define DEBUG_VERBOSE_ACCEL 0x1 159 #define DEBUG_VERBOSE_SYNC 0x2 160 #define DEBUG_VERBOSE_VGA 0x4 161 #define DEBUG_VERBOSE_RING 0x8 162 #define DEBUG_VERBOSE_OUTREG 0x10 163 #define DEBUG_VERBOSE_MEMORY 0x20 164 #define DEBUG_VERBOSE_CURSOR 0x40 165 #define DEBUG_ALWAYS_SYNC 0x80 166 #define DEBUG_VERBOSE_DRI 0x100 167 #define DEBUG_VERBOSE_BIOS 0x200 168 #endif /* !REG_DUMPER */ 169 170 /* Size of the mmio region. 171 */ 172 #define I810_REG_SIZE 0x80000 173 174 #ifndef PCI_CHIP_I810 175 #define PCI_CHIP_I810 0x7121 176 #define PCI_CHIP_I810_DC100 0x7123 177 #define PCI_CHIP_I810_E 0x7125 178 #define PCI_CHIP_I815 0x1132 179 #define PCI_CHIP_I810_BRIDGE 0x7120 180 #define PCI_CHIP_I810_DC100_BRIDGE 0x7122 181 #define PCI_CHIP_I810_E_BRIDGE 0x7124 182 #define PCI_CHIP_I815_BRIDGE 0x1130 183 #endif 184 185 #ifndef PCI_CHIP_I830_M 186 #define PCI_CHIP_I830_M 0x3577 187 #define PCI_CHIP_I830_M_BRIDGE 0x3575 188 #endif 189 190 #ifndef PCI_CHIP_845_G 191 #define PCI_CHIP_845_G 0x2562 192 #define PCI_CHIP_845_G_BRIDGE 0x2560 193 #endif 194 195 #ifndef PCI_CHIP_I855_GM 196 #define PCI_CHIP_I855_GM 0x3582 197 #define PCI_CHIP_I855_GM_BRIDGE 0x3580 198 #endif 199 200 #ifndef PCI_CHIP_I865_G 201 #define PCI_CHIP_I865_G 0x2572 202 #define PCI_CHIP_I865_G_BRIDGE 0x2570 203 #endif 204 205 #ifndef PCI_CHIP_I915_G 206 #define PCI_CHIP_I915_G 0x2582 207 #define PCI_CHIP_I915_G_BRIDGE 0x2580 208 #endif 209 210 #ifndef PCI_CHIP_I915_GM 211 #define PCI_CHIP_I915_GM 0x2592 212 #define PCI_CHIP_I915_GM_BRIDGE 0x2590 213 #endif 214 215 #ifndef PCI_CHIP_E7221_G 216 #define PCI_CHIP_E7221_G 0x258A 217 /* Same as I915_G_BRIDGE */ 218 #define PCI_CHIP_E7221_G_BRIDGE 0x2580 219 #endif 220 221 #ifndef PCI_CHIP_I945_G 222 #define PCI_CHIP_I945_G 0x2772 223 #define PCI_CHIP_I945_G_BRIDGE 0x2770 224 #endif 225 226 #ifndef PCI_CHIP_I945_GM 227 #define PCI_CHIP_I945_GM 0x27A2 228 #define PCI_CHIP_I945_GM_BRIDGE 0x27A0 229 #endif 230 231 #ifndef PCI_CHIP_I945_GME 232 #define PCI_CHIP_I945_GME 0x27AE 233 #define PCI_CHIP_I945_GME_BRIDGE 0x27AC 234 #endif 235 236 #ifndef PCI_CHIP_IGD_GM 237 #define PCI_CHIP_IGD_GM 0xA011 238 #define PCI_CHIP_IGD_GM_BRIDGE 0xA010 239 #define PCI_CHIP_IGD_G 0xA001 240 #define PCI_CHIP_IGD_G_BRIDGE 0xA000 241 #endif 242 243 #ifndef PCI_CHIP_G35_G 244 #define PCI_CHIP_G35_G 0x2982 245 #define PCI_CHIP_G35_G_BRIDGE 0x2980 246 #endif 247 248 #ifndef PCI_CHIP_I965_Q 249 #define PCI_CHIP_I965_Q 0x2992 250 #define PCI_CHIP_I965_Q_BRIDGE 0x2990 251 #endif 252 253 #ifndef PCI_CHIP_I965_G 254 #define PCI_CHIP_I965_G 0x29A2 255 #define PCI_CHIP_I965_G_BRIDGE 0x29A0 256 #endif 257 258 #ifndef PCI_CHIP_I946_GZ 259 #define PCI_CHIP_I946_GZ 0x2972 260 #define PCI_CHIP_I946_GZ_BRIDGE 0x2970 261 #endif 262 263 #ifndef PCI_CHIP_I965_GM 264 #define PCI_CHIP_I965_GM 0x2A02 265 #define PCI_CHIP_I965_GM_BRIDGE 0x2A00 266 #endif 267 268 #ifndef PCI_CHIP_I965_GME 269 #define PCI_CHIP_I965_GME 0x2A12 270 #define PCI_CHIP_I965_GME_BRIDGE 0x2A10 271 #endif 272 273 #ifndef PCI_CHIP_G33_G 274 #define PCI_CHIP_G33_G 0x29C2 275 #define PCI_CHIP_G33_G_BRIDGE 0x29C0 276 #endif 277 278 #ifndef PCI_CHIP_Q35_G 279 #define PCI_CHIP_Q35_G 0x29B2 280 #define PCI_CHIP_Q35_G_BRIDGE 0x29B0 281 #endif 282 283 #ifndef PCI_CHIP_Q33_G 284 #define PCI_CHIP_Q33_G 0x29D2 285 #define PCI_CHIP_Q33_G_BRIDGE 0x29D0 286 #endif 287 288 #ifndef PCI_CHIP_GM45_GM 289 #define PCI_CHIP_GM45_GM 0x2A42 290 #define PCI_CHIP_GM45_BRIDGE 0x2A40 291 #endif 292 293 #ifndef PCI_CHIP_IGD_E_G 294 #define PCI_CHIP_IGD_E_G 0x2E02 295 #define PCI_CHIP_IGD_E_G_BRIDGE 0x2E00 296 #endif 297 298 #ifndef PCI_CHIP_G45_G 299 #define PCI_CHIP_G45_G 0x2E22 300 #define PCI_CHIP_G45_G_BRIDGE 0x2E20 301 #endif 302 303 #ifndef PCI_CHIP_Q45_G 304 #define PCI_CHIP_Q45_G 0x2E12 305 #define PCI_CHIP_Q45_G_BRIDGE 0x2E10 306 #endif 307 308 #ifndef PCI_CHIP_G41_G 309 #define PCI_CHIP_G41_G 0x2E32 310 #define PCI_CHIP_G41_G_BRIDGE 0x2E30 311 #endif 312 313 #ifndef PCI_CHIP_B43_G 314 #define PCI_CHIP_B43_G 0x2E42 315 #define PCI_CHIP_B43_G_BRIDGE 0x2E40 316 #endif 317 318 #ifndef PCI_CHIP_IGDNG_D_G 319 #define PCI_CHIP_IGDNG_D_G 0x0042 320 #define PCI_CHIP_IGDNG_D_G_BRIDGE 0x0040 321 #endif 322 323 #ifndef PCI_CHIP_IGDNG_M_G 324 #define PCI_CHIP_IGDNG_M_G 0x0046 325 #define PCI_CHIP_IGDNG_M_G_BRIDGE 0x0044 326 #endif 327 328 #define I810_MEMBASE(p,n) (p)->regions[(n)].base_addr 329 #define VENDOR_ID(p) (p)->vendor_id 330 #define DEVICE_ID(p) (p)->device_id 331 #define SUBVENDOR_ID(p) (p)->subvendor_id 332 #define SUBSYS_ID(p) (p)->subdevice_id 333 #define CHIP_REVISION(p) (p)->revision 334 335 #define IS_I810(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I810 || \ 336 DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I810_DC100 || \ 337 DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I810_E) 338 #define IS_I815(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I815) 339 #define IS_I830(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I830_M) 340 #define IS_845G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_845_G) 341 #define IS_I85X(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I855_GM) 342 #define IS_I852(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I855_GM && (pI810->variant == I852_GM || pI810->variant == I852_GME)) 343 #define IS_I855(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I855_GM && (pI810->variant == I855_GM || pI810->variant == I855_GME)) 344 #define IS_I865G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I865_G) 345 346 #define IS_I915G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I915_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_E7221_G) 347 #define IS_I915GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I915_GM) 348 #define IS_I945G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_G) 349 #define IS_I945GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_GME) 350 #define IS_IGDGM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGD_GM) 351 #define IS_IGDG(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGD_G) 352 #define IS_IGD(pI810) (IS_IGDG(pI810) || IS_IGDGM(pI810)) 353 #define IS_GM45(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_GM45_GM) 354 #define IS_G4X(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGD_E_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G45_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q45_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G41_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_B43_G || IS_GM45(pI810)) 355 #define IS_I965GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME) 356 #define IS_965_Q(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_Q) 357 #define IS_IGDNG_D(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGDNG_D_G) 358 #define IS_IGDNG_M(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGDNG_M_G) 359 #define IS_IGDNG(pI810) (IS_IGDNG_D(pI810) || IS_IGDNG_M(pI810)) 360 #define IS_I965G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G35_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_Q || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I946_GZ || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME || IS_G4X(pI810) || IS_IGDNG(pI810)) 361 #define IS_G33CLASS(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G33_G ||\ 362 DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q35_G ||\ 363 DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q33_G || \ 364 IS_IGD(pI810)) 365 #define IS_I9XX(pI810) (IS_I915G(pI810) || IS_I915GM(pI810) || IS_I945G(pI810) || IS_I945GM(pI810) || IS_I965G(pI810) || IS_G33CLASS(pI810)) 366 #define IS_I915(pI810) (IS_I915G(pI810) || IS_I915GM(pI810) || IS_I945G(pI810) || IS_I945GM(pI810) || IS_G33CLASS(pI810)) 367 368 #define IS_MOBILE(pI810) (IS_I830(pI810) || IS_I85X(pI810) || IS_I915GM(pI810) || IS_I945GM(pI810) || IS_I965GM(pI810) || IS_GM45(pI810) || IS_IGD(pI810) || IS_IGDNG_M(pI810)) 369 /* mark chipsets for using gfx VM offset for overlay */ 370 #define OVERLAY_NOPHYSICAL(pI810) (IS_G33CLASS(pI810) || IS_I965G(pI810)) 371 /* mark chipsets without overlay hw */ 372 #define OVERLAY_NOEXIST(pI810) (IS_G4X(pI810) || IS_IGDNG(pI810)) 373 /* chipsets require graphics mem for hardware status page */ 374 #define HWS_NEED_GFX(pI810) (!pI810->use_drm_mode && \ 375 (IS_G33CLASS(pI810) ||\ 376 IS_G4X(pI810) || IS_IGDNG(pI810))) 377 /* chipsets require status page in non stolen memory */ 378 #define HWS_NEED_NONSTOLEN(pI810) (IS_G4X(pI810) || IS_IGDNG(pI810)) 379 #define SUPPORTS_INTEGRATED_HDMI(pI810) (IS_G4X(pI810) || IS_IGDNG(pI810)) 380 /* dsparb controlled by hw only */ 381 #define DSPARB_HWCONTROL(pI810) (IS_G4X(pI810) || IS_IGDNG(pI810)) 382 /* supports Y tiled surfaces (pre-965 Mesa isn't ready yet) */ 383 #define SUPPORTS_YTILING(pI810) (IS_I965G(pI830)) 384 385 #define GTT_PAGE_SIZE KB(4) 386 #define ROUND_TO(x, y) (((x) + (y) - 1) / (y) * (y)) 387 #define ROUND_DOWN_TO(x, y) ((x) / (y) * (y)) 388 #define ROUND_TO_PAGE(x) ROUND_TO((x), GTT_PAGE_SIZE) 389 #define ROUND_TO_MB(x) ROUND_TO((x), MB(1)) 390 #define PRIMARY_RINGBUFFER_SIZE KB(128) 391 #define MIN_SCRATCH_BUFFER_SIZE KB(16) 392 #define MAX_SCRATCH_BUFFER_SIZE KB(64) 393 #define HWCURSOR_SIZE GTT_PAGE_SIZE 394 #define HWCURSOR_SIZE_ARGB GTT_PAGE_SIZE * 4 395 #define OVERLAY_SIZE GTT_PAGE_SIZE 396 397 /* Use a 64x64 HW cursor */ 398 #define I810_CURSOR_X 64 399 #define I810_CURSOR_Y I810_CURSOR_X 400 401 #define PIPE_NAME(n) ('A' + (n)) 402 403 struct pci_device * 404 intel_host_bridge (void); 405 406 #endif /* _INTEL_COMMON_H_ */ 407
Indexes created Sun Jul 05 00:25:41 UTC 2026