1 /* $NetBSD: ixp12x0reg.h,v 1.9 2021/09/17 08:13:06 andvar Exp $ */ 2 3 /* 4 * Copyright (c) 2002, 2003 5 * Ichiro FUKUHARA <ichiro (at) ichiro.org>. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR 21 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #ifndef _IXP12X0REG_H_ 31 #define _IXP12X0REG_H_ 32 33 /* 34 * Physical memory map for the Intel IXP12X0 35 */ 36 37 /* 38 * FFFF FFFF --------------------------- 39 * Device 6 40 * SDRAM 41 * FF00 0000 - FF00 0014 42 * SDRAM Control Register 43 * D000 0000 - DFFF FFFF 44 * Prefetch 256MB 45 * C000 0000 - CFFF FFFF 46 * non-Prefetch 256MB 47 * C000 0000 --------------------------- 48 * Device 5 49 * AMBA Translation (ATU) 50 * B000 0000 --------------------------- 51 * Device 4 52 * Reserved 53 * A000 0000 --------------------------- 54 * Device 3 55 * StrongARM Core System 56 * 9000 0000 --------------------------- 57 * Device 2 58 * Reserved 59 * 8000 0000 --------------------------- 60 * Device 1 61 * PCI UNIT 62 * 6000 0000 - 7FFF FFFF 63 * PCI Memory Cycle Access 64 * 5400 0000 - 5400 FFFF 65 * PCI I/O Cycle Access 66 * 5300 0000 - 53BF FFFF 67 * PCI Type0 Configuration Cycle Access 68 * 5200 0000 - 52FF FFFF 69 * PCI Type1 Configuration Cycle Access 70 * 4200 0000 - 4200 03FF 71 * Local PCI Configuration Space 72 * 4000 0000 --------------------------- 73 * Device 0 74 * SRAM UNIT 75 * 0000 0000 --------------------------- 76 */ 77 78 79 /* 80 * Virtual memory map for the Intel IXP12X0 integrated devices 81 * 82 * IXP12x0 processors have many device registers at very lower addresses. 83 * To make user process space wider, we map the registers at lower address 84 * to upper address using address translation of virtual memory system. 85 * 86 * Some device registers are statically mapped on upper address region. 87 * because we have to access them before bus_space is initialized. 88 * Most device is dynamically mapped by bus_space_map(). In this case, 89 * the actual mapped (virtual) address are not cared by device drivers. 90 */ 91 92 /* 93 * FFFF FFFF --------------------------- 94 * 95 * F400 0000 --------------------------- 96 * PCI Type 0 Configuration Cycle Access 97 * VA F300 0000 == PA 5300 0000 (16Mbyte) 98 * F300 0000 --------------------------- 99 * PCI Type 1 Configuration Cycle Access 100 * VA F200 0000 == PA 5200 0000 (16Mbyte) 101 * F200 0000 --------------------------- 102 * not used 103 * F020 0000 --------------------------- 104 * PCI Registers Accessible Through I/O 105 * VA F010 0000 == PA 5400 0000 (1Mbyte) 106 * F010 0000 --------------------------- 107 * not used 108 * F001 1000 --------------------------- 109 * PCI Registers Accessible Through StrongARM Core 110 * VA F001 0000 == PA 4200 0000 (4kbyte) 111 * F001 0300 - F001 036F TIMER 112 * F001 0200 - F001 0293 PCI_FIQ 113 * F001 0180 - F001 0193 PCI_IRQ 114 * F001 0000 --------------------------- 115 * StrongARM System and Peripheral Registers 116 * VA F000 0000 == PA 9000 0000 (64kbyte) 117 * F000 3400 - F000 3C03 UART 118 * F000 3400 - F000 3C03 UART 119 * F000 2000 - F000 3003 RTC 120 * F000 1C00 - F000 1C03 GPIO_DATA 121 * F000 1800 - F000 1C03 GPIO 122 * F000 1400 - F000 1403 IRQ 123 * F000 1000 - F000 1003 FIQ 124 * F000 0C00 - F000 0C03 PLL_CFG (not used at this address) 125 * F000 0000 --------------------------- 126 * Kernel text and data 127 * C000 0000 --------------------------- 128 * L2 tables for user process (XXX should be fixed) 129 * 8000 0000 --------------------------- 130 * PCI Registers Accessible Through Memory 131 * VA 6000 0000 == PA 6000 0000 (512Mbyte) 132 * 6000 0000 --------------------------- 133 * 5400 0000 --------------------------- 134 * 0000 0000 --------------------------- 135 * 136 */ 137 138 /* Virtual address for I/O space */ 139 #define IXP12X0_IO_VBASE 0xf0000000UL 140 141 /* StrongARM System and Peripheral Registers */ 142 #define IXP12X0_SYS_VBASE 0xf0000000UL 143 #define IXP12X0_SYS_HWBASE 0x90000000UL 144 #define IXP12X0_SYS_SIZE 0x00010000UL /* 64Kbyte */ 145 146 #define IXP12X0_PLL_CFG (IXP12X0_IO_VBASE + 0x0c00) 147 #define IXP12X0_PLL_CFG_CCF 0x1f 148 149 /* PCI Registers Accessible Through StrongARM Core */ 150 #define IXP12X0_PCI_VBASE 0xf0010000UL 151 #define IXP12X0_PCI_HWBASE 0x42000000UL 152 #define IXP12X0_PCI_SIZE 0x00001000UL /* 4Kbyte */ 153 154 /* PCI I/O Space */ 155 #define IXP12X0_PCI_IO_VBASE 0xf0100000UL 156 #define IXP12X0_PCI_IO_HWBASE 0x54000000UL 157 #define IXP12X0_PCI_IO_SIZE 0x00100000UL /* 1Mbyte */ 158 159 /* PCI Memory Space */ 160 #define IXP12X0_PCI_MEM_HWBASE 0x60000000UL /* VA == PA */ 161 #define IXP12X0_PCI_MEM_VBASE IXP12X0_PCI_MEM_HWBASE 162 #define IXP12X0_PCI_MEM_SIZE 0x20000000UL 163 164 /* PCI Type0/1 Configuration address */ 165 #define IXP12X0_PCI_TYPE0_HWBASE 0x53000000UL 166 #define IXP12X0_PCI_TYPE0_VBASE 0xf3000000UL 167 #define IXP12X0_PCI_TYPE0_SIZE 0x01000000UL /* 16MB */ 168 169 #define IXP12X0_PCI_TYPE1_HWBASE 0x52000000UL 170 #define IXP12X0_PCI_TYPE1_VBASE 0xf2000000UL 171 #define IXP12X0_PCI_TYPE1_SIZE 0x01000000UL /* 16MB */ 172 173 /* 174 * SlowPort I/O Register 175 */ 176 /* see. arch/evbarm/ixm1200/ixm1200reg.h */ 177 178 /* Physical register base addresses */ 179 /* #define IXP12X0_GPIO_VBASE */ 180 #define IXP12X0_GPIO_HWBASE 0x90001800UL 181 #define IXP12X0_GPIO_SIZE 0x00000800UL 182 183 /* Interrupts */ 184 #define IXP12X0_FIQ_VBASE (IXP12X0_IO_VBASE + 0x1000) 185 #define IXP12X0_FIQ_HWBASE 0x90001000UL 186 #define IXP12X0_FIQ_SIZE 0x00000004UL 187 #define IXP12X0_IRQ_VBASE (IXP12X0_IO_VBASE + 0x1400) 188 #define IXP12X0_IRQ_HWBASE 0x90001400UL 189 #define IXP12X0_IRQ_SIZE 0x00000004UL 190 191 /* 192 * Interrupt index assignment 193 * 194 * 195 * FIQ/IRQ bitmap in "StrongARM System and Peripheral Registers" 196 * 197 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 198 * bit 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 199 * +-+-------------------------------------------+-+-+-+-+-+-+-+---+ 200 * |M| |U|S|R|S|U|C|P| | 201 * |B| |A|D|T|R|E|I|C| | 202 * |Z| RES |R|R|C|A|N|N|I|RES| 203 * | | |T|A| |M|G|T| | | 204 * | | | |M| | | | | | | 205 * +-+-------------------------------------------+-+-+-+-+-+-+-+---+ 206 * 3 207 * index 1 8 7 6 5 4 3 2 208 * 209 * 210 * We Map a software interrupt queue index to the unused bits in the 211 * IRQ/FIQ registers. (in "StrongARM System and Peripheral Registers") 212 * 213 * XXX will need to revisit this if those bits are ever used in future 214 * steppings). 215 * 216 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 217 * bit 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 218 * +-+-+-+-+-+-----------------------------------+-+-+-+-+-+-+-+---+ 219 * |M|S|C|N|S| |U|S|R|S|U|C|P| | 220 * |B|O|L|E|E| |A|D|T|R|E|I|C| | 221 * |Z|F|O|T|R| RES |R|R|C|A|N|N|I|RES| 222 * | |T|C| |I| |T|A| |M|G|T| | | 223 * | | |K| |A| | |M| | | | | | | 224 * | | | | |L| | | | | | | | | | 225 * +-+-+-+-+-+-----------------------------------+-+-+-+-+-+-+-+---+ 226 * 3 3 2 2 2 227 * index 1 0 9 8 7 8 7 6 5 4 3 2 228 * 229 */ 230 231 #define NIRQ 64 232 #define SYS_NIRQ 32 233 234 #define IXP12X0_INTR_MBZ 31 235 #define IXP12X0_INTR_bit30 30 236 #define IXP12X0_INTR_bit29 29 237 #define IXP12X0_INTR_bit28 28 238 #define IXP12X0_INTR_bit27 27 239 #define IXP12X0_INTR_bit26 26 240 #define IXP12X0_INTR_bit25 25 241 #define IXP12X0_INTR_bit24 24 242 #define IXP12X0_INTR_bit23 23 243 #define IXP12X0_INTR_bit22 22 244 #define IXP12X0_INTR_bit21 21 245 #define IXP12X0_INTR_bit20 20 246 #define IXP12X0_INTR_bit19 19 247 #define IXP12X0_INTR_bit18 18 248 #define IXP12X0_INTR_bit17 17 249 #define IXP12X0_INTR_bit16 16 250 #define IXP12X0_INTR_bit15 15 251 #define IXP12X0_INTR_bit14 14 252 #define IXP12X0_INTR_bit13 13 253 #define IXP12X0_INTR_bit12 12 254 #define IXP12X0_INTR_bit11 11 255 #define IXP12X0_INTR_bit10 10 256 #define IXP12X0_INTR_bit9 9 257 #define IXP12X0_INTR_UART 8 258 #define IXP12X0_INTR_SDRAM 7 259 #define IXP12X0_INTR_RTC 6 260 #define IXP12X0_INTR_SRAM 5 261 #define IXP12X0_INTR_UENG 4 262 #define IXP12X0_INTR_CINT 3 263 #define IXP12X0_INTR_PCI 2 264 #define IXP12X0_INTR_bit1 1 265 #define IXP12X0_INTR_bit0 0 266 267 #define IXP12X0_INTR_MASK \ 268 ((1U << IXP12X0_INTR_MBZ) \ 269 | (1U << IXP12X0_INTR_UART) \ 270 | (1U << IXP12X0_INTR_SDRAM) \ 271 | (1U << IXP12X0_INTR_RTC) \ 272 | (1U << IXP12X0_INTR_SRAM) \ 273 | (1U << IXP12X0_INTR_UENG) \ 274 | (1U << IXP12X0_INTR_CINT)) 275 276 #endif /* _IXP12X0REG_H_ */ 277
Indexes created Mon Sep 29 15:09:53 GMT 2025