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    Searched defs:Idx1 (Results 1 - 4 of 4) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SILoadStoreOptimizer.cpp 986 // DS_WRITE_B32 addr, f(w), idx1
1560 unsigned Idx1;
1566 Idx1 = Idxs[0][Paired.Width - 1];
1570 Idx1 = Idxs[CI.Width][Paired.Width - 1];
1573 return std::make_pair(Idx0, Idx1);
SIISelLowering.cpp 5546 const int Idx1 = SVN->getMaskElt(I + 1);
5548 int VecIdx1 = Idx1 < SrcNumElts ? 0 : 1;
5550 int EltIdx1 = Idx1 < SrcNumElts ? Idx1 : Idx1 - SrcNumElts;
10617 SDValue Idx1 = Op1.getOperand(1);
10638 if (Idx1 != Op2.getOperand(1) || Idx2 != FMAOp2.getOperand(1) ||
10639 // Idx1 and Idx2 cannot be the same.
10640 Idx1 == Idx2)
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonVectorCombine.cpp 1332 Value *Idx1 = Gep1->getOperand(1);
1336 Simplify(CallBuilder(B, CreateSub(Idx0, Idx1)))))
1340 KnownBits Known1 = computeKnownBits(Idx1, DL, 0, &AC, Gep1, &DT);
1347 Value *AndU1 = Simplify(CallBuilder(B, CreateAnd(Idx1, MaskU)));
1358 Value *AndK1 = Simplify(CallBuilder(B, CreateAnd(Idx1, MaskK)));
  /src/external/apache2/llvm/dist/llvm/utils/TableGen/
CodeGenRegisters.cpp 1395 CodeGenSubRegIndex *Idx1 = I1.first;
1401 // Try composing Idx1 with another SubRegIndex.
1413 if (CodeGenSubRegIndex *Prev = Idx1->addComposite(Idx2, Idx3)) {
1415 if (!UserDefined.count({Idx1, Idx2}) ||
1416 agree(compose(Idx1, Idx2), SubRegAction.at(Idx3)))
1417 PrintWarning(Twine("SubRegIndex ") + Idx1->getQualifiedName() +

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