HomeSort by: relevance | last modified time | path
    Searched defs:Imm (Results 1 - 25 of 139) sorted by relevancy

1 2 3 4 5 6

  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/MCTargetDesc/
RISCVMatInt.h 21 int64_t Imm;
23 Inst(unsigned Opc, int64_t Imm) : Opc(Opc), Imm(Imm) {}
RISCVMCTargetDesc.cpp 112 int64_t Imm;
114 Imm = Inst.getOperand(1).getImm();
116 Imm = Inst.getOperand(2).getImm();
117 Target = Addr + Imm;
RISCVInstPrinter.cpp 126 unsigned Imm = MI->getOperand(OpNo).getImm();
127 auto SysReg = RISCVSysReg::lookupSysRegByEncoding(Imm);
131 O << Imm;
172 unsigned Imm = MI->getOperand(OpNo).getImm();
173 RISCVVType::printVType(Imm, O);
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
MIRFormatter.h 42 Optional<unsigned> OpIdx, int64_t Imm) const {
43 OS << Imm;
49 StringRef Src, int64_t &Imm,
  /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/MCTargetDesc/
AVRInstPrinter.cpp 158 int64_t Imm = Op.getImm();
163 if (Imm >= 0)
166 O << Imm;
  /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/MCTargetDesc/
BPFInstPrinter.cpp 76 auto Imm = OffsetOp.getImm();
77 if (Imm >= 0)
78 O << " + " << formatImm(Imm);
80 O << " - " << formatImm(-Imm);
101 int16_t Imm = Op.getImm();
102 O << ((Imm >= 0) ? "+" : "") << formatImm(Imm);
BPFMCTargetDesc.cpp 81 int16_t Imm;
83 Imm = Inst.getOperand(2).getImm();
85 Imm = Inst.getOperand(0).getImm();
89 Target = Addr + Size + Imm * Size;
BPFMCCodeEmitter.cpp 140 uint64_t Imm = MO.isImm() ? MO.getImm() : 0;
144 OSE.write<uint32_t>(Imm >> 32);
  /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/MCTargetDesc/
MSP430InstPrinter.cpp 41 int64_t Imm = Op.getImm() * 2 + 2;
43 if (Imm >= 0)
45 O << Imm;
MSP430MCCodeEmitter.cpp 171 int64_t Imm = MO.getImm();
172 switch (Imm) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
WebAssemblyRegNumbering.cpp 78 int64_t Imm = MI.getOperand(1).getImm();
80 << " -> WAReg " << Imm << "\n");
81 MFI.setWAReg(MI.getOperand(0).getReg(), Imm);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/MCTargetDesc/
LanaiMCTargetDesc.cpp 103 int64_t Imm = Inst.getOperand(0).getImm();
104 Target = Addr + Size + Imm;
107 int64_t Imm = Inst.getOperand(0).getImm();
111 if (Imm == 0)
114 Target = Imm;
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/
MipsInstPrinter.cpp 146 uint64_t Imm = MO.getImm();
147 Imm -= Offset;
148 Imm &= (1 << Bits) - 1;
149 Imm += Offset;
150 O << formatImm(Imm);
159 // Load/Store memory operands -- imm($reg)
  /src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/MCTargetDesc/
NVPTXInstPrinter.cpp 91 O << markup("<imm:") << formatImm(Op.getImm()) << markup(">");
101 int64_t Imm = MO.getImm();
105 if (Imm & NVPTX::PTXCvtMode::FTZ_FLAG)
109 if (Imm & NVPTX::PTXCvtMode::SAT_FLAG)
113 switch (Imm & NVPTX::PTXCvtMode::BASE_MASK) {
151 int64_t Imm = MO.getImm();
155 if (Imm & NVPTX::PTXCmpMode::FTZ_FLAG)
158 switch (Imm & NVPTX::PTXCmpMode::BASE_MASK) {
225 int Imm = (int) MO.getImm();
227 if (Imm)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/MCTargetDesc/
X86InstPrinterCommon.cpp 30 int64_t Imm = MI->getOperand(Op).getImm();
31 switch (Imm) {
54 int64_t Imm = MI->getOperand(Op).getImm();
55 switch (Imm) {
96 int64_t Imm = MI->getOperand(MI->getNumOperands() - 1).getImm();
97 switch (Imm) {
272 int64_t Imm = MI->getOperand(Op).getImm();
273 switch (Imm) {
X86ATTInstPrinter.cpp 85 int64_t Imm = MI->getOperand(MI->getNumOperands() - 1).getImm();
98 if (Imm >= 0 && Imm <= 7) {
156 if (Imm >= 0 && Imm <= 31) {
221 if (Imm >= 0 && Imm <= 7) {
298 if ((Imm >= 0 && Imm <= 2) || (Imm >= 4 && Imm <= 6))
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUExportClustering.cpp 35 unsigned Imm = TII->getNamedOperand(*MI, AMDGPU::OpName::tgt)->getImm();
36 return Imm >= AMDGPU::Exp::ET_POS0 && Imm <= AMDGPU::Exp::ET_POS_LAST;
AMDGPUInstructionSelector.h 74 int64_t Imm;
75 GEPInfo(const MachineInstr &GEP) : GEP(GEP), Imm(0) { }
301 bool isInlineImmediate16(int64_t Imm) const;
302 bool isInlineImmediate32(int64_t Imm) const;
303 bool isInlineImmediate64(int64_t Imm) const;
304 bool isInlineImmediate(const APFloat &Imm) const;
  /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
AVRRelaxMemOperations.cpp 93 int64_t Imm = MI.getOperand(1).getImm();
96 if (Imm > 63) {
106 .addImm(-Imm);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/
LanaiISelDAGToDAG.cpp 85 inline SDValue getI32Imm(unsigned Imm, const SDLoc &DL) {
86 return CurDAG->getTargetConstant(Imm, DL, MVT::i32);
108 int32_t Imm = CN->getSExtValue();
109 Offset = CurDAG->getTargetConstant(Imm, DL, CN->getValueType(0));
130 int16_t Imm = CN->getSExtValue();
131 Offset = CurDAG->getTargetConstant(Imm, DL, CN->getValueType(0));
143 int16_t Imm = CN->getSExtValue();
144 Offset = CurDAG->getTargetConstant(Imm, DL, CN->getValueType(0));
167 // Address of the form imm + reg
317 SDValue Imm = CurDAG->getTargetConstant(0, DL, MVT::i32)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/MCTargetDesc/
SparcInstPrinter.cpp 217 unsigned Imm = MI->getOperand(opNum).getImm();
219 if (Imm > 127) {
220 O << Imm;
226 if (Imm & (1 << i)) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/VE/
VEISelDAGToDAG.cpp 107 const APInt &Imm = N->getValueAPF().bitcastToAPInt();
108 uint64_t Val = Imm.getZExtValue();
109 if (Imm.getBitWidth() == 32) {
199 return false; // Let the reg+imm(=0) pattern catch this!
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86EvexToVex.cpp 162 MachineOperand &Imm = MI.getOperand(MI.getNumExplicitOperands()-1);
163 Imm.setImm(Imm.getImm() * Scale);
177 MachineOperand &Imm = MI.getOperand(MI.getNumExplicitOperands()-1);
178 int64_t ImmVal = Imm.getImm();
180 Imm.setImm(0x20 | ((ImmVal & 2) << 3) | (ImmVal & 1));
199 const MachineOperand &Imm = MI.getOperand(MI.getNumExplicitOperands()-1);
200 int64_t ImmVal = Imm.getImm();
216 // [Prefixes] [VEX] OPCODE ModR/M [SIB] [DISP] [IMM]
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
CombinerHelper.h 54 int64_t Imm;
60 int64_t Imm;
155 /// Match sext_inreg(load p), imm -> sextload p
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64RedundantCopyElimination.cpp 89 int32_t Imm;
90 RegImm(MCPhysReg Reg, int32_t Imm) : Reg(Reg), Imm(Imm) {}
333 KnownRegs.push_back(RegImm(CopyDstReg, KnownReg.Imm));
342 KnownRegs.push_back(RegImm(CopySrcReg, KnownReg.Imm));
394 if (IsCopy && KnownReg.Imm != 0)
400 if (KnownReg.Imm != SrcImm)
414 if (TRI->isSuperRegister(DefReg, KnownReg.Reg) && KnownReg.Imm < 0)

Completed in 37 milliseconds

1 2 3 4 5 6