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    Searched defs:InReg (Results 1 - 8 of 8) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCTLSDynamicCall.cpp 83 Register InReg = PPC::NoRegister;
88 InReg = MI.getOperand(1).getReg();
89 OrigRegs.push_back(InReg);
161 assert(InReg != PPC::NoRegister && "Operand must be a register");
162 Addi = BuildMI(MBB, I, DL, TII->get(Opc1), GPR3).addReg(InReg);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
StatepointLowering.cpp 1201 Register InReg = Record.payload.Reg;
1203 DAG.getDataLayout(), InReg, Relocate.getType(),
SelectionDAGBuilder.cpp 1455 Register InReg = It->second;
1458 DAG.getDataLayout(), InReg, Ty,
1652 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1654 RegsForValue RFV(*DAG.getContext(), TLI, DAG.getDataLayout(), InReg,
1956 AttributeList::ReturnIndex, Attribute::InReg);
1973 // 'inreg' on function refers to return value
2665 if (GuardCheckFn->hasAttribute(1, Attribute::AttrKind::InReg))
9338 Attrs.push_back(Attribute::InReg);
9510 // passed InReg - is surely an HVA
9518 // Set InReg Fla
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  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUCallLowering.cpp 441 // FIXME: How should these inputs interact with inreg / custom SGPR inputs?
620 const bool InReg = Arg.hasAttribute(Attribute::InReg);
623 if (!IsGraphics && InReg)
631 if (CC == CallingConv::AMDGPU_PS && !InReg && PSInputNum <= 15) {
AMDGPUInstructionSelector.cpp 1974 bool InReg = I.getOpcode() == AMDGPU::G_SEXT_INREG;
1975 bool Signed = I.getOpcode() == AMDGPU::G_SEXT || InReg;
2041 const TargetRegisterClass &SrcRC = InReg && DstSize > 32 ?
2059 if (DstSize > 32 && (SrcSize <= 32 || InReg)) {
2063 unsigned SubReg = InReg ? AMDGPU::sub0 : 0;
  /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
WebAssemblyISelLowering.cpp 374 Register InReg = MI.getOperand(1).getReg();
410 Tmp0 = MRI.createVirtualRegister(MRI.getRegClass(InReg));
411 Tmp1 = MRI.createVirtualRegister(MRI.getRegClass(InReg));
421 Tmp0 = InReg;
423 BuildMI(BB, DL, TII.get(Abs), Tmp0).addReg(InReg);
431 Tmp1 = MRI.createVirtualRegister(MRI.getRegClass(InReg));
447 BuildMI(FalseMBB, DL, TII.get(LoweredOpcode), FalseReg).addReg(InReg);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonISelLowering.cpp 837 bool InReg = VA.isRegLoc() &&
840 if (InReg) {
  /src/external/apache2/llvm/dist/clang/lib/CodeGen/
TargetInfo.cpp 673 "Unexpected InReg seen in arginfo in generic VAArg emitter!");
979 // Floating-point types don't go inreg.
1145 bool shouldAggregateUseDirect(QualType Ty, CCState &State, bool &InReg,
1689 bool &InReg,
1698 InReg = !IsMCUABI;
1820 bool InReg;
1821 if (shouldAggregateUseDirect(Ty, State, InReg, NeedsPadding)) {
1825 if (InReg)
1882 bool InReg = shouldPrimitiveUseInReg(Ty, State);
1885 if (InReg)
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