| /src/external/apache2/llvm/dist/llvm/lib/Transforms/Utils/ |
| MatrixUtils.cpp | 43 Value *Inc = B.CreateAdd(IV, Step, Name + ".step");
44 Value *Cond = B.CreateICmpNE(Inc, Bound, Name + ".cond");
46 IV->addIncoming(Inc, Latch);
|
| /src/external/apache2/llvm/dist/clang/lib/Driver/ |
| Job.cpp | 184 StringRef Inc = FlagRef.slice(2, StringRef::npos);
185 if (getAbsPath(Inc, NewInc)) {
194 StringRef Inc(Args[Idx + NumArgs - 1]);
195 if (!getAbsPath(Inc, NewInc))
|
| /src/external/apache2/llvm/dist/clang/lib/Analysis/ |
| ReachableCode.cpp | 638 const Expr *Inc = FS->getInc();
639 Loc = Inc->getBeginLoc();
640 R2 = Inc->getSourceRange();
|
| /src/external/apache2/llvm/dist/llvm/lib/Transforms/Instrumentation/ |
| MemProfiler.cpp | 486 Value *Inc = ConstantInt::get(Type::getInt64Ty(*C), 1);
487 ShadowValue = IRB.CreateAdd(ShadowValue, Inc);
|
| InstrProfiling.cpp | 439 InstrProfIncrementInst *Inc = dyn_cast<InstrProfIncrementInstStep>(Instr);
440 if (Inc)
441 return Inc;
451 InstrProfIncrementInst *Inc = castToIncrementInst(&*Instr);
452 if (Inc) {
453 lowerIncrement(Inc);
607 #include "llvm/ProfileData/InstrProfData.inc"
674 void InstrProfiling::lowerIncrement(InstrProfIncrementInst *Inc) {
675 GlobalVariable *Counters = getOrCreateRegionCounters(Inc);
677 IRBuilder<> Builder(Inc);
[all...] |
| /src/sys/external/bsd/compiler_rt/dist/lib/sanitizer_common/ |
| sanitizer_allocator_primary64.h | 378 void Inc(uptr i) const {
388 Inc(i);
503 counters.Inc(free_array[i] >> page_size_scaled_log);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonEarlyIfConv.cpp | 462 SmallVector<unsigned,2> Inc;
466 Inc.push_back(i);
468 assert(Inc.size() <= 2);
469 if (Inc.size() < 2)
|
| HexagonSplitDouble.cpp | 669 int64_t Inc = Load ? MI->getOperand(3).getImm()
677 .addImm(Inc);
|
| HexagonISelDAGToDAG.cpp | 55 #include "HexagonGenDAGISel.inc"
70 int32_t Inc = cast<ConstantSDNode>(Offset.getNode())->getSExtValue();
78 bool IsValidInc = HII->isValidAutoIncImm(LoadedVT, Inc);
128 SDValue IncV = CurDAG->getTargetConstant(Inc, dl, MVT::i32);
205 auto Inc = cast<ConstantSDNode>(IntN->getOperand(5));
206 SDValue I = CurDAG->getTargetConstant(Inc->getSExtValue(), dl, MVT::i32);
390 auto Inc = cast<ConstantSDNode>(IntN->getOperand(3));
391 SDValue I = CurDAG->getTargetConstant(Inc->getSExtValue(), DL, MVT::i32);
425 auto Inc = cast<ConstantSDNode>(IntN->getOperand(3));
426 SDValue I = CurDAG->getTargetConstant(Inc->getSExtValue(), DL, MVT::i32)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86LowerAMXIntrinsics.cpp | 123 Value *Inc = B.CreateAdd(IV, Step, Name + ".step");
124 Value *Cond = B.CreateICmpNE(Inc, Bound, Name + ".cond");
126 IV->addIncoming(Inc, Latch);
|
| /src/external/apache2/llvm/dist/llvm/lib/Transforms/InstCombine/ |
| InstCombineMulDivRem.cpp | 811 Value *Inc = Builder.CreateAdd(Op1, Op0);
812 Value *Cmp = Builder.CreateICmpULT(Inc, ConstantInt::get(Ty, 3));
|
| /src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/ |
| LoopRerollPass.cpp | 455 int64_t Inc;
457 // Loop reroll count; if Inc == 1, this records the scaling applied
459 // If Inc is not 1, Scale = Inc.
832 // If we found non-loop-inc, non-root users of Base, assume they are
982 Inc = IVToIncMap[IV];
985 if (std::abs(Inc) == 1) {
|
| LoopIdiomRecognize.cpp | 1513 ConstantInt *Inc = dyn_cast<ConstantInt>(Inst->getOperand(1));
1514 if (!Inc || !Inc->isOne())
1639 ConstantInt *Inc = dyn_cast<ConstantInt>(Inst->getOperand(1));
1640 if (!Inc || (!Inc->isOne() && !Inc->isMinusOne()))
1724 // %i.0 = phi [ %i0, %entry ], [ %inc, %while.cond ]
1727 // %inc = add nsw %i.0, 1
|
| /src/external/gpl3/gcc/dist/libsanitizer/sanitizer_common/ |
| sanitizer_allocator_primary64.h | 447 void Inc(uptr i) const {
457 Inc(i);
570 counters.Inc(free_array[i] >> page_size_scaled_log);
|
| /src/external/gpl3/gcc.old/dist/libsanitizer/sanitizer_common/ |
| sanitizer_allocator_primary64.h | 447 void Inc(uptr i) const {
457 Inc(i);
570 counters.Inc(free_array[i] >> page_size_scaled_log);
|
| /src/external/apache2/llvm/dist/clang/lib/CodeGen/ |
| CoverageMappingGen.cpp | 30 // This selects the coverage mapping format defined when `InstrProfData.inc`
1170 if (const Stmt *Inc = S->getInc()) {
1171 propagateCounts(addCounters(BackedgeCount, BodyBC.ContinueCount), Inc);
1611 #include "llvm/ProfileData/InstrProfData.inc"
1620 #include "llvm/ProfileData/InstrProfData.inc"
1710 #include "llvm/ProfileData/InstrProfData.inc"
1716 #include "llvm/ProfileData/InstrProfData.inc"
|
| /src/external/apache2/llvm/dist/libcxx/src/filesystem/ |
| operations.cpp | 311 const int Inc = P < End ? 1 : -1;
312 P += Inc;
314 P += Inc;
337 const int Inc = P < End ? 1 : -1;
338 P += Inc;
340 P += Inc;
341 if (P == End && Inc < 0) {
|
| /src/external/apache2/llvm/dist/clang/include/clang/AST/ |
| StmtOpenMP.h | 751 Expr *Inc;
812 Cond != nullptr && Init != nullptr && Inc != nullptr;
826 Inc = nullptr;
1098 void setInc(Expr *Inc) { Data->getChildren()[IncOffset] = Inc; }
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMISelDAGToDAG.cpp | 188 #include "ARMGenDAGISel.inc"
193 /// Indexed (pre/post inc/dec) load matching code for ARM.
1666 // The encoding of LDM is not how the rest of ISel expects a post-inc load to
2068 static bool isPerfectIncrement(SDValue Inc, EVT VecTy, unsigned NumVecs) {
2069 auto C = dyn_cast<ConstantSDNode>(Inc);
2142 SDValue Inc = N->getOperand(AddrOpIdx + 1);
2143 bool IsImmUpdate = isPerfectIncrement(Inc, VT, NumVecs);
2149 Ops.push_back(Inc);
2178 SDValue Inc = N->getOperand(AddrOpIdx + 1);
2179 assert(isa<ConstantSDNode>(Inc.getNode()) &
[all...] |
| ARMISelLowering.cpp | 314 // Pre and Post inc are supported on loads and stores
344 // Pre and Post inc are supported on loads and stores
424 // Pre and Post inc on these are legal, given the correct extends
1093 // Thumb-1 has limited post-inc load/store support - LDM r0!, {r1}.
14714 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
14715 ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode());
14777 Ops.push_back(Inc);
14845 // to post-inc the last of the them.
14913 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
14914 ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())
[all...] |
| /src/external/apache2/llvm/dist/clang/lib/Sema/ |
| TreeTransform.h | 394 #include "clang/Basic/AttrList.inc"
732 #include "clang/AST/StmtNodes.inc"
738 #include "llvm/Frontend/OpenMP/OMP.inc"
1379 Sema::FullExprArg Inc, SourceLocation RParenLoc,
1382 Inc, RParenLoc, Body);
2335 Expr *Inc, Stmt *LoopVar,
2363 Range, Begin, End, Cond, Inc, LoopVar,
3756 #include "clang/AST/StmtNodes.inc"
3762 #include "clang/AST/StmtNodes.inc"
3787 #include "llvm/Frontend/OpenMP/OMP.inc"
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| DAGCombiner.cpp | 15035 static bool getCombineLoadStoreParts(SDNode *N, unsigned Inc, unsigned Dec,
15042 if (!TLI.isIndexedLoadLegal(Inc, VT) && !TLI.isIndexedLoadLegal(Dec, VT))
15049 if (!TLI.isIndexedStoreLegal(Inc, VT) && !TLI.isIndexedStoreLegal(Dec, VT))
15057 if (!TLI.isIndexedMaskedLoadLegal(Inc, VT) &&
15066 if (!TLI.isIndexedMaskedStoreLegal(Inc, VT) &&
15442 SDValue Inc = LD->getOperand(2);
15447 assert((Inc.getOpcode() != ISD::TargetConstant ||
15448 !cast<ConstantSDNode>(Inc)->isOpaque()) &&
15450 if (Inc.getOpcode() == ISD::TargetConstant) {
15451 ConstantSDNode *ConstInc = cast<ConstantSDNode>(Inc);
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 7537 #include "AArch64GenAsmMatcher.inc"
14733 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
14734 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
14739 Inc = DAG.getRegister(AArch64::XZR, MVT::i64);
14761 Ops.push_back(Inc);
14905 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
14906 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
14913 Inc = DAG.getRegister(AArch64::XZR, MVT::i64);
14922 Ops.push_back(Inc);
17167 // We want inc-of-add for scalars and sub-of-not for vectors
[all...] |
