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    Searched defs:IndexReg (Results 1 - 19 of 19) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/MCTargetDesc/
X86ATTInstPrinter.cpp 399 const MCOperand &IndexReg = MI->getOperand(Op + X86::AddrIndexReg);
409 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))
416 if (IndexReg.getReg() || BaseReg.getReg()) {
421 if (IndexReg.getReg()) {
X86IntelInstPrinter.cpp 357 const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg);
371 if (IndexReg.getReg()) {
385 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
X86MCTargetDesc.cpp 544 const MCOperand &IndexReg = Inst.getOperand(MemOpStart + X86::AddrIndexReg);
547 if (SegReg.getReg() != 0 || IndexReg.getReg() != 0 || ScaleAmt.getImm() != 1 ||
X86MCCodeEmitter.cpp 167 unsigned IndexReg = Index.getReg();
169 if (STI.hasFeature(X86::Mode16Bit) && BaseReg == 0 && IndexReg == 0)
173 (IndexReg != 0 &&
174 X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg)))
184 const MCOperand &IndexReg = MI.getOperand(Op + X86::AddrIndexReg);
188 (IndexReg.getReg() != 0 &&
189 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg())))
192 assert(IndexReg.getReg() == 0 && "Invalid eip-based address.");
195 if (IndexReg.getReg() == X86::EIZ)
206 const MCOperand &IndexReg = MI.getOperand(Op + X86::AddrIndexReg)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86InsertPrefetch.cpp 83 Register IndexReg = MI.getOperand(Op + X86::AddrIndexReg).getReg();
87 (IndexReg == 0 ||
88 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg) ||
89 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg));
X86InstrBuilder.h 54 unsigned IndexReg;
60 : BaseType(RegBase), Scale(1), IndexReg(0), Disp(0), GV(nullptr),
77 MO.push_back(MachineOperand::CreateReg(IndexReg, false, false, false, false,
108 AM.IndexReg = Op2.getReg();
183 MIB.addImm(AM.Scale).addReg(AM.IndexReg);
X86AsmPrinter.cpp 289 const MachineOperand &IndexReg = MI->getOperand(OpNo + X86::AddrIndexReg);
299 bool HasParenPart = IndexReg.getReg() || HasBaseReg;
320 assert(IndexReg.getReg() != X86::ESP &&
327 if (IndexReg.getReg()) {
355 const MachineOperand &IndexReg = MI->getOperand(OpNo + X86::AddrIndexReg);
379 if (IndexReg.getReg()) {
392 if (DispVal || (!IndexReg.getReg() && !HasBaseReg)) {
X86FixupLEAs.cpp 385 Register IndexReg = Index.getReg();
395 if (IndexReg != 0)
396 IndexReg = TRI->getSubReg(IndexReg, X86::sub_32bit);
403 if (BaseReg != 0 && IndexReg != 0 && Disp.getImm() == 0 &&
404 (DestReg == BaseReg || DestReg == IndexReg)) {
407 std::swap(BaseReg, IndexReg);
412 .addReg(BaseReg).addReg(IndexReg)
417 .addReg(BaseReg).addReg(IndexReg);
419 } else if (DestReg == BaseReg && IndexReg == 0)
    [all...]
X86MCInstLower.cpp 1096 // IndexReg/BaseReg below need to be updated.
1112 unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg;
1113 IndexReg = Displacement = SegmentReg = 0;
1141 IndexReg = X86::RAX;
1147 IndexReg = X86::RAX;
1158 IndexReg = X86::RAX;
1164 IndexReg = X86::RAX;
1170 IndexReg = X86::RAX;
1194 .addReg(IndexReg)
X86SpeculativeLoadHardening.cpp 1344 unsigned BaseReg = 0, IndexReg = 0;
1349 IndexReg = IndexMO.getReg();
1351 if (!BaseReg && !IndexReg)
1360 (IndexReg && LoadDepRegs.test(IndexReg)))
1373 !HardenedAddrRegs.count(IndexReg)) {
1384 if (IndexReg)
1385 HardenedAddrRegs.insert(IndexReg);
X86FastISel.cpp 221 /// IndexReg field of the addressing mode will be updated to match in this case.
226 AM.IndexReg = constrainOperandRegClass(MIB->getDesc(), AM.IndexReg,
737 (AM.Base.Reg == 0 && AM.IndexReg == 0)) {
756 assert(AM.Base.Reg == 0 && AM.IndexReg == 0);
818 if (AM.IndexReg == 0) {
820 AM.IndexReg = getRegForValue(V);
821 return AM.IndexReg != 0;
905 unsigned IndexReg = AM.IndexReg;
    [all...]
X86ISelDAGToDAG.cpp 69 SDValue IndexReg;
83 : BaseType(RegBase), Base_FrameIndex(0), Scale(1), IndexReg(), Disp(0),
94 IndexReg.getNode() != nullptr || Base_Reg.getNode() != nullptr;
122 << "IndexReg ";
125 if (IndexReg.getNode())
126 IndexReg.getNode()->dump(DAG);
283 AM.IndexReg), 0);
284 AM.IndexReg = Neg;
287 if (AM.IndexReg.getNode())
288 Index = AM.IndexReg;
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/
M68kISelDAGToDAG.cpp 69 SDValue IndexReg;
83 : AM(AT), BaseType(Base::RegBase), Disp(0), BaseFrameIndex(0), IndexReg(),
103 return BaseType == Base::RegBase && IndexReg.getNode() != nullptr;
147 void setIndexReg(SDValue Reg) { IndexReg = Reg; }
159 dbgs() << ", IndexReg: ";
160 if (IndexReg.getNode()) {
161 IndexReg.getNode()->dump();
374 AM.IndexReg = N;
510 AM.IndexReg = N.getOperand(1);
738 if (!isAddressBase(AM.BaseReg) && isAddressBase(AM.IndexReg)) {
    [all...]
  /src/external/apache2/llvm/dist/llvm/include/llvm/MC/MCParser/
MCTargetAsmParser.h 44 AOK_IntelExpr // SizeDirective SymDisp [BaseReg + IndexReg * Scale + ImmDisp]
67 StringRef IndexReg;
72 : NeedBracs(false), Imm(0), BaseReg(StringRef()), IndexReg(StringRef()),
74 // [BaseReg + IndexReg * ScaleExpression + OFFSET name + ImmediateExpression]
75 IntelExpr(StringRef baseReg, StringRef indexReg, unsigned scale,
77 : NeedBracs(needBracs), Imm(imm), BaseReg(baseReg), IndexReg(indexReg),
83 bool hasIndexReg() const { return !IndexReg.empty(); }
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/AsmParser/
X86Operand.h 62 unsigned IndexReg;
136 if (Mem.IndexReg)
137 OS << ",IndexReg="
138 << X86IntelInstPrinter::getRegisterName(Mem.IndexReg);
192 return Mem.IndexReg;
325 return Mem.IndexReg >= LowR && Mem.IndexReg <= HighR;
672 Res->Mem.IndexReg = 0;
686 unsigned BaseReg, unsigned IndexReg, unsigned Scale, SMLoc StartLoc,
693 assert((SegReg || BaseReg || IndexReg || DefaultBaseReg) &
    [all...]
X86AsmParser.cpp 426 unsigned BaseReg, IndexReg, TmpReg, Scale;
450 : State(IES_INIT), PrevState(IES_ERROR), BaseReg(0), IndexReg(0),
460 unsigned getIndexReg() const { return IndexReg; }
653 // If we already have a BaseReg, then assume this is the IndexReg with
658 if (IndexReg) {
659 ErrMsg = "BaseReg/IndexReg already set!";
662 IndexReg = TmpReg;
714 // If we already have a BaseReg, then assume this is the IndexReg with
719 if (IndexReg) {
720 ErrMsg = "BaseReg/IndexReg already set!"
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCFastISel.cpp 167 unsigned &IndexReg);
421 unsigned &IndexReg) {
442 IndexReg = PPCMaterializeInt(Offset, MVT::i64);
443 assert(IndexReg && "Unexpected error in PPCMaterializeInt!");
506 unsigned IndexReg = 0;
507 PPCSimplifyAddress(Addr, UseOffset, IndexReg);
579 if (IndexReg)
580 MIB.addReg(Addr.Base.Reg).addReg(IndexReg);
655 unsigned IndexReg = 0;
656 PPCSimplifyAddress(Addr, UseOffset, IndexReg);
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/VE/AsmParser/
VEAsmParser.cpp 182 unsigned IndexReg;
364 return Mem.IndexReg;
695 Op->Mem.IndexReg = 0;
706 Op->Mem.IndexReg = 0;
717 Op->Mem.IndexReg = Index;
729 Op->Mem.IndexReg = 0;
740 Op->Mem.IndexReg = Index;
751 Op->Mem.IndexReg = 0;
1213 unsigned IndexReg = 0;
1217 if (ParseRegister(IndexReg, S, E)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZISelLowering.cpp 871 bool IndexReg;
874 LongDisplacement(LongDispl), IndexReg(IdxReg) {}
980 if (!SupportedAM.IndexReg)
7267 Register IndexReg = MI.getOperand(3).getReg();
7286 if (STOCOpcode && !IndexReg && Subtarget.hasLoadStoreOnCond()) {
7334 .addReg(IndexReg)

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