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    Searched defs:Ins (Results 1 - 25 of 38) sorted by relevancy

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  /src/external/apache2/llvm/dist/clang/tools/clang-import-test/
clang-import-test.cpp 164 auto Ins = std::make_unique<CompilerInstance>();
167 Ins->createDiagnostics(DC.release(), ShouldOwnClient);
174 CompilerInvocation::CreateFromArgs(*Inv, ClangArgv, Ins->getDiagnostics());
206 Ins->setInvocation(std::move(Inv));
209 Ins->getDiagnostics(), Ins->getInvocation().TargetOpts);
210 Ins->setTarget(TI);
211 Ins->getTarget().adjust(Ins->getLangOpts());
212 Ins->createFileManager()
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  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
FastISel.h 96 SmallVector<ISD::InputArg, 4> Ins;
195 Ins.clear();
  /src/external/apache2/llvm/dist/llvm/lib/TableGen/
TGParser.h 114 bool Ins = vars.insert(std::make_pair(std::string(Name), I)).second;
115 (void)Ins;
116 assert(Ins && "Local variable already exists");
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/
StraightLineStrengthReduce.cpp 145 : CandidateKind(CT), Base(B), Index(Idx), Stride(S), Ins(I) {}
172 Instruction *Ins = nullptr;
275 return (Basis.Ins != C.Ins && // skip the same instruction
278 Basis.Ins->getType() == C.Ins->getType() &&
280 DT->dominates(Basis.Ins->getParent(), C.Ins->getParent()) &&
308 return isGEPFoldable(cast<GetElementPtrInst>(C.Ins), TTI);
335 hasOnlyOneNonZeroIndex(cast<GetElementPtrInst>(C.Ins)));
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InductiveRangeCheckElimination.cpp 1026 Instruction *Ins = Preheader->getTerminator();
1030 Expander.expandCodeFor(FixedRightSCEV, FixedRightSCEV->getType(), Ins);
1032 Value *IndVarStartV = Expander.expandCodeFor(IndVarStart, IndVarTy, Ins);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
RDFLiveness.cpp 365 NodeList Ins = BA.Addr->members(DFG);
367 auto E = Ins.rend();
368 auto B = std::find_if(Ins.rbegin(), E,
411 Ins = BA.Addr->members(DFG);
412 B = Ins.rbegin();
413 E = Ins.rend();
862 // Add function live-ins to the live-in set of the function entry block.
894 // Remove all live-ins.
900 // Add the newly computed live-ins.
RegAllocGreedy.cpp 1253 unsigned Ins = 0;
1259 ++Ins;
1262 ++Ins;
1264 ++Ins;
1279 ++Ins;
1282 ++Ins;
1284 ++Ins;
1289 while (Ins--)
1616 unsigned Ins = 0;
1644 Ins += RegIn != (BC.Entry == SpillPlacement::PrefReg)
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  /src/external/apache2/llvm/dist/llvm/lib/Target/ARC/
ARCISelLowering.cpp 228 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
248 RetCCInfo.AnalyzeCallResult(Ins, RetCC_ARC);
432 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
439 return LowerCallArguments(Chain, CallConv, IsVarArg, Ins, dl, DAG, InVals);
447 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG,
459 CCInfo.AnalyzeFormalArguments(Ins, CC_ARC);
513 const ArgDataPair ADP = {ArgIn, Ins[i].Flags};
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMBaseRegisterInfo.cpp 651 MachineBasicBlock::iterator Ins = MBB->begin();
653 if (Ins != MBB->end())
654 DL = Ins->getDebugLoc();
663 MachineInstrBuilder MIB = BuildMI(*MBB, Ins, DL, MCID, BaseReg)
  /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/
BPFISelLowering.cpp 301 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
317 CCInfo.AnalyzeFormalArguments(Ins, getHasAlu32() ? CC_BPF32 : CC_BPF64);
373 auto &Ins = CLI.Ins;
495 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, CLI.DL, DAG,
549 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
557 if (Ins.size() >= 2) {
559 for (unsigned i = 0, e = Ins.size(); i != e; ++i)
560 InVals.push_back(DAG.getConstant(0, DL, Ins[i].VT));
561 return DAG.getCopyFromReg(Chain, DL, 1, Ins[0].VT, InFlag).getValue(1)
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  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsCallLowering.cpp 446 SmallVector<ISD::InputArg, 8> Ins;
447 subTargetRegTypeForCallingConv(F, ArgInfos, OrigArgIndices, Ins);
458 CCInfo.AnalyzeFormalArguments(Ins, TLI.CCAssignFnForCall());
459 setLocInfo(ArgLocs, Ins);
616 SmallVector<ISD::InputArg, 8> Ins;
617 subTargetRegTypeForCallingConv(F, ArgInfos, OrigRetIndices, Ins);
623 CCInfo.AnalyzeCallResult(Ins, TLI.CCAssignFnForReturn(), Info.OrigRet.Ty,
625 setLocInfo(ArgLocs, Ins);
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCRegisterInfo.cpp 883 MachineBasicBlock::reverse_iterator Ins = MI;
885 ++Ins;
888 for (; Ins != Rend; ++Ins) {
890 if (Ins->modifiesRegister(SrcReg, TRI))
893 if (Ins->readsRegister(SrcReg, TRI))
897 Ins = MI;
901 if (!Ins->isDebugInstr())
906 if (Ins == MBB.rend())
907 Ins = MI
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  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/MCTargetDesc/
AArch64InstPrinter.cpp 786 std::string Ins;
809 case 4: Ins = "cfp\t"; break;
810 case 5: Ins = "dvp\t"; break;
811 case 7: Ins = "cpp\t"; break;
824 Ins = "ic\t";
836 Ins = "dc\t";
847 Ins = "at\t";
859 Ins = "tlbi\t";
865 std::string Str = Ins + Name;
  /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/
LanaiISelLowering.cpp 398 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
403 return LowerCCCArguments(Chain, CallConv, IsVarArg, Ins, DL, DAG, InVals);
415 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
429 OutVals, Ins, DL, DAG, InVals);
439 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
451 CCInfo.AnalyzeFormalArguments(Ins, CC_Lanai32_Fast);
453 CCInfo.AnalyzeFormalArguments(Ins, CC_Lanai32);
600 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
768 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG
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  /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/
MSP430ISelLowering.cpp 446 const SmallVectorImpl<ISD::InputArg> &Ins) {
447 State.AnalyzeFormalArguments(Ins, CC_MSP430_AssignStack);
550 const SmallVectorImpl<ISD::InputArg> &Ins) {
551 State.AnalyzeCallResult(Ins, RetCC_MSP430);
568 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
576 return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals);
578 if (Ins.empty())
591 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
608 Outs, OutVals, Ins, dl, DAG, InVals)
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  /src/external/apache2/llvm/dist/llvm/lib/Transforms/IPO/
PartialInlining.cpp 1097 Instruction *Ins = &ClonedOI->ReturnBlock->front();
1105 PHINode::Create(OldPhi->getType(), NumPredsFromEntries + 1, "", Ins);
1107 Ins = ClonedOI->ReturnBlock->getFirstNonPHI();
  /src/external/apache2/llvm/dist/llvm/utils/TableGen/
CodeGenRegisters.h 112 std::pair<CompMap::iterator, bool> Ins =
123 return (Ins.second || Ins.first->second == B) ? nullptr
124 : Ins.first->second;
CodeGenRegisters.cpp 368 DenseMap<const CodeGenRegister*, CodeGenSubRegIndex*>::iterator Ins =
370 if (Ins->second == SubReg.first)
378 SubReg.first->getName() + " and " + Ins->second->getName());
  /src/external/apache2/llvm/dist/llvm/include/llvm/TableGen/
Record.h 1829 bool Ins = Classes.insert(std::make_pair(std::string(R->getName()),
1831 (void)Ins;
1832 assert(Ins && "Class already exists");
1836 bool Ins = Defs.insert(std::make_pair(std::string(R->getName()),
1838 (void)Ins;
1839 assert(Ins && "Record already exists");
1843 bool Ins = ExtraGlobals.insert(std::make_pair(std::string(Name), I)).second;
1844 (void)Ins;
1846 assert(Ins && "Global already exists");
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIRegisterInfo.cpp 672 MachineBasicBlock::iterator Ins = MBB->begin();
675 if (Ins != MBB->end())
676 DL = Ins->getDebugLoc();
689 BuildMI(*MBB, Ins, DL, TII->get(MovOpc), BaseReg)
700 BuildMI(*MBB, Ins, DL, TII->get(AMDGPU::S_MOV_B32), OffsetReg)
702 BuildMI(*MBB, Ins, DL, TII->get(MovOpc), FIReg)
706 BuildMI(*MBB, Ins, DL, TII->get(AMDGPU::S_ADD_U32), BaseReg)
712 TII->getAddNoCarry(*MBB, Ins, DL, BaseReg)
  /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
AVRISelLowering.cpp 1126 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1139 CCInfo.AnalyzeFormalArguments(Ins, ArgCC_AVR_Vararg);
1141 analyzeArguments(nullptr, &MF.getFunction(), &DL, Ins, ArgLocs, CCInfo);
1229 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1379 if (!Ins.empty()) {
1385 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, DL, DAG,
1394 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG,
1404 CCInfo.AnalyzeCallResult(Ins, RetCC_AVR_BUILTIN);
1406 analyzeReturnValues(Ins, CCInfo)
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  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonCommonGEP.cpp 563 std::pair<NodeSymRel::iterator, bool> Ins = EqRel.insert(C);
564 (void)Ins;
565 assert(Ins.second && "Cannot add a class");
594 std::pair<ProjMap::iterator,bool> Ins = PM.insert(std::make_pair(&S, Min));
595 (void)Ins;
596 assert(Ins.second && "Cannot add minimal element");
1251 ValueVect Ins;
1253 Ins.push_back(&*I);
1254 for (ValueVect::iterator I = Ins.begin(), E = Ins.end(); I != E; ++I)
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HexagonISelLowering.cpp 348 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
358 CCInfo.AnalyzeCallResult(Ins, RetCC_Hexagon_HVX);
360 CCInfo.AnalyzeCallResult(Ins, RetCC_Hexagon);
406 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
441 OutVals, Ins, DAG);
623 return LowerCallResult(Chain, Glue, CallConv, IsVarArg, Ins, dl, DAG,
778 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
794 CCInfo.AnalyzeFormalArguments(Ins, CC_Hexagon_HVX);
796 CCInfo.AnalyzeFormalArguments(Ins, CC_Hexagon_Legacy)
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  /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
WebAssemblyISelLowering.cpp 892 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1042 for (const auto &In : Ins) {
1067 for (size_t I = 0; I < Ins.size(); ++I)
1071 return Res.getValue(Ins.size());
1114 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
1128 for (const ISD::InputArg &In : Ins) {
1173 DAG.getTargetConstant(Ins.size(), DL, MVT::i32)));
  /src/external/apache2/llvm/dist/llvm/lib/Target/XCore/
XCoreISelLowering.cpp 1036 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1054 Outs, OutVals, Ins, dl, DAG, InVals);
1110 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1129 RetCCInfo.AnalyzeCallResult(Ins, RetCC_XCore);
1242 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1251 Ins, dl, DAG, InVals);
1261 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1273 CCInfo.AnalyzeFormalArguments(Ins, CC_XCore);
1338 const ArgDataPair ADP = { ArgIn, Ins[i].Flags }
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