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    Searched defs:Instruction (Results 1 - 16 of 16) sorted by relevancy

  /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r600/sfn/
sfn_instruction_base.cpp 94 Instruction::Instruction(instr_type t):
99 Instruction::~Instruction()
103 void Instruction::print(std::ostream& os) const
110 void Instruction::remap_registers(ValueRemapper& map)
127 void Instruction::add_remappable_src_value(PValue *v)
133 void Instruction::add_remappable_src_value(GPRVector *v)
138 void Instruction::add_remappable_dst_value(PValue *v)
144 void Instruction::add_remappable_dst_value(GPRVector *v
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sfn_instruction_base.h 69 class Instruction {
99 typedef std::shared_ptr<Instruction> Pointer;
101 friend bool operator == (const Instruction& lhs, const Instruction& rhs);
103 Instruction(instr_type t);
105 virtual ~Instruction();
131 virtual bool is_equal_to(const Instruction& lhs) const = 0;
143 using PInstruction=Instruction::Pointer;
145 inline std::ostream& operator << (std::ostream& os, const Instruction& instr)
151 bool operator == (const Instruction& lhs, const Instruction& rhs)
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  /xsrc/external/mit/MesaLib/dist/src/panfrost/bifrost/valhall/
valhall.py 99 # Model a single instruction
171 class Instruction:
239 # Build a single instruction from XML and group based overrides
270 instr = Instruction(name, opcode, opcode2, srcs = sources, dests = dests, immediates = imms, modifiers = modifiers, staging = staging)
275 # overrides for each distinct instruction
  /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/nouveau/codegen/
nv50_ir.cpp 100 Instruction *insn = src->value->getUniqueInsn();
172 if (!insn || !insn->bb) // Unbound instruction ?
179 Instruction *insn = (*it)->getInsn();
275 Instruction *insn = getInsn();
562 void Instruction::init()
597 Instruction::Instruction()
607 Instruction::Instruction(Function *fn, operation opr, DataType ty)
617 Instruction::~Instruction(
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nv50_ir_from_tgsi.cpp 44 class Instruction
47 Instruction(const struct tgsi_full_instruction *inst) : insn(inst) { }
184 inline uint getOpcode() const { return insn->Instruction.Opcode; }
186 unsigned int srcCount() const { return insn->Instruction.NumSrcRegs; }
187 unsigned int dstCount() const { return insn->Instruction.NumDstRegs; }
234 if (!insn->Instruction.Memory)
241 unsigned getSaturate() const { return insn->Instruction.Saturate; }
252 unsigned int Instruction::texOffsetMask() const
255 assert(insn->Instruction.Texture);
281 unsigned int Instruction::srcMask(unsigned int s) cons
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nv50_ir.h 180 // various instruction-specific modifier definitions Instruction::subOp
304 // if the instruction's sType is signed, sign extend the operand from 16 bits
566 class Instruction;
580 uint8_t size; // this should match the Instruction type's size
668 inline Instruction *getInsn() const { return insn; }
669 inline void setInsn(Instruction *inst) { insn = inst; }
688 Instruction *insn;
706 inline Instruction *getInsn() const { return insn; }
707 inline void setInsn(Instruction *inst) { insn = inst;
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  /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/nouveau/codegen/
nv50_ir.cpp 101 Instruction *insn = src->value->getUniqueInsn();
173 if (!insn || !insn->bb) // Unbound instruction ?
180 Instruction *insn = (*it)->getInsn();
276 Instruction *insn = getInsn();
561 void Instruction::init()
592 Instruction::Instruction()
603 Instruction::Instruction(Function *fn, operation opr, DataType ty)
613 Instruction::~Instruction(
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nv50_ir_from_tgsi.cpp 45 class Instruction
48 Instruction(const struct tgsi_full_instruction *inst) : insn(inst) { }
185 inline uint getOpcode() const { return insn->Instruction.Opcode; }
187 unsigned int srcCount() const { return insn->Instruction.NumSrcRegs; }
188 unsigned int dstCount() const { return insn->Instruction.NumDstRegs; }
236 if (!insn->Instruction.Memory)
243 unsigned getSaturate() const { return insn->Instruction.Saturate; }
254 unsigned int Instruction::texOffsetMask() const
257 assert(insn->Instruction.Texture);
283 unsigned int Instruction::srcMask(unsigned int s) cons
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nv50_ir.h 173 // various instruction-specific modifier definitions Instruction::subOp
279 // if the instruction's sType is signed, sign extend the operand from 16 bits
515 class Instruction;
529 uint8_t size; // this should match the Instruction type's size
616 inline Instruction *getInsn() const { return insn; }
617 inline void setInsn(Instruction *inst) { insn = inst; }
636 Instruction *insn;
654 inline Instruction *getInsn() const { return insn; }
655 inline void setInsn(Instruction *inst) { insn = inst;
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  /xsrc/external/mit/MesaLib/dist/src/gallium/auxiliary/tgsi/
tgsi_parse.h 90 struct tgsi_instruction Instruction;
  /xsrc/external/mit/MesaLib.old/dist/src/gallium/auxiliary/tgsi/
tgsi_parse.h 90 struct tgsi_instruction Instruction;
  /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/i915/
i915_fpc.h 262 struct tgsi_instruction Instruction;
  /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/i915/
i915_fpc.h 297 struct tgsi_instruction Instruction;
  /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r300/compiler/
radeon_pair_schedule.c 45 struct rc_instruction * Instruction;
47 /** Next instruction in the linked list of ready instructions. */
50 /** Values that this instruction reads and writes */
58 * this instruction can be scheduled.
63 * "all readers"), even those outside the basic block this instruction
67 /** If the scheduler has paired an RGB and an Alpha instruction together,
68 * PairedInst references the alpha instruction's dependency information.
73 * instruction to schedule. Instructions with a higher value of Score
77 /** The number of components that read from a TEX instruction. */
111 * of the instruction writing \ref Next is decremented
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  /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r300/compiler/
radeon_pair_schedule.c 45 struct rc_instruction * Instruction;
47 /** Next instruction in the linked list of ready instructions. */
50 /** Values that this instruction reads and writes */
58 * this instruction can be scheduled.
63 * "all readers"), even those outside the basic block this instruction
67 /** If the scheduler has paired an RGB and an Alpha instruction together,
73 * instruction to schedule. Instructions with a higher value of Score
77 /** The number of components that read from a TEX instruction. */
111 * of the instruction writing \ref Next is decremented.
190 fprintf(stderr,"%u (%d) [%u],", ptr->Instruction->IP, score
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  /xsrc/external/mit/MesaLib/dist/src/amd/compiler/
aco_ir.h 60 * Representation of the instruction's microcode encoding format
62 * - VOP2* | VOP3 represents a VOP2 instruction in VOP3 encoding
63 * - VOP2* | DPP represents a VOP2 instruction with data parallel primitive.
64 * - VOP2* | SDWA represents a VOP2 instruction with sub-dword addressing.
69 /* Pseudo Instruction Format */
165 /* this is a atomic instruction (may only read or write memory) */
167 /* this is instruction both reads and writes memory */
483 * Constant values are inlined into the instruction sequence.
803 * instruction's definitions. Unlike isKill() and isFirstKill(), this is
976 struct Instruction;
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