| /src/external/apache2/llvm/dist/llvm/include/llvm/MCA/Stages/ |
| EntryStage.h | 11 /// purpose in life is to pick instructions in sequence and move them to the
28 SmallVector<std::unique_ptr<Instruction>, 16> Instructions;
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| /src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/ |
| CodeTemplate.h | 10 /// A set of structures and functions to craft instructions for the
130 // The list of the instructions for this template.
131 std::vector<InstructionTemplate> Instructions;
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| MCInstrDescView.h | 94 /// A cache of BitVector to reuse between Instructions.
96 /// For X86, this is ~160 unique vectors for all of the ~15K Instructions.
114 // Prevent copy or move, instructions are allocated once and cached.
173 // Instructions are expensive to instantiate. This class provides a cache of
174 // Instructions with lazy construction.
186 Instructions;
230 // This is not assembly but the internal LLVM's name for instructions and
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| BenchmarkResult.h | 37 std::vector<MCInst> Instructions;
67 const MCInst &keyInstruction() const { return Key.Instructions[0]; }
68 // The number of instructions inside the repeated snippet. For example, if a
69 // snippet of 3 instructions is repeated 4 times, this is 12.
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| BenchmarkRunner.cpp | 147 const std::vector<MCInst> &Instructions = BC.Key.Instructions;
168 // Assemble at least kMinInstructionsForSnippet instructions by repeating
170 // understands that the inside instructions are repeated.
178 Repetitor->Repeat(Instructions, kMinInstructionsForSnippet),
188 // Assemble NumRepetitions instructions repetitions of the snippet for
191 Repetitor->Repeat(Instructions, InstrBenchmark.NumRepetitions);
228 BM.PerSnippetValue *= static_cast<double>(Instructions.size()) /
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| /src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/Mips/ |
| Target.cpp | 71 // Generates instructions to load an immediate value into a register.
95 std::vector<MCInst> Instructions;
101 Instructions.push_back(
106 Instructions.push_back(
112 Instructions.push_back(
120 Instructions.push_back(
127 return Instructions;
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| /src/external/apache2/llvm/dist/llvm/tools/llvm-mca/ |
| CodeRegion.h | 51 /// It identifies a sequence of machine instructions.
55 // Instructions that form this region.
56 llvm::SmallVector<llvm::MCInst, 8> Instructions;
69 Instructions.emplace_back(Instruction);
76 bool empty() const { return Instructions.empty(); }
79 llvm::ArrayRef<llvm::MCInst> getInstructions() const { return Instructions; }
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| /src/external/apache2/llvm/dist/llvm/tools/llvm-mca/Views/ |
| SummaryView.h | 17 /// Instructions: 900
24 /// performance indicators are 'Total Cycles' and IPC (Instructions Per Cycle).
46 // The total number of micro opcodes contributed by a block of instructions.
50 unsigned Instructions;
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| /src/external/apache2/llvm/dist/llvm/include/llvm/Analysis/ |
| StackLifetime.h | 31 /// Live ranges are represented as sets of "interesting" instructions, which are
32 /// defined as instructions that may start or end an alloca's lifetime. These
36 /// Interesting instructions are numbered in the depth-first walk of the CFG,
62 /// This class represents a set of interesting instructions where an alloca is
97 /// Interesting instructions. Instructions of the same block are adjustent
99 SmallVector<const IntrinsicInst *, 64> Instructions;
102 /// Instructions inside each BB have monotonic and consecutive ids.
147 return make_filter_range(Instructions, NotNull);
150 /// Returns a set of "interesting" instructions where the given alloca i
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/MC/ |
| MCWinEH.h | 31 // Check whether two instructions refer to the same operation
56 std::vector<Instruction> Instructions;
68 if (!Instructions.empty())
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| MCDwarf.h | 180 /// unit where machine instructions have been assembled after seeing .loc
546 /// was at the beginning of the function, after all initial instructions added
626 std::vector<MCCFIInstruction> Instructions;
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| /src/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| CodeGenTarget.h | 52 std::unique_ptr<CodeGenInstruction>> Instructions;
147 if (Instructions.empty()) ReadInstructions();
148 return Instructions;
153 if (Instructions.empty()) ReadInstructions();
154 auto I = Instructions.find(InstRec);
155 assert(I != Instructions.end() && "Not an instruction");
159 /// Returns the number of predefined instructions.
162 /// Returns the number of pseudo instructions.
169 /// Return all of the instructions defined by the target, ordered by their
171 /// The following order of instructions is also guaranteed
[all...] |
| AsmWriterEmitter.cpp | 61 std::vector<AsmWriterInst> Instructions;
108 /// instructions that are suitably similar to it.
122 // If this differs in the same operand as the rest of the instructions in
138 // If the operand is the same for all instructions, just print it.
141 // If this is the operand that varies between all of the instructions,
171 // instructions each case are used for. It is a comma separated string of
177 for (size_t i = 0, e = Instructions.size(); i != e; ++i) {
178 const AsmWriterInst &Inst = Instructions[i];
203 // For each entry of UniqueOperandCommands, there is a set of instructions
204 // that uses it. If the next command of all instructions in the set ar
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| MIRCanonicalizerPass.cpp | 20 // Reorders instructions canonically.
94 rescheduleLexographically(std::vector<MachineInstr *> instructions,
102 for (auto *II : instructions) {
150 // Pre-Populate vector of instructions to reschedule so that we don't
152 std::vector<MachineInstr *> Instructions;
154 Instructions.push_back(&MI);
162 for (auto *II : Instructions) {
178 for (auto *II : Instructions) {
284 dbgs() << "Rescheduling Multi-Use Instructions Lexographically.";);
292 dbgs() << "Rescheduling Idempotent Instructions Lexographically.";)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/MCTargetDesc/ |
| X86WinCOFFTargetStreamer.cpp | 63 SmallVector<FPOInstruction, 5> Instructions;
186 // Complain if there were prologue setup instructions but no end prologue.
187 if (!CurFPOData->Instructions.empty()) {
189 CurFPOData->Instructions.clear();
210 CurFPOData->Instructions.push_back(Inst);
221 CurFPOData->Instructions.push_back(Inst);
232 CurFPOData->Instructions.push_back(Inst);
239 if (!llvm::any_of(CurFPOData->Instructions, [](const FPOInstruction &Inst) {
250 CurFPOData->Instructions.push_back(Inst);
414 for (const FPOInstruction &Inst : FPO->Instructions) {
[all...] |
| /src/external/apache2/llvm/dist/llvm/tools/llvm-cfi-verify/lib/ |
| FileAnalysis.h | 74 // sequential control flows, including indirect control flow instructions.
118 // Undefined (and bad) instructions cannot fall through, and instruction that
141 // Returns the list of indirect instructions.
221 std::map<uint64_t, Instr> Instructions;
223 // Contains a mapping between a specific address, and a list of instructions
224 // that use this address as a branch target (including call instructions).
227 // A list of addresses of indirect control flow instructions.
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| /src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/X86/ |
| Target.cpp | 218 // We do not handle instructions with OPERAND_PCREL.
223 // We do not handle second-form X87 instructions. We only handle first-form
295 CT.Instructions.push_back(std::move(IT));
359 // These are instructions like
414 // These are instructions like
517 Instructions.push_back(Inst);
526 std::vector<MCInst> Instructions;
537 return std::move(Instructions);
552 return std::move(Instructions);
566 return std::move(Instructions);
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/Disassembler/ |
| HexagonDisassembler.cpp | 473 auto Instructions = HexagonMCInstrInfo::bundleInstructions(**CurrentBundle);
474 auto i = Instructions.end() - 1;
475 for (auto n = Instructions.begin() - 1;; --i, ++Offset) {
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| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsInstructionSelector.cpp | 236 assert(STI.hasMSA() && "Vector instructions require target with MSA.");
755 SmallVector<struct Instr, 2> Instructions;
765 Instructions.emplace_back(Mips::XOR, Temp, LHS, RHS);
766 Instructions.emplace_back(Mips::SLTiu, ICMPReg, Temp, 1);
769 Instructions.emplace_back(Mips::XOR, Temp, LHS, RHS);
770 Instructions.emplace_back(Mips::SLTu, ICMPReg, Mips::ZERO, Temp);
773 Instructions.emplace_back(Mips::SLTu, ICMPReg, RHS, LHS);
776 Instructions.emplace_back(Mips::SLTu, Temp, LHS, RHS);
777 Instructions.emplace_back(Mips::XORi, ICMPReg, Temp, 1);
780 Instructions.emplace_back(Mips::SLTu, ICMPReg, LHS, RHS)
[all...] |
| /src/external/apache2/llvm/dist/llvm/tools/bugpoint/ |
| CrashDebugger.cpp | 24 #include "llvm/IR/Instructions.h"
746 /// non-terminator instructions and replacing them with undef.
776 SmallPtrSet<Instruction *, 32> Instructions;
779 Instructions.insert(cast<Instruction>(VMap[Insts[i]]));
782 outs() << "Checking for crash with only " << Instructions.size();
783 if (Instructions.size() == 1)
786 outs() << " instructions: ";
792 if (!Instructions.count(Inst) && !Inst->isTerminator() &&
813 for (Instruction *Inst : Instructions)
823 /// the specified instructions
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/AsmParser/ |
| SparcAsmParser.cpp | 1 //===-- SparcAsmParser.cpp - Parse Sparc assembly to MCInst instructions --===//
113 SmallVectorImpl<MCInst> &Instructions);
558 SmallVectorImpl<MCInst> &Instructions) {
600 Instructions.push_back(TmpInst);
605 // * A non-immediate value will always require both instructions.
626 Instructions.push_back(TmpInst);
637 SmallVector<MCInst, 8> Instructions;
645 Instructions.push_back(Inst);
648 if (expandSET(Inst, IDLoc, Instructions))
653 for (const MCInst &I : Instructions) {
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/AsmParser/ |
| WebAssemblyAsmParser.cpp | 202 // Order of labels, directives and instructions in a .s file have no
212 Instructions,
518 // WebAssembly has instructions with / in them, which AsmLexer parses
594 // These instructions have differing operand orders in the text format vs
595 // the binary formats. The MC instructions follow the binary format, so
961 // be encoded as a prelude to the instructions, so emit an empty list of
1003 CurrentState = Instructions;
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| /src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/ |
| LoopDistribute.cpp | 52 #include "llvm/IR/Instructions.h"
125 /// Maintains the set of instructions of the loop for a partition before
158 /// instructions that the seeded instructions dependent on.
167 // instructions that the originally seeded instructions depend on.
171 // Insert instructions from the loop that we depend on.
205 /// remapinstruction to remap the cloned instructions.
208 /// Remaps the cloned instructions using VMap.
213 /// Based on the set of instructions selected for this partition
[all...] |
| LoopRerollPass.cpp | 38 #include "llvm/IR/Instructions.h"
98 // of isomorphic DAGs of instructions, with each DAG rooted at some increment
117 // where each f(i) is a set of instructions that, collectively, are a function
160 /// instructions that belong to all iterations.
207 // A chain of isomorphic instructions, identified by a single-use PHI
211 SimpleLoopReduction(Instruction *P, Loop *L) : Instructions(1, P) {
222 return Instructions.front();
227 return Instructions.back();
232 return Instructions[i+1];
240 return Instructions.size()-1
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/MC/ |
| MCDwarf.cpp | 1472 /// Emit frame instructions to describe the layout of the frame.
1680 // Initial Instructions
1684 const std::vector<MCCFIInstruction> &Instructions =
1686 emitCFIInstructions(Instructions, nullptr);
1762 // Call Frame Instructions
1763 emitCFIInstructions(frame.Instructions, frame.Begin);
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