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    Searched defs:IsWave32 (Results 1 - 4 of 4) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SILowerI1Copies.cpp 47 bool IsWave32 = false;
420 return MRI.createVirtualRegister(ST.isWave32() ? &AMDGPU::SReg_32RegClass
456 IsWave32 = ST->isWave32();
458 if (IsWave32) {
565 MRI->setRegClass(DstReg, IsWave32 ? &AMDGPU::SReg_32RegClass
686 MRI->setRegClass(DstReg, IsWave32 ? &AMDGPU::SReg_32RegClass
SIPreEmitPeephole.cpp 80 const bool IsWave32 = ST.isWave32();
82 const unsigned ExecReg = IsWave32 ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
83 const unsigned And = IsWave32 ? AMDGPU::S_AND_B32 : AMDGPU::S_AND_B64;
84 const unsigned AndN2 = IsWave32 ? AMDGPU::S_ANDN2_B32 : AMDGPU::S_ANDN2_B64;
85 const unsigned Mov = IsWave32 ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64;
SILowerControlFlow.cpp 637 bool IsWave32 = ST.isWave32();
642 TII->get(IsWave32 ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64), Exec)
687 TII->get(IsWave32 ? AMDGPU::S_BFM_B32 : AMDGPU::S_BFM_B64), Exec)
695 TII->get(IsWave32 ? AMDGPU::S_CMOV_B32 : AMDGPU::S_CMOV_B64),
782 if (ST.isWave32()) {
SIRegisterInfo.cpp 105 bool IsWave32;
111 bool IsWave32, MachineBasicBlock::iterator MI, int Index,
117 IsWave32(IsWave32) {
122 if (IsWave32) {
139 Data.PerVGPR = IsWave32 ? 32 : 64;
183 IsWave32 ? AMDGPU::SGPR_32RegClass : AMDGPU::SGPR_64RegClass;
275 SpillSGPRToVGPR(EnableSpillSGPRToVGPR), isWave32(ST.isWave32()) {
492 if (isWave32) {
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