1 /* $NetBSD: kirkwoodreg.h,v 1.7 2022/10/31 20:30:22 andvar Exp $ */ 2 /* 3 * Copyright (c) 2007, 2008 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #ifndef _KIRKWOODREG_H_ 29 #define _KIRKWOODREG_H_ 30 31 #include <arm/marvell/mvsocreg.h> 32 #include <dev/marvell/mvgbereg.h> 33 34 /* 35 * MHz TCLK GbE SATA TDMI Audio MTS GPIO TSens TWSI 36 * 6180: 600/800, 166, x1, -, -, o, -, 30, -, x1 37 * 6190: 600, 166, *x2, x1, -, -, -, 36, -, x1 38 * 6192: 800, 166, x2, x2, o, o, o, 36, -, x1 39 * 6281: 1.0/1.2/1.5, 200, x2, x2, o, o, o, 50, -, x1 40 * 6282: ?-2.0, 200, x2, x2, o, o, o, 50, o, x2 41 * 42 * * GbE x1 + 100BT x1 43 */ 44 45 #define KIRKWOOD_UNITID_DDR MVSOC_UNITID_DDR 46 #define KIRKWOOD_UNITID_DEVBUS MVSOC_UNITID_DEVBUS 47 #define KIRKWOOD_UNITID_MLMB MVSOC_UNITID_MLMB 48 #define KIRKWOOD_UNITID_CRYPT 0x3 /* Cryptographic Engine reg */ 49 #define KIRKWOOD_UNITID_SA 0x3 /* Security Accelerator reg */ 50 #define KIRKWOOD_UNITID_PEX MVSOC_UNITID_PEX 51 #define KIRKWOOD_UNITID_USB 0x5 /* USB registers */ 52 #define KIRKWOOD_UNITID_IDMA 0x6 /* IDMA registers */ 53 #define KIRKWOOD_UNITID_XOR 0x6 /* XOR registers */ 54 #define KIRKWOOD_UNITID_GBE 0x7 /* Gigabit Ethernet registers */ 55 #define KIRKWOOD_UNITID_SATA 0x8 /* SATA registers */ 56 #define KIRKWOOD_UNITID_SDIO 0x9 /* SDIO registers */ 57 #define KIRKWOOD_UNITID_AUDIO 0xa /* Audio registers */ 58 #define KIRKWOOD_UNITID_MTS 0xb /* MPEG Transport Stream reg */ 59 #define KIRKWOOD_UNITID_TDM 0xd /* TDM registers */ 60 61 #define KIRKWOOD_ATTR_NAND 0x2f 62 #define KIRKWOOD_ATTR_SPI 0x1e 63 #define KIRKWOOD_ATTR_BOOTROM 0x1d 64 #define KIRKWOOD_ATTR_PEX_MEM 0xe8 65 #define KIRKWOOD_ATTR_PEX_IO 0xe0 66 #define KIRKWOOD_ATTR_PEX1_MEM 0xd8 67 #define KIRKWOOD_ATTR_PEX1_IO 0xd0 68 #define KIRKWOOD_ATTR_CRYPT 0x00 69 70 #define KIRKWOOD_IRQ_HIGH 0 /* High interrupt */ 71 #define KIRKWOOD_IRQ_BRIDGE 1 /* Mbus-L to Mbus Bridge */ 72 #define KIRKWOOD_IRQ_H2CPUDB 2 /* Doorbell interrupt */ 73 #define KIRKWOOD_IRQ_CPU2HDB 3 /* Doorbell interrupt */ 74 #define KIRKWOOD_IRQ_XOR0CHAN0 5 /* Xor 0 Channel0 */ 75 #define KIRKWOOD_IRQ_XOR0CHAN1 6 /* Xor 0 Channel1 */ 76 #define KIRKWOOD_IRQ_XOR1CHAN0 7 /* Xor 1 Channel0 */ 77 #define KIRKWOOD_IRQ_XOR1CHAN1 8 /* Xor 1 Channel1 */ 78 #define KIRKWOOD_IRQ_PEX0INT 9 /* PCI Express port0 INT A-D */ 79 #define KIRKWOOD_IRQ_PEX1INT 10 /* PCI Express port1 INT A-D */ 80 #define KIRKWOOD_IRQ_GBE0SUM 11 /* GbE0 summary */ 81 #define KIRKWOOD_IRQ_GBE0RX 12 /* GbE0 receive interrupt */ 82 #define KIRKWOOD_IRQ_GBE0TX 13 /* GbE0 transmit interrupt */ 83 #define KIRKWOOD_IRQ_GBE0MISC 14 /* GbE0 miscellaneous intr */ 84 #define KIRKWOOD_IRQ_GBE1SUM 15 /* GbE1 summary */ 85 #define KIRKWOOD_IRQ_GBE1RX 16 /* GbE1 receive interrupt */ 86 #define KIRKWOOD_IRQ_GBE1TX 17 /* GbE1 transmit interrupt */ 87 #define KIRKWOOD_IRQ_GBE1MISC 18 /* GbE1 miscellaneous intr */ 88 #define KIRKWOOD_IRQ_USB0CNT 19 /* USB0 controller interrupt */ 89 #define KIRKWOOD_IRQ_SATA 21 /*Sata ports interrupt summary*/ 90 #define KIRKWOOD_IRQ_SECURITYINT 22 /* Security engine completion */ 91 #define KIRKWOOD_IRQ_SPIINT 23 /* SPI Interrupt */ 92 #define KIRKWOOD_IRQ_AUDIOINT 24 /* Audio interrupt */ 93 #define KIRKWOOD_IRQ_TS0INT 26 /* TS0 Interrupt */ 94 #define KIRKWOOD_IRQ_SDIOINT 28 /* SDIO Interrupt */ 95 #define KIRKWOOD_IRQ_TWSI 29 /* TWSI interrupt */ 96 #define KIRKWOOD_IRQ_AVBINT 30 /* AVB Interrupt */ 97 #define KIRKWOOD_IRQ_TDMINT 31 /* TDM Interrupt */ 98 #define KIRKWOOD_IRQ_TWSI1 32 /* TWSI1 interrupt */ 99 #define KIRKWOOD_IRQ_UART0INT 33 /* UART0 */ 100 #define KIRKWOOD_IRQ_UART1INT 34 /* UART1 */ 101 #define KIRKWOOD_IRQ_GPIOLO7_0 35 /* GPIO Low[7:0] */ 102 #define KIRKWOOD_IRQ_GPIOLO8_15 36 /* GPIO Low[15:8] */ 103 #define KIRKWOOD_IRQ_GPIOLO16_23 37 /* GPIO Low[23:16] */ 104 #define KIRKWOOD_IRQ_GPIOLO24_31 38 /* GPIO Low[31:24] */ 105 #define KIRKWOOD_IRQ_GPIOHI7_0 39 /* GPIO High[7:0] */ 106 #define KIRKWOOD_IRQ_GPIOHI8_15 40 /* GPIO High[15:8] */ 107 #define KIRKWOOD_IRQ_GPIOHI16_23 41 /* GPIO High[23:16] */ 108 #define KIRKWOOD_IRQ_XOR0ERR 42 /* XOR0 error */ 109 #define KIRKWOOD_IRQ_XOR1ERR 43 /* XOR1 error */ 110 #define KIRKWOOD_IRQ_PEX0ERR 44 /* PCI Express0 error */ 111 #define KIRKWOOD_IRQ_PEX1ERR 45 /* PCI Express1 error */ 112 #define KIRKWOOD_IRQ_GBE0ERR 46 /* GbE port0 error */ 113 #define KIRKWOOD_IRQ_GBE1ERR 47 /* GbE port1 error */ 114 #define KIRKWOOD_IRQ_USBERR 48 /* USB error */ 115 #define KIRKWOOD_IRQ_SECURITYERR 49 /* Cryptographic engine error */ 116 #define KIRKWOOD_IRQ_AUDIOERR 50 /* Audio error */ 117 #define KIRKWOOD_IRQ_RTCINT 53 /* Real time clock interrupt */ 118 119 120 /* 121 * Physical address of integrated peripherals 122 */ 123 124 #define KIRKWOOD_UNITID2PHYS(uid) ((KIRKWOOD_UNITID_ ## uid) << 16) 125 126 /* 127 * Pin Multiplexing Interface Registers 128 */ 129 #define KIRKWOOD_MPP_BASE (MVSOC_DEVBUS_BASE + 0x0000) 130 #define KIRKWOOD_MPP_MPPC0R 0x00 131 #define KIRKWOOD_MPP_MPPC1R 0x04 132 #define KIRKWOOD_MPP_MPPC2R 0x08 133 #define KIRKWOOD_MPP_MPPC3R 0x0c 134 #define KIRKWOOD_MPP_MPPC4R 0x10 135 #define KIRKWOOD_MPP_MPPC5R 0x14 136 #define KIRKWOOD_MPP_MPPC6R 0x18 137 #define KIRKWOOD_MPP_SAMPLE_AT_RESET 0x30 138 139 /* 140 * Miscellaneous Registers 141 */ 142 #define KIRKWOOD_MISC_BASE (MVSOC_DEVBUS_BASE + 0x0000) 143 #define KIRKWOOD_MISC_DEVICEID 0x34 144 #define KIRKWOOD_MISC_CLOCKCONTROL 0x4c 145 #define KIRKWOOD_MISC_SYSRSTLC 0x50 /* SYSRSTn Length Counter */ 146 #define KIRKWOOD_MISC_AGC 0x7c /* Analog Group Configuration */ 147 #define KIRKWOOD_MISC_SSCGC 0xd8 /* SSCG Configuration */ 148 #define KIRKWOOD_MISC_PTPCC 0xdc /* PTP Clock Configuration */ 149 #define KIRKWOOD_MISC_IOC0 0xe0 /* IO Configuration 0 */ 150 151 /* 152 * Real-Time Clock Unit Registers 153 */ 154 #define KIRKWOOD_RTC_BASE (MVSOC_DEVBUS_BASE + 0x0300) 155 156 /* 157 * Serial Peripheral Interface Registers 158 */ 159 #define KIRKWOOD_SPI_BASE (MVSOC_DEVBUS_BASE + 0x0600) 160 161 /* 162 * Mbus-L to Mbus Bridge Registers 163 */ 164 /* CPU Address Map Registers */ 165 #define KIRKWOOD_MLMB_NWINDOW 8 166 #define KIRKWOOD_MLMB_NREMAP 4 167 168 /* Main Interrupt Controller Registers */ 169 #define KIRKWOOD_MLMB_MICLR 0x200 /*Main Interrupt Cause Low reg*/ 170 #define KIRKWOOD_MLMB_MIRQIMLR 0x204 /*Main IRQ Interrupt Low Mask*/ 171 #define KIRKWOOD_MLMB_MFIQIMLR 0x208 /*Main FIQ Interrupt Low Mask*/ 172 #define KIRKWOOD_MLMB_EIMLR 0x20c /*Endpoint Interrupt Low Mask*/ 173 #define KIRKWOOD_MLMB_MICHR 0x210 /*Main Intr Cause High reg*/ 174 #define KIRKWOOD_MLMB_MIRQIMHR 0x214 /*Main IRQ Interrupt High Mask*/ 175 #define KIRKWOOD_MLMB_MFIQIMHR 0x218 /*Main FIQ Interrupt High Mask*/ 176 #define KIRKWOOD_MLMB_EIMHR 0x21c /*Endpoint Interrupt High Mask*/ 177 178 179 /* 180 * Kirkwood Thermal Sensor(6282 only) 181 */ 182 #define KIRKWOOD_TS_BASE (MVSOC_DEVBUS_BASE + 0x0078) /* XXXX: ??? */ 183 184 /* 185 * Two-Wire Serial Interface Registers 186 */ 187 #define KIRKWOOD_TWSI1_BASE (MVSOC_TWSI_BASE + 0x0100) 188 189 /* 190 * PCI-Express Interface Registers 191 */ 192 #define KIRKWOOD_PEX1_BASE (MVSOC_PEX_BASE + 0x4000) 193 194 /* 195 * Cryptographic Engine and Security Accelerator Registers 196 */ /* 0x3d000 */ 197 #define KIRKWOOD_CESA_BASE (KIRKWOOD_UNITID2PHYS(CRYPT) + 0xd000) 198 199 /* 200 * USB 2.0 Interface Registers 201 */ 202 #define KIRKWOOD_USB_BASE (KIRKWOOD_UNITID2PHYS(USB)) /* 0x50000 */ 203 204 /* 205 * IDMA Controller and XOR Engine Registers 206 */ 207 #define KIRKWOOD_IDMAC_BASE (KIRKWOOD_UNITID2PHYS(IDMA)) /* 0x60000 */ 208 209 /* 210 * Gigabit Ethernet Registers 211 */ 212 #define KIRKWOOD_GBE0_BASE (KIRKWOOD_UNITID2PHYS(GBE)) /* 0x70000 */ 213 #define KIRKWOOD_GBE1_BASE (KIRKWOOD_GBE0_BASE + MVGBE_SIZE) 214 215 /* 216 * Serial-ATA Host Controller (SATAHC) Registers 217 */ 218 #define KIRKWOOD_SATAHC_BASE (KIRKWOOD_UNITID2PHYS(SATA)) /* 0x80000 */ 219 220 /* 221 * Secure Digital Input/Output (SDIO) Interface Registers 222 */ 223 #define KIRKWOOD_SDIO_BASE (KIRKWOOD_UNITID2PHYS(SDIO)) /* 0x90000 */ 224 225 /* 226 * Audio (I2S/S/PDIF) Interface Registers 227 */ 228 #define KIRKWOOD_AUDIO_BASE (KIRKWOOD_UNITID2PHYS(AUDIO)) /* 0xa0000 */ 229 230 /* 231 * MPEG-2 Transport Stream (TS) Interface Registers 232 */ 233 #define KIRKWOOD_MTS_BASE (KIRKWOOD_UNITID2PHYS(MTS)) /* 0xb0000 */ 234 235 /* 236 * Time Division Multiplexing (TDM) Unit Registers 237 */ 238 #define KIRKWOOD_TDM_BASE (KIRKWOOD_UNITID2PHYS(TDM)) /* 0xd0000 */ 239 240 #endif /* _KIRKWOODREG_H_ */ 241
Indexes created Sat Sep 27 14:09:57 GMT 2025