1 /* $NetBSD: kmin.h,v 1.10 2005/12/11 12:18:39 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * The Mach Operating System project at Carnegie-Mellon University, 9 * Ralph Campbell and Rick Macklem. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. Neither the name of the University nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * @(#)kmin.h 8.1 (Berkeley) 6/10/93 36 */ 37 38 /* 39 * Mach Operating System 40 * Copyright (c) 1991,1990,1989 Carnegie Mellon University 41 * All Rights Reserved. 42 * 43 * Permission to use, copy, modify and distribute this software and 44 * its documentation is hereby granted, provided that both the copyright 45 * notice and this permission notice appear in all copies of the 46 * software, derivative works or modified versions, and any portions 47 * thereof, and that both notices appear in supporting documentation. 48 * 49 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 50 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 51 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 52 * 53 * Carnegie Mellon requests users of this software to return to 54 * 55 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 56 * School of Computer Science 57 * Carnegie Mellon University 58 * Pittsburgh PA 15213-3890 59 * 60 * any improvements or extensions that they make and grant Carnegie the 61 * rights to redistribute these changes. 62 */ 63 /* 64 * HISTORY 65 * Log: kmin.h,v 66 * Revision 2.3 92/03/02 18:33:43 rpd 67 * Split out the ASIC defns into separate file, which is 68 * in common with MAXine. Added some nitwits defines. 69 * [92/03/02 02:28:27 af] 70 * 71 * Revision 2.2 91/08/24 12:21:08 af 72 * Documented new SCSI registers, which were missing in the 3min prototype. 73 * [91/08/22 11:14:57 af] 74 * 75 * Created, from the DEC specs: 76 * "3MIN System Module Functional Specification" Revision 1.7 77 * Workstation Systems Engineering, Palo Alto, CA. Sept 14, 1990. 78 * "KN02BA Daughter Card Functional Specification" Revision 1.0 79 * Workstation Systems Engineering, Palo Alto, CA. Aug 14, 1990. 80 * [91/06/21 af] 81 * 82 */ 83 /* 84 * File: kmin.h 85 * Author: Alessandro Forin, Carnegie Mellon University 86 * Date: 6/91 87 * 88 * Definitions specific to the KN02BA/KN02DA processors and 3MIN 89 * system module (54-20604-01) 90 */ 91 92 #ifndef MIPS_KMIN_H 93 #define MIPS_KMIN_H 1 94 95 /* 96 * 3MIN's Physical address space 97 */ 98 #define KMIN_PHYS_MIN 0x00000000 /* 512 Meg */ 99 #define KMIN_PHYS_MAX 0x1fffffff 100 101 /* 102 * Memory map 103 */ 104 #define KMIN_PHYS_MEMORY_START 0x00000000 105 #define KMIN_PHYS_MEMORY_END 0x07ffffff /* 128 Meg in 8 slots */ 106 107 /* 108 * I/O map 109 */ 110 #define KMIN_PHYS_RESERVED 0x08000000 /* Reserved */ 111 /* 64 Meg */ 112 113 #define KMIN_PHYS_MREGS_START 0x0c000000 /* Memory control registers */ 114 #define KMIN_PHYS_MREGS_END 0x0dffffff /* 32 Meg */ 115 #define KMIN_PHYS_CREGS_START 0x0e000000 /* CPU ASIC control regs */ 116 #define KMIN_PHYS_CREGS_END 0x0fffffff /* 32 Meg */ 117 118 #define KMIN_PHYS_TC_0_START 0x10000000 /* TURBOchannel, slot 0 */ 119 #define KMIN_PHYS_TC_0_END 0x13ffffff /* 64 Meg, option0 */ 120 121 #define KMIN_PHYS_TC_1_START 0x14000000 /* TURBOchannel, slot 1 */ 122 #define KMIN_PHYS_TC_1_END 0x17ffffff /* 64 Meg, option1 */ 123 124 #define KMIN_PHYS_TC_2_START 0x18000000 /* TURBOchannel, slot 2 */ 125 #define KMIN_PHYS_TC_2_END 0x1bffffff /* 64 Meg, option2 */ 126 127 #define KMIN_PHYS_TC_3_START 0x1c000000 /* TURBOchannel, slot 3 */ 128 #define KMIN_PHYS_TC_3_END 0x1fffffff /* 64 Meg, system devices */ 129 130 #define KMIN_PHYS_TC_START KMIN_PHYS_TC_0_START 131 #define KMIN_PHYS_TC_END KMIN_PHYS_TC_3_END /* 256 Meg */ 132 133 #define KMIN_TC_NSLOTS 4 134 #define KMIN_TC_MIN 0 135 #define KMIN_TC_MAX 2 /* don't look at system slot */ 136 137 /* 138 * System module space (IOASIC) 139 */ 140 #define KMIN_SYS_ASIC ( KMIN_PHYS_TC_3_START + 0x0000000 ) 141 #define KMIN_SYS_ROM_START ( KMIN_SYS_ASIC + IOASIC_SLOT_0_START ) 142 #define KMIN_SYS_ASIC_REGS ( KMIN_SYS_ASIC + IOASIC_SLOT_1_START ) 143 #define KMIN_SYS_ETHER_ADDRESS ( KMIN_SYS_ASIC + IOASIC_SLOT_2_START ) 144 #define KMIN_SYS_LANCE ( KMIN_SYS_ASIC + IOASIC_SLOT_3_START ) 145 #define KMIN_SYS_SCC_0 ( KMIN_SYS_ASIC + IOASIC_SLOT_4_START ) 146 #define KMIN_SYS_SCC_1 ( KMIN_SYS_ASIC + IOASIC_SLOT_6_START ) 147 #define KMIN_SYS_CLOCK ( KMIN_SYS_ASIC + IOASIC_SLOT_8_START ) 148 #define KMIN_SYS_SCSI ( KMIN_SYS_ASIC + IOASIC_SLOT_12_START ) 149 #define KMIN_SYS_SCSI_DMA ( KMIN_SYS_ASIC + IOASIC_SLOT_14_START ) 150 #define KMIN_SYS_BOOT_ROM_START ( KMIN_PHYS_TC_3_START + 0x3c00000 ) 151 #define KMIN_SYS_BOOT_ROM_END ( KMIN_PHYS_TC_3_START + 0x3c40000 ) 152 153 /* 154 * Interrupts 155 */ 156 #define KMIN_INT_FPA IP_LEV7 /* Floating Point coproc */ 157 #define KMIN_INT_HALTB IP_LEV6 /* Halt button */ 158 #define KMIN_INT_TC3 IP_LEV5 /* TC slot 3, system */ 159 #define KMIN_INT_TC2 IP_LEV4 /* TC option slot 2 */ 160 #define KMIN_INT_TC1 IP_LEV3 /* TC option slot 1 */ 161 #define KMIN_INT_TC0 IP_LEV2 /* TC option slot 0 */ 162 163 /* 164 * System registers addresses (MREG and CREG space, and IO Control ASIC) 165 */ 166 #define KMIN_REG_MER 0x0c400000 /* Memory error register */ 167 #define KMIN_REG_MSR 0x0c800000 /* Memory size register */ 168 169 #define KMIN_REG_CNFG 0x0e000000 /* Config mem timeouts */ 170 #define KMIN_REG_AER 0x0e000004 /* Address error register */ 171 #define KMIN_REG_BOOT 0x0e000008 /* Boot 0 register */ 172 #define KMIN_REG_TIMEOUT 0x0e00000c /* Mem access timeout reg */ 173 174 #define KMIN_REG_SCSI_DMAPTR ( KMIN_SYS_ASIC + IOASIC_SCSI_DMAPTR ) 175 #define KMIN_REG_SCSI_DMANPTR ( KMIN_SYS_ASIC + IOASIC_SCSI_NEXTPTR ) 176 #define KMIN_REG_LANCE_DMAPTR ( KMIN_SYS_ASIC + IOASIC_LANCE_DMAPTR ) 177 #define KMIN_REG_SCC_T1_DMAPTR ( KMIN_SYS_ASIC + IOASIC_SCC_T1_DMAPTR ) 178 #define KMIN_REG_SCC_R1_DMAPTR ( KMIN_SYS_ASIC + IOASIC_SCC_R1_DMAPTR ) 179 #define KMIN_REG_SCC_T2_DMAPTR ( KMIN_SYS_ASIC + IOASIC_SCC_T2_DMAPTR ) 180 #define KMIN_REG_SCC_R2_DMAPTR ( KMIN_SYS_ASIC + IOASIC_SCC_R2_DMAPTR ) 181 #define KMIN_REG_CSR ( KMIN_SYS_ASIC + IOASIC_CSR ) 182 #define KMIN_REG_INTR ( KMIN_SYS_ASIC + IOASIC_INTR ) 183 #define KMIN_REG_IMSK ( KMIN_SYS_ASIC + IOASIC_IMSK ) 184 #define KMIN_REG_CURADDR ( KMIN_SYS_ASIC + IOASIC_CURADDR ) 185 186 #define KMIN_REG_LANCE_DECODE ( KMIN_SYS_ASIC + IOASIC_LANCE_DECODE ) 187 #define KMIN_REG_SCSI_DECODE ( KMIN_SYS_ASIC + IOASIC_SCSI_DECODE ) 188 #define KMIN_REG_SCC0_DECODE ( KMIN_SYS_ASIC + IOASIC_SCC0_DECODE ) 189 #define KMIN_REG_SCC1_DECODE ( KMIN_SYS_ASIC + IOASIC_SCC1_DECODE ) 190 # define KMIN_LANCE_CONFIG 3 191 # define KMIN_SCSI_CONFIG 14 192 # define KMIN_SCC0_CONFIG (0x10|4) 193 # define KMIN_SCC1_CONFIG (0x10|6) 194 195 #define KMIN_REG_SCSI_SCR ( KMIN_SYS_ASIC + IOASIC_SCSI_SCR ) 196 #define KMIN_REG_SCSI_SDR0 ( KMIN_SYS_ASIC + IOASIC_SCSI_SDR0 ) 197 #define KMIN_REG_SCSI_SDR1 ( KMIN_SYS_ASIC + IOASIC_SCSI_SDR1 ) 198 199 200 /* 201 * System registers defines (MREG and CREG) 202 */ 203 /* Memory error register */ 204 #define KMIN_MER_xxx 0xfffe30ff /* undefined */ 205 #define KMIN_MER_PAGE_BRY 0x00010000 /* rw: Page boundary error */ 206 #define KMIN_MER_TLEN 0x00008000 /* rw: Xfer length error */ 207 #define KMIN_MER_PARDIS 0x00004000 /* rw: Dis parity err intr */ 208 #define KMIN_MER_LASTBYTE 0x00000f00 /* rz: Last byte in error: */ 209 # define KMIN_LASTB31 0x00000800 /* upper byte of word */ 210 # define KMIN_LASTB23 0x00000400 /* .. through .. */ 211 # define KMIN_LASTB15 0x00000200 /* .. the .. */ 212 # define KMIN_LASTB07 0x00000100 /* .. lower byte */ 213 214 /* Memory size register */ 215 #define KMIN_MSR_SIZE_16Mb 0x00002000 /* rw: using 16Mb mem banks */ 216 #define KMIN_MSR_xxx 0xffffdfff /* undefined */ 217 218 /* NOTES 219 220 Memory access priority is, from higher to lower: 221 - DRAM refresh 222 - IO DMA (IO Control ASIC) 223 - Processor 224 - Slot 2 DMA 225 - Slot 1 DMA 226 - Slot 0 DMA 227 228 Memory performance is (with 80ns mem cycles) 229 - single word read 5 cyc 10.0 Mb/s 230 - word write 3 cyc 16.7 Mb/s 231 - single byte write 3 cyc 4.2 Mb/s 232 - 64w DMA read 68 cyc 47.1 Mb/s 233 - 64w DMA write 66 cyc 48.5 Mb/s 234 - Refresh 5 cyc N/A 235 */ 236 237 /* Timeout config register */ 238 #define KMIN_CNFG_VALUE_12Mhz 127 239 #define KMIN_CNFG_VALUE_25Mhz 0 240 241 /* Address error register */ 242 #define KMIN_AER_ADDR_MASK 0x1ffffffc /* ro: phys addr in error */ 243 244 /* Boot 0 register */ 245 #define KMIN_BOOT_FROM_SLOT0 0x00000001 /* rw: diag board boot */ 246 247 /* Memory access timeout interrupt register */ 248 #define KMIN_TIMEO_INTR 0x00000001 /* rc: intr pending */ 249 250 /* 251 * More system registers defines (IOASIC) 252 */ 253 /* (re)defines for the system Status and Control register (SSR) */ 254 /* high-order 16 bits 0xFFFF0000 same on all DECstation IOASICs */ 255 #define KMIN_CSR_DIAGDN 0x00008000 /* rw */ 256 #define KMIN_CSR_TXDIS_2 0x00004000 /* rw */ 257 #define KMIN_CSR_TXDIS_1 0x00002000 /* rw */ 258 #define KMIN_CSR_SCC_ENABLE 0x00000800 /* rw */ 259 #define KMIN_CSR_RTC_ENABLE 0x00000400 /* rw */ 260 #define KMIN_CSR_SCSI_ENABLE 0x00000200 /* rw */ 261 #define KMIN_CSR_LANCE_ENABLE 0x00000100 /* rw */ 262 #define KMIN_CSR_LEDS 0x000000ff /* rw */ 263 264 /* (re)defines for the System Interrupt and Mask Registers */ 265 /* high-order 16 bits 0xFFFF0000 same on all DECstation IOASICs */ 266 #define KMIN_INTR_NVR_JUMPER 0x00004000 /* ro */ 267 #define KMIN_INTR_TIMEOUT 0x00001000 /* ro */ 268 #define KMIN_INTR_NRMOD_JUMPER 0x00000400 /* ro */ 269 #define KMIN_INTR_SCSI 0x00000200 /* ro */ 270 #define KMIN_INTR_LANCE 0x00000100 /* ro */ 271 #define KMIN_INTR_SCC_1 0x00000080 /* ro */ 272 #define KMIN_INTR_SCC_0 0x00000040 /* ro */ 273 #define KMIN_INTR_CLOCK 0x00000020 /* ro */ 274 #define KMIN_INTR_PSWARN 0x00000010 /* ro */ 275 #define KMIN_INTR_SCSI_FIFO 0x00000004 /* ro */ 276 #define KMIN_INTR_PBNC 0x00000002 /* ro */ 277 #define KMIN_INTR_PBNO 0x00000001 /* ro */ 278 #define KMIN_INTR_ASIC 0xff0f0004 279 #define KMIN_IM0 0xff0f13f0 /* all good ones enabled */ 280 281 #endif /* MIPS_KMIN_H */ 282
Indexes created Tue Sep 30 11:09:46 GMT 2025