1 /* $NetBSD: kn03.h,v 1.13 2017/06/22 16:46:53 flxd Exp $ */ 2 3 /*- 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * The Mach Operating System project at Carnegie-Mellon University, 9 * Ralph Campbell and Rick Macklem. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. Neither the name of the University nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * @(#)kn03.h 8.1 (Berkeley) 6/10/93 36 */ 37 38 /* 39 * Mach Operating System 40 * Copyright (c) 1991,1990,1989 Carnegie Mellon University 41 * All Rights Reserved. 42 * 43 * Permission to use, copy, modify and distribute this software and 44 * its documentation is hereby granted, provided that both the copyright 45 * notice and this permission notice appear in all copies of the 46 * software, derivative works or modified versions, and any portions 47 * thereof, and that both notices appear in supporting documentation. 48 * 49 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 50 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 51 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 52 * 53 * Carnegie Mellon requests users of this software to return to 54 * 55 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 56 * School of Computer Science 57 * Carnegie Mellon University 58 * Pittsburgh PA 15213-3890 59 * 60 * any improvements or extensions that they make and grant Carnegie the 61 * rights to redistribute these changes. 62 */ 63 /* 64 * Definitions specific to the KN03GA processors and 3MAX+ 65 * DECstation 5000/240 mother board. 66 */ 67 68 #ifndef MIPS_KN03_H 69 #define MIPS_KN03_H 1 70 71 /* 72 * 3MAX+'s Physical address space 73 */ 74 #define KN03_PHYS_MIN 0x00000000 /* 512 Meg */ 75 #define KN03_PHYS_MAX 0x1fffffff 76 77 /* 78 * Memory map 79 */ 80 #define KN03_PHYS_MEMORY_START 0x00000000 81 #define KN03_PHYS_MEMORY_END 0x1dffffff /* 480 Meg */ 82 83 /* 84 * I/O map 85 */ 86 #define KN03_PHYS_TC_0_START 0x1e000000 /* TURBOchannel, slot 0 */ 87 #define KN03_PHYS_TC_0_END 0x1e7fffff /* 8 Meg, option0 */ 88 89 #define KN03_PHYS_TC_1_START 0x1e800000 /* TURBOchannel, slot 1 */ 90 #define KN03_PHYS_TC_1_END 0x1effffff /* 8 Meg, option1 */ 91 92 #define KN03_PHYS_TC_2_START 0x1f000000 /* TURBOchannel, slot 2 */ 93 #define KN03_PHYS_TC_2_END 0x1f7fffff /* 8 Meg, option2 */ 94 95 #define KN03_PHYS_TC_3_START 0x1f800000 /* TURBOchannel, slot 3 */ 96 #define KN03_PHYS_TC_3_END 0x1fffffff /* 8 Meg, system devices */ 97 98 #define KN03_PHYS_TC_START KN03_PHYS_TC_0_START 99 #define KN03_PHYS_TC_END KN03_PHYS_TC_3_END 100 101 #define KN03_TC_NSLOTS 4 102 #define KN03_TC_MIN 0 103 #define KN03_TC_MAX 2 /* don't look at system slot */ 104 105 /* 106 * System module space (IOASIC) 107 */ 108 #define KN03_SYS_ASIC ( KN03_PHYS_TC_3_START + 0x0000000 ) 109 #define KN03_SYS_ROM_START ( KN03_SYS_ASIC + IOASIC_SLOT_0_START ) 110 #define KN03_SYS_ASIC_REGS ( KN03_SYS_ASIC + IOASIC_SLOT_1_START ) 111 #define KN03_SYS_ETHER_ADDRESS ( KN03_SYS_ASIC + IOASIC_SLOT_2_START ) 112 #define KN03_SYS_LANCE ( KN03_SYS_ASIC + IOASIC_SLOT_3_START ) 113 #define KN03_SYS_SCC_0 ( KN03_SYS_ASIC + IOASIC_SLOT_4_START ) 114 #define KN03_SYS_SCC_1 ( KN03_SYS_ASIC + IOASIC_SLOT_6_START ) 115 #define KN03_SYS_CLOCK ( KN03_SYS_ASIC + IOASIC_SLOT_8_START ) 116 #define KN03_SYS_ERRADR ( KN03_SYS_ASIC + IOASIC_SLOT_9_START ) 117 #define KN03_SYS_ERRSYN ( KN03_SYS_ASIC + IOASIC_SLOT_10_START ) 118 #define KN03_SYS_CSR ( KN03_SYS_ASIC + IOASIC_SLOT_11_START ) 119 #define KN03_SYS_SCSI ( KN03_SYS_ASIC + IOASIC_SLOT_12_START ) 120 #define KN03_SYS_SCSI_DMA ( KN03_SYS_ASIC + IOASIC_SLOT_14_START ) 121 #define KN03_SYS_BOOT_ROM_START ( KN03_PHYS_TC_3_START + 0x400000 ) 122 #define KN03_SYS_BOOT_ROM_END ( KN03_PHYS_TC_3_START + 0x43ffff ) 123 124 /* 125 * Interrupts 126 */ 127 #define KN03_INT_FPA IP_LEV7 /* Floating Point coproc */ 128 #define KN03_INT_HALTB IP_LEV6 /* Halt button */ 129 #define KN03_INT_MEM IP_LEV5 /* Memory Errors */ 130 #define KN03_INT_RTC IP_LEV3 /* RTC clock */ 131 #define KN03_INT_ASIC IP_LEV2 /* All TURBOchannel */ 132 133 #define KN03_REG_SCSI_DMAPTR ( KN03_SYS_ASIC + IOASIC_SCSI_DMAPTR ) 134 #define KN03_REG_SCSI_DMANPTR ( KN03_SYS_ASIC + IOASIC_SCSI_NEXTPTR ) 135 #define KN03_REG_LANCE_DMAPTR ( KN03_SYS_ASIC + IOASIC_LANCE_DMAPTR ) 136 #define KN03_REG_SCC_T1_DMAPTR ( KN03_SYS_ASIC + IOASIC_SCC_T1_DMAPTR ) 137 #define KN03_REG_SCC_R1_DMAPTR ( KN03_SYS_ASIC + IOASIC_SCC_R1_DMAPTR ) 138 #define KN03_REG_SCC_T2_DMAPTR ( KN03_SYS_ASIC + IOASIC_SCC_T2_DMAPTR ) 139 #define KN03_REG_SCC_R2_DMAPTR ( KN03_SYS_ASIC + IOASIC_SCC_R2_DMAPTR ) 140 #define KN03_REG_CSR ( KN03_SYS_ASIC + IOASIC_CSR ) 141 #define KN03_REG_INTR ( KN03_SYS_ASIC + IOASIC_INTR ) 142 #define KN03_REG_IMSK ( KN03_SYS_ASIC + IOASIC_IMSK ) 143 #define KN03_REG_CURADDR ( KN03_SYS_ASIC + IOASIC_CURADDR ) 144 145 #define KN03_REG_LANCE_DECODE ( KN03_SYS_ASIC + IOASIC_LANCE_DECODE ) 146 #define KN03_REG_SCSI_DECODE ( KN03_SYS_ASIC + IOASIC_SCSI_DECODE ) 147 #define KN03_REG_SCC0_DECODE ( KN03_SYS_ASIC + IOASIC_SCC0_DECODE ) 148 #define KN03_REG_SCC1_DECODE ( KN03_SYS_ASIC + IOASIC_SCC1_DECODE ) 149 # define KN03_LANCE_CONFIG 3 150 # define KN03_SCSI_CONFIG 14 151 # define KN03_SCC0_CONFIG (0x10|4) 152 # define KN03_SCC1_CONFIG (0x10|6) 153 154 #define KN03_REG_SCSI_SCR ( KN03_SYS_ASIC + IOASIC_SCSI_SCR ) 155 #define KN03_REG_SCSI_SDR0 ( KN03_SYS_ASIC + IOASIC_SCSI_SDR0 ) 156 #define KN03_REG_SCSI_SDR1 ( KN03_SYS_ASIC + IOASIC_SCSI_SDR1 ) 157 158 /* NOTES 159 160 Memory access priority is, from higher to lower: 161 - DRAM refresh 162 - IO DMA (IO Control ASIC) 163 - Slot 2 DMA 164 - Slot 1 DMA 165 - Slot 0 DMA 166 - Processor 167 168 */ 169 170 /* 171 * More system registers defines (IO Control ASIC) 172 */ 173 /* (re)defines for the system Status and Control register (SSR) */ 174 /* high-order 16 bits 0xFFFF0000 same on all DECstation IOASICs */ 175 #define KN03_CSR_LEDS 0x000000ff /* rw */ 176 #define KN03_CSR_BNK32M 0x00000400 /* rw Memory bank stride */ 177 #define KN03_CSR_CORRECT 0x00002000 /* rw ECC corrects single bit */ 178 #define KN03_CSR_ECCMD 0x0000c000 /* rw ECC logic mode */ 179 180 /* (re)defines for the System Interrupt and Mask Registers */ 181 /* high-order 16 bits 0xFFFF0000 same on all DECstation IOASICs */ 182 #define KN03_INTR_PBNO 0x00000001 /* ro */ 183 #define KN03_INTR_PBNC 0x00000002 /* ro */ 184 #define KN03_INTR_SCSI_FIFO 0x00000004 /* ro */ 185 #define KN03_INTR_PSWARN 0x00000010 /* ro */ 186 #define KN03_INTR_CLOCK 0x00000020 /* ro */ 187 #define KN03_INTR_SCC_0 0x00000040 /* ro */ 188 #define KN03_INTR_SCC_1 0x00000080 /* ro */ 189 #define KN03_INTR_LANCE 0x00000100 /* ro */ 190 #define KN03_INTR_SCSI 0x00000200 /* ro */ 191 #define KN03_INTR_NRMOD_JUMPER 0x00000400 /* ro */ 192 #define KN03_INTR_TC_0 0x00000800 /* ro */ 193 #define KN03_INTR_TC_1 0x00001000 /* ro */ 194 #define KN03_INTR_TC_2 0x00002000 /* ro */ 195 #define KN03_INTR_NVR_JUMPER 0x00004000 /* ro */ 196 #define KN03_INTR_PROD_JUMPER 0x00008000 /* ro */ 197 198 #define KN03_INTR_ASIC 0xff0f0004 199 #define KN03_IM0 0xff0f3bf0 /* all good ones enabled */ 200 201 /* 202 * Error Address Register Bit Definitions 203 */ 204 #define KN03_ERR_ADDRESS 0x07ffffff /* phys address */ 205 #define KN03_ERR_RESERVED 0x08000000 /* unused */ 206 #define KN03_ERR_ECCERR 0x10000000 /* ECC error */ 207 #define KN03_ERR_WRITE 0x20000000 /* read/write transaction */ 208 #define KN03_ERR_CPU 0x40000000 /* CPU or device initiator */ 209 #define KN03_ERR_VALID 0x80000000 /* Info is valid */ 210 211 /* ECC check/syndrome status register */ 212 #define KN03_ECC_SYNLO 0x0000007f /* syndrome, even bank */ 213 #define KN03_ECC_SNGLO 0x00000080 /* single bit err, " */ 214 #define KN03_ECC_CHKLO 0x00007f00 /* check bits, " " */ 215 #define KN03_ECC_VLDLO 0x00008000 /* info valid for " */ 216 #define KN03_ECC_SYNHI 0x007f0000 /* syndrome, odd bank */ 217 #define KN03_ECC_SNGHI 0x00800000 /* single bit err, " */ 218 #define KN03_ECC_CHKHI 0x7f000000 /* check bits, " " */ 219 #define KN03_ECC_VLDHI 0x80000000 /* info valid for " */ 220 221 #endif /* MIPS_KN03_H */ 222
Indexes created Fri Sep 26 20:09:58 GMT 2025