1 /* $NetBSD: amcc460ex.h,v 1.4 2026/06/22 12:34:20 rkujawa Exp $ */ 2 3 /* 4 * Copyright (c) 2012, 2014, 2024, 2026 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Radoslaw Kujawa. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 /* 32 * AMCC/AppliedMicro 460EX system-on-chip 33 */ 34 35 #ifndef _IBM4XX_AMCC460EX_H_ 36 #define _IBM4XX_AMCC460EX_H_ 37 38 /* Upper 4 bits (ERPN) of the physical address of the I/O region */ 39 #define AMCC460EX_OPB_PA_HIGH 0x4 40 41 #define AMCC460EX_OPB_BASE 0xef600000 42 43 #define AMCC460EX_UART0_BASE 0xef600300 44 #define AMCC460EX_UART1_BASE 0xef600400 45 #define AMCC460EX_UART2_BASE 0xef600500 46 #define AMCC460EX_UART3_BASE 0xef600600 47 #define AMCC460EX_IIC0_BASE 0xef600700 48 #define AMCC460EX_IIC1_BASE 0xef600800 49 #define AMCC460EX_GPIO0_BASE 0xef600b00 50 #define AMCC460EX_ZMII0_BASE 0xef600d00 51 #define AMCC460EX_EMAC0_BASE 0xef600e00 52 #define AMCC460EX_EMAC1_BASE 0xef600f00 53 #define AMCC460EX_TAH0_BASE 0xef601350 54 #define AMCC460EX_TAH1_BASE 0xef601450 55 #define AMCC460EX_RGMII0_BASE 0xef601500 56 57 /* UARTs get freq from external 11.0592 MHz osc */ 58 #define AMCC460EX_COM_FREQ 11059200 59 60 /* 61 * PLB-PCIX host bridge. 62 */ 63 #define AMCC460EX_PCIX0_CFG_PLBA 0x0ec00000 /* ERPN 0xc */ 64 #define AMCC460EX_PCIX0_REGS_PLBA 0x0ec80000 /* ERPN 0xc */ 65 #define AMCC460EX_PCIX0_CFG_PA_HIGH 0xc 66 #define AMCC460EX_PCIX0_IO_PLBA 0x08000000 /* ERPN 0xc */ 67 #define AMCC460EX_PCIX0_IO_PA_HIGH 0xc 68 #define AMCC460EX_PCIX0_MEM_BASE 0x80000000 /* ERPN 0xd */ 69 #define AMCC460EX_PCIX0_MEM_PLBA_H 0xd 70 /* How much of the (128MB) outbound memory window has pinned mappings */ 71 #define AMCC460EX_PCIX0_MEM_SIZE 0x05000000 /* 80MB */ 72 73 /* 74 * Second outbound memory window (POM1) 75 */ 76 #define AMCC460EX_PCIX0_PMEM_BASE 0x88000000 /* ERPN 0xd */ 77 #define AMCC460EX_PCIX0_PMEM_PLBA_H 0xd 78 #define AMCC460EX_PCIX0_PMEM_SIZE 0x10000000 /* 256MB POM1/extent */ 79 /* How much of the prefetchable window gets pinned into kernel VA */ 80 #define AMCC460EX_PCIX0_PMEM_MAP 0x04000000 /* 64MB */ 81 82 /* 83 * PCI Express root complexes (PCIE0/PCIE1). 84 */ 85 #define AMCC460EX_PCIE0_DCR_BASE 0x100 /* PEGPL register block */ 86 #define AMCC460EX_PCIE1_DCR_BASE 0x120 87 88 #define AMCC460EX_PCIE_CFG_PA_HIGH 0xd /* ERPN of config windows */ 89 #define AMCC460EX_PCIE0_CFG_PLBA 0x30000000 90 /* 91 * The PCIe core - port's local config 92 * XCFG: PECFG inbound BAR/PIM at cfg-region-base + 0x10000000 93 */ 94 #define AMCC460EX_PCIE1_CFG_PLBA 0x40000000 95 #define AMCC460EX_PCIE_CFG_SIZE 0x01000000 /* ECAM: buses 0-15 */ 96 #define AMCC460EX_PCIE_CFG_REGION_SIZE 0x20000000 /* PEGPL region: 512MB */ 97 #define AMCC460EX_PCIE_XCFG_OFFSET 0x10000000 /* local cfg vs region base */ 98 #define AMCC460EX_PCIE1_XCFG_PLBA (AMCC460EX_PCIE1_CFG_PLBA + \ 99 AMCC460EX_PCIE_XCFG_OFFSET) 100 101 #define AMCC460EX_PCIE_MEM_PA_HIGH 0xe /* ERPN of memory windows */ 102 #define AMCC460EX_PCIE0_MEM_PLBA 0x10000000 103 #define AMCC460EX_PCIE1_MEM_PLBA 0x90000000 104 #define AMCC460EX_PCIE_MEM_BASE 0xa0000000 /* PCI-side base */ 105 #define AMCC460EX_PCIE_MEM_SIZE 0x01000000 106 107 /* 108 * AHB peripherals (USB). 109 */ 110 #define AMCC460EX_AHB_PA_HIGH 0x4 /* ERPN */ 111 #define AMCC460EX_AHB_BASE 0xbf000000 112 #define AMCC460EX_AHB_SIZE 0x01000000 113 114 #define AMCC460EX_USB_OTG_BASE 0xbff80000 /* DWC OTG, 256KB */ 115 #define AMCC460EX_USB_OTG_SIZE 0x00040000 116 #define AMCC460EX_USB_OHCI_BASE 0xbffd0000 117 #define AMCC460EX_USB_OHCI_SIZE 0x00000400 118 #define AMCC460EX_USB_EHCI_BASE 0xbffd0400 119 #define AMCC460EX_USB_EHCI_SIZE 0x00000400 120 121 /* 122 * On-chip SATA, the lousy DWC SATA-II core 123 */ 124 #define AMCC460EX_SATA_DMA_BASE 0xbffd0800 125 #define AMCC460EX_SATA_DMA_SIZE 0x00000400 126 #define AMCC460EX_SATA_BASE 0xbffd1000 127 #define AMCC460EX_SATA_SIZE 0x00000800 128 129 /* 130 * Per-port PCIe SDR registers 131 */ 132 #define AMCC460EX_PESDR0_LOOP 0x303 133 #define AMCC460EX_PESDR0_RCSSET 0x304 134 #define AMCC460EX_PESDR0_RCSSTS 0x305 135 #define AMCC460EX_PESDR1_LOOP 0x343 136 #define AMCC460EX_PESDR1_RCSSET 0x344 137 #define AMCC460EX_PESDR1_RCSSTS 0x345 138 139 #define AMCC460EX_PESDR_LOOP_LNKUP 0x00001000 /* link trained */ 140 141 /* 142 * Interrupt numbers in the flat PIC space: 143 * UIC0 : irqs 0-31 144 * UIC1 : cascaded via UIC0 bit 30) is irqs 32-63 145 * UIC2 : (UIC0 bit 10) is irqs 64-95 146 * UIC3 : (UIC0 bit 16) is irqs 96-127 147 */ 148 #define AMCC460EX_UART0_IRQ 33 /* UIC1 bit 1 */ 149 #define AMCC460EX_UART1_IRQ 1 /* UIC0 bit 1 */ 150 #define AMCC460EX_IIC0_IRQ 2 /* UIC0 bit 2 */ 151 #define AMCC460EX_IIC1_IRQ 3 /* UIC0 bit 3 */ 152 #define AMCC460EX_PCI_IRQ 32 /* UIC1 bit 0: PCI INTA */ 153 #define AMCC460EX_MAL_TXEOB_IRQ 70 /* UIC2 bit 6 */ 154 #define AMCC460EX_MAL_RXEOB_IRQ 71 /* UIC2 bit 7 */ 155 #define AMCC460EX_EMAC0_IRQ 80 /* UIC2 bit 16 */ 156 #define AMCC460EX_EMAC1_IRQ 81 /* UIC2 bit 17 */ 157 #define AMCC460EX_USB_EHCI_IRQ 93 /* UIC2 bit 29 */ 158 #define AMCC460EX_USB_OHCI_IRQ 94 /* UIC2 bit 30 */ 159 #define AMCC460EX_SATA_IRQ 96 /* UIC3 bit 0 */ 160 #define AMCC460EX_SATA_DMA_IRQ 101 /* UIC3 bit 5: AHB DMAC */ 161 162 /* 163 * L2 cache controller (L2C0) device control registers. 164 */ 165 #define DCR_L2C0_CFG 0x030 /* L2 cache configuration */ 166 #define L2C_CFG_L2M 0x80000000 /* SRAM array used as L2 */ 167 #define L2C_CFG_ICU 0x40000000 /* I-cache uses L2 */ 168 #define L2C_CFG_DCU 0x20000000 /* D-cache uses L2 */ 169 #define L2C_CFG_FRAN 0x00200000 /* fast read ack (best perf) */ 170 #define L2C_CFG_SS_256KB 0x00000000 /* SRAM size 256KB (only) */ 171 #define L2C_CFG_SNPCI 0x00000020 /* snoop cache-inhibit writes */ 172 #define L2C_CFG_RDBW 0x00000008 /* read byte write (required) */ 173 #define DCR_L2C0_CMD 0x031 /* L2 cache command */ 174 #define L2C_CMD_INV 0x20000000 /* invalidate at L2C0_ADDR */ 175 #define L2C_CMD_CCP 0x10000000 /* clear cache parity error */ 176 #define L2C_CMD_CTE 0x08000000 /* clear tag error */ 177 #define L2C_CMD_HCC 0x00800000 /* hardware clear whole cache */ 178 #define DCR_L2C0_ADDR 0x032 /* L2 cache address */ 179 #define DCR_L2C0_DATA 0x033 /* L2 cache data */ 180 #define DCR_L2C0_SR 0x034 /* L2 cache status */ 181 #define L2C_SR_CC 0x80000000 /* command complete */ 182 #define DCR_L2C0_REVID 0x035 /* L2 cache revision id */ 183 #define DCR_L2C0_SNP0 0x036 /* L2 snoop region 0 */ 184 #define DCR_L2C0_SNP1 0x037 /* L2 snoop region 1 */ 185 #define L2C_SNP_SSR_SHIFT 12 /* size field (bits 16:19) shift */ 186 #define L2C_SNP_ESR 0x00000800 /* enable snoop region */ 187 188 /* Internal SRAM0 bank config registers; zeroed to free the array for L2. */ 189 #define DCR_SRAM0_SB0CR 0x020 190 #define DCR_SRAM0_SB1CR 0x021 191 #define DCR_SRAM0_SB2CR 0x022 192 #define DCR_SRAM0_SB3CR 0x023 193 194 /* 195 * AHB-to-PLB bridge CSRs 196 */ 197 #define DCR_AHB_REV 0x0a0 /* revision id */ 198 #define DCR_AHB_TOP 0x0a4 /* PLB2AHB top address */ 199 #define DCR_AHB_BOT 0x0a5 /* PLB2AHB bottom address */ 200 #define DCR_AHB_ATT 0x0a6 /* PLB2AHB attribute */ 201 #define DCR_AHB_CR 0x0a7 /* AHB2PLB control (PUOA in [6:3]) */ 202 #define AHB_CR_PUOA_MASK 0x00000078 /* PLB upper order address */ 203 #define AHB_CR_PUOA_SHIFT 3 204 205 #endif /* _IBM4XX_AMCC460EX_H_ */ 206
Indexes created Tue Jul 07 00:25:39 UTC 2026