1 /* $NetBSD: lan9118reg.h,v 1.4 2024/03/16 18:17:39 andvar Exp $ */ 2 /* 3 * Copyright (c) 2008 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #ifndef _LAN9118REG_H_ 29 #define _LAN9118REG_H_ 30 31 #define LAN9118_IOSIZE 0x100 32 33 #define LAN9118_ID_9115 0x0115 34 #define LAN9118_ID_9116 0x0116 35 #define LAN9118_ID_9117 0x0117 36 #define LAN9118_ID_9118 0x0118 37 #define LAN9218_ID_9215 0x115a 38 #define LAN9218_ID_9217 0x117a 39 #define LAN9218_ID_9218 0x118a 40 41 #define LAN9210_ID_9210 0x9210 42 #define LAN9210_ID_9211 0x9211 43 #define LAN9220_ID_9220 0x9220 44 #define LAN9220_ID_9221 0x9221 45 46 #define IS_LAN9118(id) ((id) >= LAN9118_ID_9115 && (id) <= LAN9118_ID_9118) 47 #define IS_LAN9218(id) ((id) >= LAN9218_ID_9215 && (id) <= LAN9218_ID_9218) 48 49 #define LAN9118_IPHY_ADDR 0x01 /* Internal PHY Address */ 50 51 52 #define LAN9118_RXDFIFOP 0x00 /* RX Data FIFO Port */ 53 #define LAN9118_RXDFIFOAP 0x04 /* RX Data FIFO Alias Ports */ 54 #define LAN9118_TXDFIFOP 0x20 /* TX Data FIFO Port */ 55 #define LAN9118_TXDFIFOAP 0x24 /* TX Data FIFO Alias Ports */ 56 #define LAN9118_RXSFIFOP 0x40 /* RX Status FIFO Port */ 57 #define LAN9118_RXSFIFOPEEK 0x44 /* RX Status FIFO PEEK */ 58 #define LAN9118_TXSFIFOP 0x48 /* TX Status FIFO Port */ 59 #define LAN9118_TXSFIFOPEEK 0x4c /* TX Status FIFO PEEK */ 60 61 /* System Control and Status Registers */ 62 #define LAN9118_ID_REV 0x50 /* Chip ID and Revision */ 63 #define LAN9118_ID_REV_ID(x) (((x) >> 16) & 0xffff) 64 #define LAN9118_ID_REV_REV(x) ((x) & 0xffff) 65 #define LAN9118_IRQ_CFG 0x54 /* Main Interrupt Configuration */ 66 #define LAN9118_IRQ_CFG_INT_DEAS(t) ((t) << 24) /* Intr Deassert Interval */ 67 #define LAN9118_IRQ_CFG_INT_DEAS_CLR (1 << 14) /* Intr Deass Intrval clr */ 68 #define LAN9118_IRQ_CFG_INT_DEAS_STS (1 << 13) /* Intr Deassert Status */ 69 #define LAN9118_IRQ_CFG_IRQ_INT (1 << 12) /* Master Interrupt */ 70 #define LAN9118_IRQ_CFG_IRQ_EN (1 << 8) /* IRQ Enable */ 71 #define LAN9118_IRQ_CFG_IRQ_POL (1 << 4) /* IRQ Polarity */ 72 #define LAN9118_IRQ_CFG_IRQ_TYPE (1 << 0) /* IRQ Buffer Type */ 73 #define LAN9118_INT_STS 0x58 /* Interrupt Status */ 74 #define LAN9118_INT_EN 0x5c /* Interrupt Enable Register */ 75 #define LAN9118_INT_SW_INT (1 << 31) /* Software Interrupt */ 76 #define LAN9118_INT_TXSTOP_INT (1 << 25) /* TX Stopped */ 77 #define LAN9118_INT_RXSTOP_INT (1 << 24) /* RX Stopped */ 78 #define LAN9118_INT_RXDFH_INT (1 << 23) /* RX Drppd Frm Cnt Halfway */ 79 #define LAN9118_INT_TX_IOC (1 << 21) /* TX IOC Interrupt */ 80 #define LAN9118_INT_RXD_INT (1 << 20) /* RX DMA Interrupt */ 81 #define LAN9118_INT_GPT_INT (1 << 19) /* GP Timer */ 82 #define LAN9118_INT_PHY_INT (1 << 18) /* PHY */ 83 #define LAN9118_INT_PME_INT (1 << 17) /* Power Management Event */ 84 #define LAN9118_INT_TXSO (1 << 16) /* TX Status FIFO Overflow */ 85 #define LAN9118_INT_RWT (1 << 15) /* Rcv Watchdog Time-out */ 86 #define LAN9118_INT_RXE (1 << 14) /* Receive Error */ 87 #define LAN9118_INT_TXE (1 << 13) /* Transmitter Error */ 88 #define LAN9118_INT_TDFO (1 << 10) /* TX Data FIFO Overrun */ 89 #define LAN9118_INT_TDFA (1 << 9) /* TX Data FIFO Available */ 90 #define LAN9118_INT_TSFF (1 << 8) /* TX Status FIFO Full */ 91 #define LAN9118_INT_TSFL (1 << 7) /* TX Status FIFO Level */ 92 #define LAN9118_INT_RXDF_INT (1 << 6) /* RX Dropped Frame Intr */ 93 #define LAN9118_INT_RSFF (1 << 4) /* RX Status FIFO Full */ 94 #define LAN9118_INT_RSFL (1 << 3) /* RX Status FIFO Level */ 95 #define LAN9118_INT_GPIOX_INT(x) (1 << (x)) /* GPIO[2:0] */ 96 /* 0x60 Reserved for future use */ 97 #define LAN9118_BYTE_TEST 0x64 /* Read-only byte order testing reg */ 98 #define LAN9118_BYTE_TEST_VALUE 0x87654321 99 #define LAN9118_FIFO_INT 0x68 /* FIFO Level Interrupt */ 100 #define LAN9118_FIFO_INT_TXDAL(x) ((x) << 24) /* TX Data Available Lvl */ 101 #define LAN9118_FIFO_INT_TXSL(x) ((x) << 16) /* TX Status Level */ 102 #define LAN9118_FIFO_INT_RXSL(x) ((x) << 0) /* RX Status Level */ 103 #define LAN9118_RX_CFG 0x6c /* Receive Configuration */ 104 #define LAN9118_RX_CFG_RXEA_4B (0 << 30) /* RX End Alignment: 4 Byte */ 105 #define LAN9118_RX_CFG_RXEA_16B (1 << 30) /* 16 Byte */ 106 #define LAN9118_RX_CFG_RXEA_32B (2 << 30) /* 32 Byte */ 107 #define LAN9118_RX_CFG_RX_DMA_CNT(x) ((x) << 16) /* RX DMA Count */ 108 #define LAN9118_RX_CFG_RX_DUMP (1 << 15) /* Force RX Discard */ 109 #define LAN9118_RX_CFG_RXDOFF(x) ((x) << 8) /* RX Data Offset */ 110 #define LAN9118_TX_CFG 0x70 /* Transmit Configuration */ 111 #define LAN9118_TX_CFG_TXS_DUMP (1 << 15) /* Force TX Status Discard */ 112 #define LAN9118_TX_CFG_TXD_DUMP (1 << 14) /* Force TX Data Discard */ 113 #define LAN9118_TX_CFG_TXSAO (1 << 2) /* TX Status Allow Overrun */ 114 #define LAN9118_TX_CFG_TX_ON (1 << 1) /* Transmitter Enable */ 115 #define LAN9118_TX_CFG_STOP_TX (1 << 0) /* Stop Transmitter */ 116 #define LAN9118_HW_CFG 0x74 /* Hardware Configuration */ 117 #define LAN9118_HW_CFG_MBO (1 << 20)/* Must Be One */ 118 #define LAN9118_HW_CFG_TX_FIF_MASK (0xf << 16) /* TX FIFO Size */ 119 #define LAN9118_HW_CFG_TX_FIF_SZ(sz) ((sz) << 16) 120 #define LAN9118_HW_CFG_PHY_CLK_SEL_MASK (3 << 5) /* PHY Clock Select */ 121 #define LAN9118_HW_CFG_PHY_CLK_SEL_IPHY (0 << 5) /* Internal PHY */ 122 #define LAN9118_HW_CFG_PHY_CLK_SEL_EMII (1 << 5) /* External MII Port */ 123 #define LAN9118_HW_CFG_PHY_CLK_SEL_CD (2 << 5) /* Clock Disabled */ 124 #define LAN9118_HW_CFG_SMI_SEL (1 << 4) /* Serial Mgmt Interface Sel */ 125 #define LAN9118_HW_CFG_EXT_PHY_DET (1 << 3) /* External PHY Detect */ 126 #define LAN9118_HW_CFG_EXT_PHY_EN (1 << 2) /* External PHY Enable */ 127 #define LAN9118_HW_CFG_SRST_TO (1 << 1) /* Soft Reset Timeout */ 128 #define LAN9118_HW_CFG_SRST (1 << 0) /* Soft Reset */ 129 #define LAN9118_RX_DP_CTL 0x78 /* RX Datapath Control */ 130 #define LAN9118_RX_DP_CTL_RX_FFWD (1 << 31)/* RX Data FIFO Fast Forward */ 131 #define LAN9118_RX_FIFO_INF 0x7c /* Receive FIFO Information */ 132 #define LAN9118_RX_FIFO_INF_RXSUSED(x) (((x) >> 16) & 0xff) /*Sts Used Space*/ 133 #define LAN9118_RX_FIFO_INF_RXDUSED(x) ((x) & 0xffff) /*Data FIFO Used Space*/ 134 #define LAN9118_TX_FIFO_INF 0x80 /* Transmit FIFO Information */ 135 #define LAN9118_TX_FIFO_INF_TXSUSED(x) (((x) >> 16) & 0xff) /*Sts Used Space*/ 136 #define LAN9118_TX_FIFO_INF_TDFREE(x) ((x) & 0xffff) /*Data FIFO Free Space*/ 137 #define LAN9118_PMT_CTRL 0x84 /* Power Management Control */ 138 #define LAN9118_PMT_CTRL_PM_MODE_MASK (3 << 12) 139 #define LAN9118_PMT_CTRL_PM_MODE_D0 (0 << 12) 140 #define LAN9118_PMT_CTRL_PM_MODE_D1 (1 << 12) 141 #define LAN9118_PMT_CTRL_PM_MODE_D2 (2 << 12) 142 #define LAN9118_PMT_CTRL_PHY_RST (1 << 10) /* PHY Reset */ 143 #define LAN9118_PMT_CTRL_WOL_EN (1 << 9) /* Wake-On-LAN Enable */ 144 #define LAN9118_PMT_CTRL_ED_EN (1 << 8) /* Energy-Detect Enable */ 145 #define LAN9118_PMT_CTRL_PME_TYPE (1 << 6) /* PME Buffer Type */ 146 #define LAN9118_PMT_CTRL_WUPS_NWUED (0 << 4) /* WAKE-UP Status: No Event */ 147 #define LAN9118_PMT_CTRL_WUPS_ED (1 << 4) /* WAKE-UP Status: Energy */ 148 #define LAN9118_PMT_CTRL_WUPS_WUD (2 << 4) /* WAKE-UP Status: Wake-up */ 149 #define LAN9118_PMT_CTRL_PME_IND (1 << 3) /* PME indication */ 150 #define LAN9118_PMT_CTRL_PME_POL (1 << 2) /* PME Polarity */ 151 #define LAN9118_PMT_CTRL_PME_EN (1 << 1) /* PME Enable */ 152 #define LAN9118_PMT_CTRL_READY (1 << 0) /* Device Ready */ 153 #define LAN9118_GPIO_CFG 0x88 /* General Purpose IO Configuration */ 154 #define LAN9118_GPIO_CFG_LEDX_EN(x) (1 << ((x) + 28)) /* LED[3:1] enable */ 155 #define LAN9118_GPIO_CFG_GPIO_INT_POL(p) (1 << ((p) + 24)) /* Intr Polarity */ 156 #define LAN9118_GPIO_CFG_EEPR_EN (7 << 20) /* EEPROM Enable */ 157 #define LAN9118_GPIO_CFG_GPIOBUFN(n) (1 << ((n) + 16)) /* Buffer Type */ 158 #define LAN9118_GPIO_CFG_GPDIRN(n) (1 << ((n) + 8)) /* Direction */ 159 #define LAN9118_GPIO_CFG_GPODN(n) (1 << (n)) /* GPIO Data (3,4 is WO) */ 160 #define LAN9118_GPT_CFG 0x8c /* General Purpose Timer Config */ 161 #define LAN9118_GPT_CNT 0x90 /* General Purpose Timer Count */ 162 /* 0x94 Reserved for future use */ 163 #define LAN9118_WORD_SWAP 0x98 /* WORD SWAP Register */ 164 #define LAN9118_FREE_RUN 0x9c /* Free Run Counter */ 165 #define LAN9118_RX_DROP 0xa0 /* RX Drop Frame Counter */ 166 #define LAN9118_MAC_CSR_CMD 0xa4 /* MAC CSR Synchronizer Command */ 167 #define LAN9118_MAC_CSR_CMD_BUSY (1 << 31) 168 #define LAN9118_MAC_CSR_CMD_W (0 << 30) 169 #define LAN9118_MAC_CSR_CMD_R (1 << 30) 170 #define LAN9118_MAC_CSR_CMD_ADDRESS(a) ((a) & 0xff) 171 #define LAN9118_MAC_CSR_DATA 0xa8 /* MAC CSR Synchronizer Data */ 172 #define LAN9118_AFC_CFG 0xac /* Automatic Flow Control Config */ 173 #define LAN9118_AFC_CFG_AFC_HI(x) ((x) << 16) 174 #define LAN9118_AFC_CFG_AFC_LO(x) ((x) << 8) 175 #define LAN9118_AFC_CFG_BACK_DUR(x) ((x) << 4) 176 #define LAN9118_AFC_CFG_FCMULT (1 << 3) /* Flow Control on Multicast */ 177 #define LAN9118_AFC_CFG_FCBRD (1 << 2) /* Flow Control on Broadcast */ 178 #define LAN9118_AFC_CFG_FCADD (1 << 1) /* Flow Control on Addr Dec */ 179 #define LAN9118_AFC_CFG_FCANY (1 << 0) /* Flow Control on Any Frame */ 180 #define LAN9118_E2P_CMD 0xb0 /* EEPROM command */ 181 #define LAN9118_E2P_CMD_EPCB (1 << 31) /* EPC Busy */ 182 #define LAN9118_E2P_CMD_EPCC_READ (0 << 28) /* EPC Command: READ */ 183 #define LAN9118_E2P_CMD_EPCC_EWDS (1 << 28) /* EWDS */ 184 #define LAN9118_E2P_CMD_EPCC_EWEN (2 << 28) /* EWEN */ 185 #define LAN9118_E2P_CMD_EPCC_WRITE (3 << 28) /* WRITE */ 186 #define LAN9118_E2P_CMD_EPCC_WRAL (4 << 28) /* WRAL */ 187 #define LAN9118_E2P_CMD_EPCC_ERASE (5 << 28) /* ERASE */ 188 #define LAN9118_E2P_CMD_EPCC_ERAL (6 << 28) /* ERAL */ 189 #define LAN9118_E2P_CMD_EPCC_RELOAD (7 << 28) /* Reload */ 190 #define LAN9118_E2P_CMD_EPCTO (1 << 9) /* EPC Time-out */ 191 #define LAN9118_E2P_CMD_MACAL (1 << 8) /* MAC Address Loaded */ 192 #define LAN9118_E2P_CMD_EPCA(a) ((a) & 0xff) /* EPC Address */ 193 #define LAN9118_E2P_DATA 0xb4 /* EEPROM Data */ 194 /* 0xb8 - 0xfc Reserved for future use */ 195 196 /* MAC Control and Status Registers */ 197 #define LAN9118_MAC_CR 0x1 /* MAC Control Register */ 198 #define LAN9118_MAC_CR_RXALL (1 << 31) /* Receive All Mode */ 199 #define LAN9118_MAC_CR_RCVOWN (1 << 23) /* Disable Receive Own */ 200 #define LAN9118_MAC_CR_LOOPBK (1 << 21) /* Loopback operation Mode */ 201 #define LAN9118_MAC_CR_FDPX (1 << 20) /* Full Duplex Mode */ 202 #define LAN9118_MAC_CR_MCPAS (1 << 19) /* Pass All Multicast */ 203 #define LAN9118_MAC_CR_PRMS (1 << 18) /* Promiscuous Mode */ 204 #define LAN9118_MAC_CR_INVFILT (1 << 17) /* Inverse filtering */ 205 #define LAN9118_MAC_CR_PASSBAD (1 << 16) /* Pass Bad Frames */ 206 #define LAN9118_MAC_CR_HO (1 << 15) /* Hash Only Filtering mode */ 207 #define LAN9118_MAC_CR_HPFILT (1 << 13) /* Hash/Perfect Flt Mode */ 208 #define LAN9118_MAC_CR_LCOLL (1 << 12) /* Late Collision Control */ 209 #define LAN9118_MAC_CR_BCAST (1 << 11) /* Disable Broadcast Frms */ 210 #define LAN9118_MAC_CR_DISRTY (1 << 10) /* Disable Retry */ 211 #define LAN9118_MAC_CR_PADSTR (1 << 8) /* Automatic Pad String */ 212 #define LAN9118_MAC_CR_BOLMT (1 << 7) /* BackOff Limit */ 213 #define LAN9118_MAC_CR_DFCHK (1 << 5) /* Deferral Check */ 214 #define LAN9118_MAC_CR_TXEN (1 << 3) /* Transmitter enable */ 215 #define LAN9118_MAC_CR_RXEN (1 << 2) /* Receiver enable */ 216 #define LAN9118_ADDRH 0x2 /* MAC Address High */ 217 #define LAN9118_ADDRL 0x3 /* MAC Address Low */ 218 #define LAN9118_HASHH 0x4 /* Multicast Hash Table High */ 219 #define LAN9118_HASHL 0x5 /* Multicast Hash Table Low */ 220 #define LAN9118_MII_ACC 0x6 /* MII Access */ 221 #define LAN9118_MII_ACC_PHYA(a) ((a) << 11) /* PHY Address */ 222 #define LAN9118_MII_ACC_MIIRINDA(i) ((i) << 6) /* MII Register Index */ 223 #define LAN9118_MII_ACC_MIIWNR (1 << 1) /* MII Write */ 224 #define LAN9118_MII_ACC_MIIBZY (1 << 0) /* MII Busy */ 225 #define LAN9118_MII_DATA 0x7 /* MII Data */ 226 #define LAN9118_FLOW 0x8 /* Flow Control */ 227 #define LAN9118_FLOW_FCPT(t) ((t) << 16) /* Pause Time */ 228 #define LAN9118_FLOW_FCPASS (1 << 2) /* Pass Control Frame */ 229 #define LAN9118_FLOW_FCEN (1 << 1) /* Flow Control Enable */ 230 #define LAN9118_FLOW_FCBUSY (1 << 0) /* Flow Control Busy */ 231 #define LAN9118_VLAN1 0x9 /* VLAN1 Tag */ 232 #define LAN9118_VLAN2 0xa /* VLAN2 Tag */ 233 #define LAN9118_WUFF 0xb /* Wake-up Frame Filter */ 234 #define LAN9118_WUCSR 0xc /* Wake-up Control and Status */ 235 236 /* PHY Registers */ 237 #define LAN9118_MCSR 0x11 /* Mode Control/Status Register */ 238 #define LAN9118_MCSR_EDPWRDOWN (1 << 13) /* Energy Detect Power Down */ 239 #define LAN9118_MCSR_ENERGYON (1 << 1) 240 #define LAN9118_SMR 0x12 /* Special Modes Register */ 241 #define LAN9118_SMR_PHYAD (0x01) 242 #define LAN9118_SCSI 0x1b /* Special Control/Status Indications */ 243 #define LAN9118_SCSI_VCOOFF_LP (1 << 10) 244 #define LAN9118_SCSI_XPOL (1 << 4) /* Polarity state */ 245 #define LAN9118_ISR 0x1d /* Interrupt Source Register */ 246 #define LAN9118_IMR 0x1e /* Interrupt Mask Register */ 247 #define LAN9118_I_ENERGYON (1 << 7) 248 #define LAN9118_I_AUTONEGOCOMPL (1 << 6) 249 #define LAN9118_I_REMOTEFAULT (1 << 5) 250 #define LAN9118_I_LINKDOWN (1 << 4) 251 #define LAN9118_I_AUTONEGOLPACK (1 << 3) /* AutoNego LP Acknowledge */ 252 #define LAN9118_I_PDF (1 << 2) /* Parallel Detection Fault */ 253 #define LAN9118_I_AUTONEGOPR (1 << 1) /* AutoNego Page Received */ 254 #define LAN9118_PHYSCSR 0x1f /* PHY Special Control/Status Reg */ 255 #define LAN9118_PHYSCSR_AUTODONE (1 << 12) /* AutoNego done indication */ 256 #define LAN9118_PHYSCSR_SI_10 (1 << 2) /* Speed Indication */ 257 #define LAN9118_PHYSCSR_SI_100 (2 << 2) 258 #define LAN9118_PHYSCSR_SI_FDX (4 << 2) 259 260 261 /* TX Command 'A' Format */ 262 #define LAN9118_TXC_A_IC (1 << 31) /* Interrupt on Completion */ 263 #define LAN9118_TXC_A_BEA_4B (0 << 24) /* Buffer End Alignment: 4B */ 264 #define LAN9118_TXC_A_BEA_16B (1 << 24) /* 16B */ 265 #define LAN9118_TXC_A_BEA_32B (2 << 24) /* 32B */ 266 #define LAN9118_TXC_A_DSO(x) ((x) << 16) /*Data Start Offset: bytes*/ 267 #define LAN9118_TXC_A_FS (1 << 13) /* First Segment */ 268 #define LAN9118_TXC_A_LS (1 << 12) /* Last Segment */ 269 #define LAN9118_TXC_A_BS(x) ((x) << 0) /* Buffer Size */ 270 271 /* TX Command 'B' Format */ 272 #define LAN9118_TXC_B_PT(x) ((x) << 16) /* Packet Tag */ 273 #define LAN9118_TXC_B_ACRCD (1 << 13) /* Add CRC Disable */ 274 #define LAN9118_TXC_B_DEFP (1 << 12) /* Dis Ether Frame Padding */ 275 #define LAN9118_TXC_B_PL(x) ((x) << 0) /* Packet Length */ 276 277 /* TX Status Format */ 278 #define LAN9118_TXS_PKTTAG(x) (((x) >> 16) & 0xff) /* Packet Tag */ 279 #define LAN9118_TXS_ES (1 << 15) /* Error Status */ 280 #define LAN9118_TXS_LOC (1 << 11) /* Loss Of Carrier */ 281 #define LAN9118_TXS_NC (1 << 10) /* No Carrier */ 282 #define LAN9118_TXS_LCOL (1 << 9) /* Late Collision */ 283 #define LAN9118_TXS_ECOL (1 << 8) /* Excessive Collision*/ 284 #define LAN9118_TXS_COLCNT(x) (((x) >> 3) & 0xf) /* Collision Count */ 285 #define LAN9118_TXS_ED (1 << 2) /* Excessive Deferral */ 286 #define LAN9118_TXS_DEFERRED (1 << 0) /* Deferred */ 287 288 /* RX Status Format */ 289 #define LAN9118_RXS_FILTFAIL (1 << 30) /* Filtering Fail */ 290 #define LAN9118_RXS_PKTLEN(x) (((x) >> 16) & 0x3fff) /* Packet Len */ 291 #define LAN9118_RXS_ES (1 << 15) /* Error Status */ 292 #define LAN9118_RXS_BCF (1 << 13) /* Broadcast Frame */ 293 #define LAN9118_RXS_LENERR (1 << 12) /* Length Error */ 294 #define LAN9118_RXS_RUNTF (1 << 11) /* Runt Frame */ 295 #define LAN9118_RXS_MCF (1 << 10) /* Multicast Frame */ 296 #define LAN9118_RXS_FTL (1 << 7) /* Frame Too Long */ 297 #define LAN9118_RXS_COLS (1 << 6) /* Collision Seen */ 298 #define LAN9118_RXS_FT (1 << 5) /* Frame Type */ 299 #define LAN9118_RXS_RWTO (1 << 4) /* Rcv Watchdog time-out */ 300 #define LAN9118_RXS_MIIERR (1 << 3) /* MII Error */ 301 #define LAN9118_RXS_DBIT (1 << 2) /* Drabbling Bit */ 302 #define LAN9118_RXS_CRCERR (1 << 1) /* CRC Error */ 303 304 #endif /* _LAN9118REG_H_ */ 305
Indexes created Sat Sep 20 22:09:52 GMT 2025