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      1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
      2  * All Rights Reserved.
      3  *
      4  * Permission is hereby granted, free of charge, to any person obtaining a
      5  * copy of this software and associated documentation files (the
      6  * "Software"), to deal in the Software without restriction, including
      7  * without limitation the rights to use, copy, modify, merge, publish,
      8  * distribute, sub license, and/or sell copies of the Software, and to
      9  * permit persons to whom the Software is furnished to do so, subject to
     10  * the following conditions:
     11  *
     12  * The above copyright notice and this permission notice (including the
     13  * next paragraph) shall be included in all copies or substantial portions
     14  * of the Software.
     15  *
     16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
     17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
     18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
     19  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
     20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
     21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
     22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
     23  */
     24 
     25 #ifndef _I915_REG_H_
     26 #define _I915_REG_H_
     27 
     28 /*
     29  * The Bridge device's PCI config space has information about the
     30  * fb aperture size and the amount of pre-reserved memory.
     31  */
     32 #define INTEL_GMCH_CTRL		0x52
     33 #define INTEL_GMCH_ENABLED	0x4
     34 #define INTEL_GMCH_MEM_MASK	0x1
     35 #define INTEL_GMCH_MEM_64M	0x1
     36 #define INTEL_GMCH_MEM_128M	0
     37 
     38 #define INTEL_855_GMCH_GMS_MASK		(0x7 << 4)
     39 #define INTEL_855_GMCH_GMS_DISABLED	(0x0 << 4)
     40 #define INTEL_855_GMCH_GMS_STOLEN_1M	(0x1 << 4)
     41 #define INTEL_855_GMCH_GMS_STOLEN_4M	(0x2 << 4)
     42 #define INTEL_855_GMCH_GMS_STOLEN_8M	(0x3 << 4)
     43 #define INTEL_855_GMCH_GMS_STOLEN_16M	(0x4 << 4)
     44 #define INTEL_855_GMCH_GMS_STOLEN_32M	(0x5 << 4)
     45 
     46 #define INTEL_915G_GMCH_GMS_STOLEN_48M	(0x6 << 4)
     47 #define INTEL_915G_GMCH_GMS_STOLEN_64M	(0x7 << 4)
     48 
     49 /* PCI config space */
     50 
     51 #define HPLLCC	0xc0 /* 855 only */
     52 #define   GC_CLOCK_CONTROL_MASK		(3 << 0)
     53 #define   GC_CLOCK_133_200		(0 << 0)
     54 #define   GC_CLOCK_100_200		(1 << 0)
     55 #define   GC_CLOCK_100_133		(2 << 0)
     56 #define   GC_CLOCK_166_250		(3 << 0)
     57 #define GCFGC	0xf0 /* 915+ only */
     58 #define   GC_LOW_FREQUENCY_ENABLE	(1 << 7)
     59 #define   GC_DISPLAY_CLOCK_190_200_MHZ	(0 << 4)
     60 #define   GC_DISPLAY_CLOCK_333_MHZ	(4 << 4)
     61 #define   GC_DISPLAY_CLOCK_MASK		(7 << 4)
     62 #define LBB	0xf4
     63 
     64 /* VGA stuff */
     65 
     66 #define VGA_ST01_MDA 0x3ba
     67 #define VGA_ST01_CGA 0x3da
     68 
     69 #define VGA_MSR_WRITE 0x3c2
     70 #define VGA_MSR_READ 0x3cc
     71 #define   VGA_MSR_MEM_EN (1<<1)
     72 #define   VGA_MSR_CGA_MODE (1<<0)
     73 
     74 #define VGA_SR_INDEX 0x3c4
     75 #define VGA_SR_DATA 0x3c5
     76 
     77 #define VGA_AR_INDEX 0x3c0
     78 #define   VGA_AR_VID_EN (1<<5)
     79 #define VGA_AR_DATA_WRITE 0x3c0
     80 #define VGA_AR_DATA_READ 0x3c1
     81 
     82 #define VGA_GR_INDEX 0x3ce
     83 #define VGA_GR_DATA 0x3cf
     84 /* GR05 */
     85 #define   VGA_GR_MEM_READ_MODE_SHIFT 3
     86 #define     VGA_GR_MEM_READ_MODE_PLANE 1
     87 /* GR06 */
     88 #define   VGA_GR_MEM_MODE_MASK 0xc
     89 #define   VGA_GR_MEM_MODE_SHIFT 2
     90 #define   VGA_GR_MEM_A0000_AFFFF 0
     91 #define   VGA_GR_MEM_A0000_BFFFF 1
     92 #define   VGA_GR_MEM_B0000_B7FFF 2
     93 #define   VGA_GR_MEM_B0000_BFFFF 3
     94 
     95 #define VGA_DACMASK 0x3c6
     96 #define VGA_DACRX 0x3c7
     97 #define VGA_DACWX 0x3c8
     98 #define VGA_DACDATA 0x3c9
     99 
    100 #define VGA_CR_INDEX_MDA 0x3b4
    101 #define VGA_CR_DATA_MDA 0x3b5
    102 #define VGA_CR_INDEX_CGA 0x3d4
    103 #define VGA_CR_DATA_CGA 0x3d5
    104 
    105 /*
    106  * Memory interface instructions used by the kernel
    107  */
    108 #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
    109 
    110 #define MI_NOOP			MI_INSTR(0, 0)
    111 #define MI_USER_INTERRUPT	MI_INSTR(0x02, 0)
    112 #define MI_WAIT_FOR_EVENT       MI_INSTR(0x03, 0)
    113 #define   MI_WAIT_FOR_PLANE_B_FLIP      (1<<6)
    114 #define   MI_WAIT_FOR_PLANE_A_FLIP      (1<<2)
    115 #define   MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
    116 #define MI_FLUSH		MI_INSTR(0x04, 0)
    117 #define   MI_READ_FLUSH		(1 << 0)
    118 #define   MI_EXE_FLUSH		(1 << 1)
    119 #define   MI_NO_WRITE_FLUSH	(1 << 2)
    120 #define   MI_SCENE_COUNT	(1 << 3) /* just increment scene count */
    121 #define   MI_END_SCENE		(1 << 4) /* flush binner and incr scene count */
    122 #define MI_BATCH_BUFFER_END	MI_INSTR(0x0a, 0)
    123 #define MI_REPORT_HEAD		MI_INSTR(0x07, 0)
    124 #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
    125 #define MI_STORE_DWORD_IMM	MI_INSTR(0x20, 1)
    126 #define   MI_MEM_VIRTUAL	(1 << 22) /* 965+ only */
    127 #define MI_STORE_DWORD_INDEX	MI_INSTR(0x21, 1)
    128 #define   MI_STORE_DWORD_INDEX_SHIFT 2
    129 #define MI_LOAD_REGISTER_IMM	MI_INSTR(0x22, 1)
    130 #define MI_BATCH_BUFFER		MI_INSTR(0x30, 1)
    131 #define   MI_BATCH_NON_SECURE	(1)
    132 #define   MI_BATCH_NON_SECURE_I965 (1<<8)
    133 #define MI_BATCH_BUFFER_START	MI_INSTR(0x31, 0)
    134 
    135 /*
    136  * 3D instructions used by the kernel
    137  */
    138 #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
    139 
    140 #define GFX_OP_RASTER_RULES    ((0x3<<29)|(0x7<<24))
    141 #define GFX_OP_SCISSOR         ((0x3<<29)|(0x1c<<24)|(0x10<<19))
    142 #define   SC_UPDATE_SCISSOR       (0x1<<1)
    143 #define   SC_ENABLE_MASK          (0x1<<0)
    144 #define   SC_ENABLE               (0x1<<0)
    145 #define GFX_OP_LOAD_INDIRECT   ((0x3<<29)|(0x1d<<24)|(0x7<<16))
    146 #define GFX_OP_SCISSOR_INFO    ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
    147 #define   SCI_YMIN_MASK      (0xffff<<16)
    148 #define   SCI_XMIN_MASK      (0xffff<<0)
    149 #define   SCI_YMAX_MASK      (0xffff<<16)
    150 #define   SCI_XMAX_MASK      (0xffff<<0)
    151 #define GFX_OP_SCISSOR_ENABLE	 ((0x3<<29)|(0x1c<<24)|(0x10<<19))
    152 #define GFX_OP_SCISSOR_RECT	 ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
    153 #define GFX_OP_COLOR_FACTOR      ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
    154 #define GFX_OP_STIPPLE           ((0x3<<29)|(0x1d<<24)|(0x83<<16))
    155 #define GFX_OP_MAP_INFO          ((0x3<<29)|(0x1d<<24)|0x4)
    156 #define GFX_OP_DESTBUFFER_VARS   ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
    157 #define GFX_OP_DESTBUFFER_INFO	 ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
    158 #define GFX_OP_DRAWRECT_INFO     ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
    159 #define GFX_OP_DRAWRECT_INFO_I965  ((0x7900<<16)|0x2)
    160 #define SRC_COPY_BLT_CMD                ((2<<29)|(0x43<<22)|4)
    161 #define XY_SRC_COPY_BLT_CMD		((2<<29)|(0x53<<22)|6)
    162 #define XY_MONO_SRC_COPY_IMM_BLT	((2<<29)|(0x71<<22)|5)
    163 #define XY_SRC_COPY_BLT_WRITE_ALPHA	(1<<21)
    164 #define XY_SRC_COPY_BLT_WRITE_RGB	(1<<20)
    165 #define   BLT_DEPTH_8			(0<<24)
    166 #define   BLT_DEPTH_16_565		(1<<24)
    167 #define   BLT_DEPTH_16_1555		(2<<24)
    168 #define   BLT_DEPTH_32			(3<<24)
    169 #define   BLT_ROP_GXCOPY		(0xcc<<16)
    170 #define XY_SRC_COPY_BLT_SRC_TILED	(1<<15) /* 965+ only */
    171 #define XY_SRC_COPY_BLT_DST_TILED	(1<<11) /* 965+ only */
    172 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
    173 #define   ASYNC_FLIP                (1<<22)
    174 #define   DISPLAY_PLANE_A           (0<<20)
    175 #define   DISPLAY_PLANE_B           (1<<20)
    176 
    177 /*
    178  * Instruction and interrupt control regs
    179  */
    180 
    181 #define PRB0_TAIL	0x02030
    182 #define PRB0_HEAD	0x02034
    183 #define PRB0_START	0x02038
    184 #define PRB0_CTL	0x0203c
    185 #define   TAIL_ADDR		0x001FFFF8
    186 #define   HEAD_WRAP_COUNT	0xFFE00000
    187 #define   HEAD_WRAP_ONE		0x00200000
    188 #define   HEAD_ADDR		0x001FFFFC
    189 #define   RING_NR_PAGES		0x001FF000
    190 #define   RING_REPORT_MASK	0x00000006
    191 #define   RING_REPORT_64K	0x00000002
    192 #define   RING_REPORT_128K	0x00000004
    193 #define   RING_NO_REPORT	0x00000000
    194 #define   RING_VALID_MASK	0x00000001
    195 #define   RING_VALID		0x00000001
    196 #define   RING_INVALID		0x00000000
    197 #define PRB1_TAIL	0x02040 /* 915+ only */
    198 #define PRB1_HEAD	0x02044 /* 915+ only */
    199 #define PRB1_START	0x02048 /* 915+ only */
    200 #define PRB1_CTL	0x0204c /* 915+ only */
    201 #define ACTHD_I965	0x02074
    202 #define HWS_PGA		0x02080
    203 #define HWS_ADDRESS_MASK	0xfffff000
    204 #define HWS_START_ADDRESS_SHIFT	4
    205 #define IPEIR		0x02088
    206 #define NOPID		0x02094
    207 #define HWSTAM		0x02098
    208 #define SCPD0		0x0209c /* 915+ only */
    209 #define IER		0x020a0
    210 #define IIR		0x020a4
    211 #define IMR		0x020a8
    212 #define ISR		0x020ac
    213 #define   I915_PIPE_CONTROL_NOTIFY_INTERRUPT		(1<<18)
    214 #define   I915_DISPLAY_PORT_INTERRUPT			(1<<17)
    215 #define   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT	(1<<15)
    216 #define   I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT	(1<<14)
    217 #define   I915_HWB_OOM_INTERRUPT			(1<<13)
    218 #define   I915_SYNC_STATUS_INTERRUPT			(1<<12)
    219 #define   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT	(1<<11)
    220 #define   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT	(1<<10)
    221 #define   I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT	(1<<9)
    222 #define   I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT	(1<<8)
    223 #define   I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT		(1<<7)
    224 #define   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT		(1<<6)
    225 #define   I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT		(1<<5)
    226 #define   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT		(1<<4)
    227 #define   I915_DEBUG_INTERRUPT				(1<<2)
    228 #define   I915_USER_INTERRUPT				(1<<1)
    229 #define   I915_ASLE_INTERRUPT				(1<<0)
    230 #define EIR		0x020b0
    231 #define EMR		0x020b4
    232 #define ESR		0x020b8
    233 #define INSTPM	        0x020c0
    234 #define ACTHD	        0x020c8
    235 #define FW_BLC		0x020d8
    236 #define FW_BLC_SELF	0x020e0 /* 915+ only */
    237 #define MI_ARB_STATE	0x020e4 /* 915+ only */
    238 #define CACHE_MODE_0	0x02120 /* 915+ only */
    239 #define   CM0_MASK_SHIFT          16
    240 #define   CM0_IZ_OPT_DISABLE      (1<<6)
    241 #define   CM0_ZR_OPT_DISABLE      (1<<5)
    242 #define   CM0_DEPTH_EVICT_DISABLE (1<<4)
    243 #define   CM0_COLOR_EVICT_DISABLE (1<<3)
    244 #define   CM0_DEPTH_WRITE_DISABLE (1<<1)
    245 #define   CM0_RC_OP_FLUSH_DISABLE (1<<0)
    246 #define GFX_FLSH_CNTL	0x02170 /* 915+ only */
    247 
    248 /*
    249  * Framebuffer compression (915+ only)
    250  */
    251 
    252 #define FBC_CFB_BASE		0x03200 /* 4k page aligned */
    253 #define FBC_LL_BASE		0x03204 /* 4k page aligned */
    254 #define FBC_CONTROL		0x03208
    255 #define   FBC_CTL_EN		(1<<31)
    256 #define   FBC_CTL_PERIODIC	(1<<30)
    257 #define   FBC_CTL_INTERVAL_SHIFT (16)
    258 #define   FBC_CTL_UNCOMPRESSIBLE (1<<14)
    259 #define   FBC_CTL_STRIDE_SHIFT	(5)
    260 #define   FBC_CTL_FENCENO	(1<<0)
    261 #define FBC_COMMAND		0x0320c
    262 #define   FBC_CMD_COMPRESS	(1<<0)
    263 #define FBC_STATUS		0x03210
    264 #define   FBC_STAT_COMPRESSING	(1<<31)
    265 #define   FBC_STAT_COMPRESSED	(1<<30)
    266 #define   FBC_STAT_MODIFIED	(1<<29)
    267 #define   FBC_STAT_CURRENT_LINE	(1<<0)
    268 #define FBC_CONTROL2		0x03214
    269 #define   FBC_CTL_FENCE_DBL	(0<<4)
    270 #define   FBC_CTL_IDLE_IMM	(0<<2)
    271 #define   FBC_CTL_IDLE_FULL	(1<<2)
    272 #define   FBC_CTL_IDLE_LINE	(2<<2)
    273 #define   FBC_CTL_IDLE_DEBUG	(3<<2)
    274 #define   FBC_CTL_CPU_FENCE	(1<<1)
    275 #define   FBC_CTL_PLANEA	(0<<0)
    276 #define   FBC_CTL_PLANEB	(1<<0)
    277 #define FBC_FENCE_OFF		0x0321b
    278 
    279 #define FBC_LL_SIZE		(1536)
    280 
    281 /*
    282  * GPIO regs
    283  */
    284 #define GPIOA			0x5010
    285 #define GPIOB			0x5014
    286 #define GPIOC			0x5018
    287 #define GPIOD			0x501c
    288 #define GPIOE			0x5020
    289 #define GPIOF			0x5024
    290 #define GPIOG			0x5028
    291 #define GPIOH			0x502c
    292 # define GPIO_CLOCK_DIR_MASK		(1 << 0)
    293 # define GPIO_CLOCK_DIR_IN		(0 << 1)
    294 # define GPIO_CLOCK_DIR_OUT		(1 << 1)
    295 # define GPIO_CLOCK_VAL_MASK		(1 << 2)
    296 # define GPIO_CLOCK_VAL_OUT		(1 << 3)
    297 # define GPIO_CLOCK_VAL_IN		(1 << 4)
    298 # define GPIO_CLOCK_PULLUP_DISABLE	(1 << 5)
    299 # define GPIO_DATA_DIR_MASK		(1 << 8)
    300 # define GPIO_DATA_DIR_IN		(0 << 9)
    301 # define GPIO_DATA_DIR_OUT		(1 << 9)
    302 # define GPIO_DATA_VAL_MASK		(1 << 10)
    303 # define GPIO_DATA_VAL_OUT		(1 << 11)
    304 # define GPIO_DATA_VAL_IN		(1 << 12)
    305 # define GPIO_DATA_PULLUP_DISABLE	(1 << 13)
    306 
    307 /*
    308  * Clock control & power management
    309  */
    310 
    311 #define VGA0	0x6000
    312 #define VGA1	0x6004
    313 #define VGA_PD	0x6010
    314 #define   VGA0_PD_P2_DIV_4	(1 << 7)
    315 #define   VGA0_PD_P1_DIV_2	(1 << 5)
    316 #define   VGA0_PD_P1_SHIFT	0
    317 #define   VGA0_PD_P1_MASK	(0x1f << 0)
    318 #define   VGA1_PD_P2_DIV_4	(1 << 15)
    319 #define   VGA1_PD_P1_DIV_2	(1 << 13)
    320 #define   VGA1_PD_P1_SHIFT	8
    321 #define   VGA1_PD_P1_MASK	(0x1f << 8)
    322 #define DPLL_A	0x06014
    323 #define DPLL_B	0x06018
    324 #define   DPLL_VCO_ENABLE		(1 << 31)
    325 #define   DPLL_DVO_HIGH_SPEED		(1 << 30)
    326 #define   DPLL_SYNCLOCK_ENABLE		(1 << 29)
    327 #define   DPLL_VGA_MODE_DIS		(1 << 28)
    328 #define   DPLLB_MODE_DAC_SERIAL		(1 << 26) /* i915 */
    329 #define   DPLLB_MODE_LVDS		(2 << 26) /* i915 */
    330 #define   DPLL_MODE_MASK		(3 << 26)
    331 #define   DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
    332 #define   DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
    333 #define   DPLLB_LVDS_P2_CLOCK_DIV_14	(0 << 24) /* i915 */
    334 #define   DPLLB_LVDS_P2_CLOCK_DIV_7	(1 << 24) /* i915 */
    335 #define   DPLL_P2_CLOCK_DIV_MASK	0x03000000 /* i915 */
    336 #define   DPLL_FPA01_P1_POST_DIV_MASK	0x00ff0000 /* i915 */
    337 #define   DPLL_FPA01_P1_POST_DIV_MASK_IGD	0x00ff8000 /* IGD */
    338 
    339 #define I915_FIFO_UNDERRUN_STATUS		(1UL<<31)
    340 #define I915_CRC_ERROR_ENABLE			(1UL<<29)
    341 #define I915_CRC_DONE_ENABLE			(1UL<<28)
    342 #define I915_GMBUS_EVENT_ENABLE			(1UL<<27)
    343 #define I915_VSYNC_INTERRUPT_ENABLE		(1UL<<25)
    344 #define I915_DISPLAY_LINE_COMPARE_ENABLE	(1UL<<24)
    345 #define I915_DPST_EVENT_ENABLE			(1UL<<23)
    346 #define I915_LEGACY_BLC_EVENT_ENABLE		(1UL<<22)
    347 #define I915_ODD_FIELD_INTERRUPT_ENABLE		(1UL<<21)
    348 #define I915_EVEN_FIELD_INTERRUPT_ENABLE	(1UL<<20)
    349 #define I915_START_VBLANK_INTERRUPT_ENABLE	(1UL<<18)	/* 965 or later */
    350 #define I915_VBLANK_INTERRUPT_ENABLE		(1UL<<17)
    351 #define I915_OVERLAY_UPDATED_ENABLE		(1UL<<16)
    352 #define I915_CRC_ERROR_INTERRUPT_STATUS		(1UL<<13)
    353 #define I915_CRC_DONE_INTERRUPT_STATUS		(1UL<<12)
    354 #define I915_GMBUS_INTERRUPT_STATUS		(1UL<<11)
    355 #define I915_VSYNC_INTERRUPT_STATUS		(1UL<<9)
    356 #define I915_DISPLAY_LINE_COMPARE_STATUS	(1UL<<8)
    357 #define I915_DPST_EVENT_STATUS			(1UL<<7)
    358 #define I915_LEGACY_BLC_EVENT_STATUS		(1UL<<6)
    359 #define I915_ODD_FIELD_INTERRUPT_STATUS		(1UL<<5)
    360 #define I915_EVEN_FIELD_INTERRUPT_STATUS	(1UL<<4)
    361 #define I915_START_VBLANK_INTERRUPT_STATUS	(1UL<<2)	/* 965 or later */
    362 #define I915_VBLANK_INTERRUPT_STATUS		(1UL<<1)
    363 #define I915_OVERLAY_UPDATED_STATUS		(1UL<<0)
    364 
    365 #define SRX_INDEX		0x3c4
    366 #define SRX_DATA		0x3c5
    367 #define SR01			1
    368 #define SR01_SCREEN_OFF		(1<<5)
    369 
    370 #define PPCR			0x61204
    371 #define PPCR_ON			(1<<0)
    372 
    373 #define DVOB			0x61140
    374 #define DVOB_ON			(1<<31)
    375 #define DVOC			0x61160
    376 #define DVOC_ON			(1<<31)
    377 #define LVDS			0x61180
    378 #define LVDS_ON			(1<<31)
    379 
    380 #define ADPA			0x61100
    381 #define ADPA_DPMS_MASK		(~(3<<10))
    382 #define ADPA_DPMS_ON		(0<<10)
    383 #define ADPA_DPMS_SUSPEND	(1<<10)
    384 #define ADPA_DPMS_STANDBY	(2<<10)
    385 #define ADPA_DPMS_OFF		(3<<10)
    386 
    387 #define RING_TAIL		0x00
    388 #define TAIL_ADDR		0x001FFFF8
    389 #define RING_HEAD		0x04
    390 #define HEAD_WRAP_COUNT		0xFFE00000
    391 #define HEAD_WRAP_ONE		0x00200000
    392 #define HEAD_ADDR		0x001FFFFC
    393 #define RING_START		0x08
    394 #define START_ADDR		0xFFFFF000
    395 #define RING_LEN		0x0C
    396 #define RING_NR_PAGES		0x001FF000
    397 #define RING_REPORT_MASK	0x00000006
    398 #define RING_REPORT_64K		0x00000002
    399 #define RING_REPORT_128K	0x00000004
    400 #define RING_NO_REPORT		0x00000000
    401 #define RING_VALID_MASK		0x00000001
    402 #define RING_VALID		0x00000001
    403 #define RING_INVALID		0x00000000
    404 
    405 /* Scratch pad debug 0 reg:
    406  */
    407 #define   DPLL_FPA01_P1_POST_DIV_MASK_I830	0x001f0000
    408 /*
    409  * The i830 generation, in LVDS mode, defines P1 as the bit number set within
    410  * this field (only one bit may be set).
    411  */
    412 #define   DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS	0x003f0000
    413 #define   DPLL_FPA01_P1_POST_DIV_SHIFT	16
    414 #define   DPLL_FPA01_P1_POST_DIV_SHIFT_IGD	15
    415 /* i830, required in DVO non-gang */
    416 #define   PLL_P2_DIVIDE_BY_4		(1 << 23)
    417 #define   PLL_P1_DIVIDE_BY_TWO		(1 << 21) /* i830 */
    418 #define   PLL_REF_INPUT_DREFCLK		(0 << 13)
    419 #define   PLL_REF_INPUT_TVCLKINA	(1 << 13) /* i830 */
    420 #define   PLL_REF_INPUT_TVCLKINBC	(2 << 13) /* SDVO TVCLKIN */
    421 #define   PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
    422 #define   PLL_REF_INPUT_MASK		(3 << 13)
    423 #define   PLL_LOAD_PULSE_PHASE_SHIFT		9
    424 /*
    425  * Parallel to Serial Load Pulse phase selection.
    426  * Selects the phase for the 10X DPLL clock for the PCIe
    427  * digital display port. The range is 4 to 13; 10 or more
    428  * is just a flip delay. The default is 6
    429  */
    430 #define   PLL_LOAD_PULSE_PHASE_MASK		(0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
    431 #define   DISPLAY_RATE_SELECT_FPA1		(1 << 8)
    432 /*
    433  * SDVO multiplier for 945G/GM. Not used on 965.
    434  */
    435 #define   SDVO_MULTIPLIER_MASK			0x000000ff
    436 #define   SDVO_MULTIPLIER_SHIFT_HIRES		4
    437 #define   SDVO_MULTIPLIER_SHIFT_VGA		0
    438 #define DPLL_A_MD 0x0601c /* 965+ only */
    439 /*
    440  * UDI pixel divider, controlling how many pixels are stuffed into a packet.
    441  *
    442  * Value is pixels minus 1.  Must be set to 1 pixel for SDVO.
    443  */
    444 #define   DPLL_MD_UDI_DIVIDER_MASK		0x3f000000
    445 #define   DPLL_MD_UDI_DIVIDER_SHIFT		24
    446 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
    447 #define   DPLL_MD_VGA_UDI_DIVIDER_MASK		0x003f0000
    448 #define   DPLL_MD_VGA_UDI_DIVIDER_SHIFT		16
    449 /*
    450  * SDVO/UDI pixel multiplier.
    451  *
    452  * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
    453  * clock rate is 10 times the DPLL clock.  At low resolution/refresh rate
    454  * modes, the bus rate would be below the limits, so SDVO allows for stuffing
    455  * dummy bytes in the datastream at an increased clock rate, with both sides of
    456  * the link knowing how many bytes are fill.
    457  *
    458  * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
    459  * rate to 130Mhz to get a bus rate of 1.30Ghz.  The DPLL clock rate would be
    460  * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
    461  * through an SDVO command.
    462  *
    463  * This register field has values of multiplication factor minus 1, with
    464  * a maximum multiplier of 5 for SDVO.
    465  */
    466 #define   DPLL_MD_UDI_MULTIPLIER_MASK		0x00003f00
    467 #define   DPLL_MD_UDI_MULTIPLIER_SHIFT		8
    468 /*
    469  * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
    470  * This best be set to the default value (3) or the CRT won't work. No,
    471  * I don't entirely understand what this does...
    472  */
    473 #define   DPLL_MD_VGA_UDI_MULTIPLIER_MASK	0x0000003f
    474 #define   DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT	0
    475 #define DPLL_B_MD 0x06020 /* 965+ only */
    476 #define FPA0	0x06040
    477 #define FPA1	0x06044
    478 #define FPB0	0x06048
    479 #define FPB1	0x0604c
    480 #define   FP_N_DIV_MASK		0x003f0000
    481 #define   FP_N_IGD_DIV_MASK	0x00ff0000
    482 #define   FP_N_DIV_SHIFT		16
    483 #define   FP_M1_DIV_MASK	0x00003f00
    484 #define   FP_M1_DIV_SHIFT		 8
    485 #define   FP_M2_DIV_MASK	0x0000003f
    486 #define   FP_M2_IGD_DIV_MASK	0x000000ff
    487 #define   FP_M2_DIV_SHIFT		 0
    488 #define DPLL_TEST	0x606c
    489 #define   DPLLB_TEST_SDVO_DIV_1		(0 << 22)
    490 #define   DPLLB_TEST_SDVO_DIV_2		(1 << 22)
    491 #define   DPLLB_TEST_SDVO_DIV_4		(2 << 22)
    492 #define   DPLLB_TEST_SDVO_DIV_MASK	(3 << 22)
    493 #define   DPLLB_TEST_N_BYPASS		(1 << 19)
    494 #define   DPLLB_TEST_M_BYPASS		(1 << 18)
    495 #define   DPLLB_INPUT_BUFFER_ENABLE	(1 << 16)
    496 #define   DPLLA_TEST_N_BYPASS		(1 << 3)
    497 #define   DPLLA_TEST_M_BYPASS		(1 << 2)
    498 #define   DPLLA_INPUT_BUFFER_ENABLE	(1 << 0)
    499 #define D_STATE		0x6104
    500 #define CG_2D_DIS	0x6200
    501 #define CG_3D_DIS	0x6204
    502 
    503 /*
    504  * Palette regs
    505  */
    506 
    507 #define PALETTE_A		0x0a000
    508 #define PALETTE_B		0x0a800
    509 
    510 /* MCH MMIO space */
    511 
    512 /*
    513  * MCHBAR mirror.
    514  *
    515  * This mirrors the MCHBAR MMIO space whose location is determined by
    516  * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
    517  * every way.  It is not accessible from the CP register read instructions.
    518  *
    519  */
    520 #define MCHBAR_MIRROR_BASE	0x10000
    521 
    522 /** 915-945 and GM965 MCH register controlling DRAM channel access */
    523 #define DCC			0x10200
    524 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL		(0 << 0)
    525 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC	(1 << 0)
    526 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED	(2 << 0)
    527 #define DCC_ADDRESSING_MODE_MASK			(3 << 0)
    528 #define DCC_CHANNEL_XOR_DISABLE				(1 << 10)
    529 
    530 /** 965 MCH register controlling DRAM channel configuration */
    531 #define C0DRB3			0x10206
    532 #define C1DRB3			0x10606
    533 
    534 /*
    535  * Overlay regs
    536  */
    537 
    538 #define OVADD			0x30000
    539 #define DOVSTA			0x30008
    540 #define OC_BUF			(0x3<<20)
    541 #define OGAMC5			0x30010
    542 #define OGAMC4			0x30014
    543 #define OGAMC3			0x30018
    544 #define OGAMC2			0x3001c
    545 #define OGAMC1			0x30020
    546 #define OGAMC0			0x30024
    547 
    548 /*
    549  * Display engine regs
    550  */
    551 
    552 /* Pipe A timing regs */
    553 #define HTOTAL_A	0x60000
    554 #define HBLANK_A	0x60004
    555 #define HSYNC_A		0x60008
    556 #define VTOTAL_A	0x6000c
    557 #define VBLANK_A	0x60010
    558 #define VSYNC_A		0x60014
    559 #define PIPEASRC	0x6001c
    560 #define BCLRPAT_A	0x60020
    561 
    562 /* Pipe B timing regs */
    563 #define HTOTAL_B	0x61000
    564 #define HBLANK_B	0x61004
    565 #define HSYNC_B		0x61008
    566 #define VTOTAL_B	0x6100c
    567 #define VBLANK_B	0x61010
    568 #define VSYNC_B		0x61014
    569 #define PIPEBSRC	0x6101c
    570 #define BCLRPAT_B	0x61020
    571 
    572 /* VGA port control */
    573 #define ADPA			0x61100
    574 #define   ADPA_DAC_ENABLE	(1<<31)
    575 #define   ADPA_DAC_DISABLE	0
    576 #define   ADPA_PIPE_SELECT_MASK	(1<<30)
    577 #define   ADPA_PIPE_A_SELECT	0
    578 #define   ADPA_PIPE_B_SELECT	(1<<30)
    579 #define   ADPA_USE_VGA_HVPOLARITY (1<<15)
    580 #define   ADPA_SETS_HVPOLARITY	0
    581 #define   ADPA_VSYNC_CNTL_DISABLE (1<<11)
    582 #define   ADPA_VSYNC_CNTL_ENABLE 0
    583 #define   ADPA_HSYNC_CNTL_DISABLE (1<<10)
    584 #define   ADPA_HSYNC_CNTL_ENABLE 0
    585 #define   ADPA_VSYNC_ACTIVE_HIGH (1<<4)
    586 #define   ADPA_VSYNC_ACTIVE_LOW	0
    587 #define   ADPA_HSYNC_ACTIVE_HIGH (1<<3)
    588 #define   ADPA_HSYNC_ACTIVE_LOW	0
    589 #define   ADPA_DPMS_MASK	(~(3<<10))
    590 #define   ADPA_DPMS_ON		(0<<10)
    591 #define   ADPA_DPMS_SUSPEND	(1<<10)
    592 #define   ADPA_DPMS_STANDBY	(2<<10)
    593 #define   ADPA_DPMS_OFF		(3<<10)
    594 
    595 /* Hotplug control (945+ only) */
    596 #define PORT_HOTPLUG_EN		0x61110
    597 #define   SDVOB_HOTPLUG_INT_EN			(1 << 26)
    598 #define   SDVOC_HOTPLUG_INT_EN			(1 << 25)
    599 #define   TV_HOTPLUG_INT_EN			(1 << 18)
    600 #define   CRT_HOTPLUG_INT_EN			(1 << 9)
    601 #define   CRT_HOTPLUG_FORCE_DETECT		(1 << 3)
    602 
    603 #define PORT_HOTPLUG_STAT	0x61114
    604 #define   CRT_HOTPLUG_INT_STATUS		(1 << 11)
    605 #define   TV_HOTPLUG_INT_STATUS			(1 << 10)
    606 #define   CRT_HOTPLUG_MONITOR_MASK		(3 << 8)
    607 #define   CRT_HOTPLUG_MONITOR_COLOR		(3 << 8)
    608 #define   CRT_HOTPLUG_MONITOR_MONO		(2 << 8)
    609 #define   CRT_HOTPLUG_MONITOR_NONE		(0 << 8)
    610 #define   SDVOC_HOTPLUG_INT_STATUS		(1 << 7)
    611 #define   SDVOB_HOTPLUG_INT_STATUS		(1 << 6)
    612 
    613 /* SDVO port control */
    614 #define SDVOB			0x61140
    615 #define SDVOC			0x61160
    616 #define   SDVO_ENABLE		(1 << 31)
    617 #define   SDVO_PIPE_B_SELECT	(1 << 30)
    618 #define   SDVO_STALL_SELECT	(1 << 29)
    619 #define   SDVO_INTERRUPT_ENABLE	(1 << 26)
    620 /**
    621  * 915G/GM SDVO pixel multiplier.
    622  *
    623  * Programmed value is multiplier - 1, up to 5x.
    624  *
    625  * \sa DPLL_MD_UDI_MULTIPLIER_MASK
    626  */
    627 #define   SDVO_PORT_MULTIPLY_MASK	(7 << 23)
    628 #define   SDVO_PORT_MULTIPLY_SHIFT		23
    629 #define   SDVO_PHASE_SELECT_MASK	(15 << 19)
    630 #define   SDVO_PHASE_SELECT_DEFAULT	(6 << 19)
    631 #define   SDVO_CLOCK_OUTPUT_INVERT	(1 << 18)
    632 #define   SDVOC_GANG_MODE		(1 << 16)
    633 #define   SDVO_BORDER_ENABLE		(1 << 7)
    634 #define   SDVOB_PCIE_CONCURRENCY	(1 << 3)
    635 #define   SDVO_DETECTED			(1 << 2)
    636 /* Bits to be preserved when writing */
    637 #define   SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26))
    638 #define   SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26))
    639 
    640 /* DVO port control */
    641 #define DVOA			0x61120
    642 #define DVOB			0x61140
    643 #define DVOC			0x61160
    644 #define   DVO_ENABLE			(1 << 31)
    645 #define   DVO_PIPE_B_SELECT		(1 << 30)
    646 #define   DVO_PIPE_STALL_UNUSED		(0 << 28)
    647 #define   DVO_PIPE_STALL		(1 << 28)
    648 #define   DVO_PIPE_STALL_TV		(2 << 28)
    649 #define   DVO_PIPE_STALL_MASK		(3 << 28)
    650 #define   DVO_USE_VGA_SYNC		(1 << 15)
    651 #define   DVO_DATA_ORDER_I740		(0 << 14)
    652 #define   DVO_DATA_ORDER_FP		(1 << 14)
    653 #define   DVO_VSYNC_DISABLE		(1 << 11)
    654 #define   DVO_HSYNC_DISABLE		(1 << 10)
    655 #define   DVO_VSYNC_TRISTATE		(1 << 9)
    656 #define   DVO_HSYNC_TRISTATE		(1 << 8)
    657 #define   DVO_BORDER_ENABLE		(1 << 7)
    658 #define   DVO_DATA_ORDER_GBRG		(1 << 6)
    659 #define   DVO_DATA_ORDER_RGGB		(0 << 6)
    660 #define   DVO_DATA_ORDER_GBRG_ERRATA	(0 << 6)
    661 #define   DVO_DATA_ORDER_RGGB_ERRATA	(1 << 6)
    662 #define   DVO_VSYNC_ACTIVE_HIGH		(1 << 4)
    663 #define   DVO_HSYNC_ACTIVE_HIGH		(1 << 3)
    664 #define   DVO_BLANK_ACTIVE_HIGH		(1 << 2)
    665 #define   DVO_OUTPUT_CSTATE_PIXELS	(1 << 1)	/* SDG only */
    666 #define   DVO_OUTPUT_SOURCE_SIZE_PIXELS	(1 << 0)	/* SDG only */
    667 #define   DVO_PRESERVE_MASK		(0x7<<24)
    668 #define DVOA_SRCDIM		0x61124
    669 #define DVOB_SRCDIM		0x61144
    670 #define DVOC_SRCDIM		0x61164
    671 #define   DVO_SRCDIM_HORIZONTAL_SHIFT	12
    672 #define   DVO_SRCDIM_VERTICAL_SHIFT	0
    673 
    674 /* LVDS port control */
    675 #define LVDS			0x61180
    676 /*
    677  * Enables the LVDS port.  This bit must be set before DPLLs are enabled, as
    678  * the DPLL semantics change when the LVDS is assigned to that pipe.
    679  */
    680 #define   LVDS_PORT_EN			(1 << 31)
    681 /* Selects pipe B for LVDS data.  Must be set on pre-965. */
    682 #define   LVDS_PIPEB_SELECT		(1 << 30)
    683 /*
    684  * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
    685  * pixel.
    686  */
    687 #define   LVDS_A0A2_CLKA_POWER_MASK	(3 << 8)
    688 #define   LVDS_A0A2_CLKA_POWER_DOWN	(0 << 8)
    689 #define   LVDS_A0A2_CLKA_POWER_UP	(3 << 8)
    690 /*
    691  * Controls the A3 data pair, which contains the additional LSBs for 24 bit
    692  * mode.  Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
    693  * on.
    694  */
    695 #define   LVDS_A3_POWER_MASK		(3 << 6)
    696 #define   LVDS_A3_POWER_DOWN		(0 << 6)
    697 #define   LVDS_A3_POWER_UP		(3 << 6)
    698 /*
    699  * Controls the CLKB pair.  This should only be set when LVDS_B0B3_POWER_UP
    700  * is set.
    701  */
    702 #define   LVDS_CLKB_POWER_MASK		(3 << 4)
    703 #define   LVDS_CLKB_POWER_DOWN		(0 << 4)
    704 #define   LVDS_CLKB_POWER_UP		(3 << 4)
    705 /*
    706  * Controls the B0-B3 data pairs.  This must be set to match the DPLL p2
    707  * setting for whether we are in dual-channel mode.  The B3 pair will
    708  * additionally only be powered up when LVDS_A3_POWER_UP is set.
    709  */
    710 #define   LVDS_B0B3_POWER_MASK		(3 << 2)
    711 #define   LVDS_B0B3_POWER_DOWN		(0 << 2)
    712 #define   LVDS_B0B3_POWER_UP		(3 << 2)
    713 
    714 /* Panel power sequencing */
    715 #define PP_STATUS	0x61200
    716 #define   PP_ON		(1 << 31)
    717 /*
    718  * Indicates that all dependencies of the panel are on:
    719  *
    720  * - PLL enabled
    721  * - pipe enabled
    722  * - LVDS/DVOB/DVOC on
    723  */
    724 #define   PP_READY		(1 << 30)
    725 #define   PP_SEQUENCE_NONE	(0 << 28)
    726 #define   PP_SEQUENCE_ON	(1 << 28)
    727 #define   PP_SEQUENCE_OFF	(2 << 28)
    728 #define   PP_SEQUENCE_MASK	0x30000000
    729 #define PP_CONTROL	0x61204
    730 #define   POWER_TARGET_ON	(1 << 0)
    731 #define PP_ON_DELAYS	0x61208
    732 #define PP_OFF_DELAYS	0x6120c
    733 #define PP_DIVISOR	0x61210
    734 
    735 /* Panel fitting */
    736 #define PFIT_CONTROL	0x61230
    737 #define   PFIT_ENABLE		(1 << 31)
    738 #define   PFIT_PIPE_MASK	(3 << 29)
    739 #define   PFIT_PIPE_SHIFT	29
    740 #define   VERT_INTERP_DISABLE	(0 << 10)
    741 #define   VERT_INTERP_BILINEAR	(1 << 10)
    742 #define   VERT_INTERP_MASK	(3 << 10)
    743 #define   VERT_AUTO_SCALE	(1 << 9)
    744 #define   HORIZ_INTERP_DISABLE	(0 << 6)
    745 #define   HORIZ_INTERP_BILINEAR	(1 << 6)
    746 #define   HORIZ_INTERP_MASK	(3 << 6)
    747 #define   HORIZ_AUTO_SCALE	(1 << 5)
    748 #define   PANEL_8TO6_DITHER_ENABLE (1 << 3)
    749 #define PFIT_PGM_RATIOS	0x61234
    750 #define   PFIT_VERT_SCALE_MASK			0xfff00000
    751 #define   PFIT_HORIZ_SCALE_MASK			0x0000fff0
    752 #define PFIT_AUTO_RATIOS 0x61238
    753 
    754 /* Backlight control */
    755 #define BLC_PWM_CTL		0x61254
    756 #define   BACKLIGHT_MODULATION_FREQ_SHIFT		(17)
    757 #define BLC_PWM_CTL2		0x61250 /* 965+ only */
    758 #define   BLM_COMBINATION_MODE (1 << 30)
    759 /*
    760  * This is the most significant 15 bits of the number of backlight cycles in a
    761  * complete cycle of the modulated backlight control.
    762  *
    763  * The actual value is this field multiplied by two.
    764  */
    765 #define   BACKLIGHT_MODULATION_FREQ_MASK		(0x7fff << 17)
    766 #define   BLM_LEGACY_MODE				(1 << 16)
    767 /*
    768  * This is the number of cycles out of the backlight modulation cycle for which
    769  * the backlight is on.
    770  *
    771  * This field must be no greater than the number of cycles in the complete
    772  * backlight modulation cycle.
    773  */
    774 #define   BACKLIGHT_DUTY_CYCLE_SHIFT		(0)
    775 #define   BACKLIGHT_DUTY_CYCLE_MASK		(0xffff)
    776 
    777 /* TV port control */
    778 #define TV_CTL			0x68000
    779 /** Enables the TV encoder */
    780 # define TV_ENC_ENABLE			(1 << 31)
    781 /** Sources the TV encoder input from pipe B instead of A. */
    782 # define TV_ENC_PIPEB_SELECT		(1 << 30)
    783 /** Outputs composite video (DAC A only) */
    784 # define TV_ENC_OUTPUT_COMPOSITE	(0 << 28)
    785 /** Outputs SVideo video (DAC B/C) */
    786 # define TV_ENC_OUTPUT_SVIDEO		(1 << 28)
    787 /** Outputs Component video (DAC A/B/C) */
    788 # define TV_ENC_OUTPUT_COMPONENT	(2 << 28)
    789 /** Outputs Composite and SVideo (DAC A/B/C) */
    790 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE	(3 << 28)
    791 # define TV_TRILEVEL_SYNC		(1 << 21)
    792 /** Enables slow sync generation (945GM only) */
    793 # define TV_SLOW_SYNC			(1 << 20)
    794 /** Selects 4x oversampling for 480i and 576p */
    795 # define TV_OVERSAMPLE_4X		(0 << 18)
    796 /** Selects 2x oversampling for 720p and 1080i */
    797 # define TV_OVERSAMPLE_2X		(1 << 18)
    798 /** Selects no oversampling for 1080p */
    799 # define TV_OVERSAMPLE_NONE		(2 << 18)
    800 /** Selects 8x oversampling */
    801 # define TV_OVERSAMPLE_8X		(3 << 18)
    802 /** Selects progressive mode rather than interlaced */
    803 # define TV_PROGRESSIVE			(1 << 17)
    804 /** Sets the colorburst to PAL mode.  Required for non-M PAL modes. */
    805 # define TV_PAL_BURST			(1 << 16)
    806 /** Field for setting delay of Y compared to C */
    807 # define TV_YC_SKEW_MASK		(7 << 12)
    808 /** Enables a fix for 480p/576p standard definition modes on the 915GM only */
    809 # define TV_ENC_SDP_FIX			(1 << 11)
    810 /**
    811  * Enables a fix for the 915GM only.
    812  *
    813  * Not sure what it does.
    814  */
    815 # define TV_ENC_C0_FIX			(1 << 10)
    816 /** Bits that must be preserved by software */
    817 # define TV_CTL_SAVE			((3 << 8) | (3 << 6))
    818 # define TV_FUSE_STATE_MASK		(3 << 4)
    819 /** Read-only state that reports all features enabled */
    820 # define TV_FUSE_STATE_ENABLED		(0 << 4)
    821 /** Read-only state that reports that Macrovision is disabled in hardware*/
    822 # define TV_FUSE_STATE_NO_MACROVISION	(1 << 4)
    823 /** Read-only state that reports that TV-out is disabled in hardware. */
    824 # define TV_FUSE_STATE_DISABLED		(2 << 4)
    825 /** Normal operation */
    826 # define TV_TEST_MODE_NORMAL		(0 << 0)
    827 /** Encoder test pattern 1 - combo pattern */
    828 # define TV_TEST_MODE_PATTERN_1		(1 << 0)
    829 /** Encoder test pattern 2 - full screen vertical 75% color bars */
    830 # define TV_TEST_MODE_PATTERN_2		(2 << 0)
    831 /** Encoder test pattern 3 - full screen horizontal 75% color bars */
    832 # define TV_TEST_MODE_PATTERN_3		(3 << 0)
    833 /** Encoder test pattern 4 - random noise */
    834 # define TV_TEST_MODE_PATTERN_4		(4 << 0)
    835 /** Encoder test pattern 5 - linear color ramps */
    836 # define TV_TEST_MODE_PATTERN_5		(5 << 0)
    837 /**
    838  * This test mode forces the DACs to 50% of full output.
    839  *
    840  * This is used for load detection in combination with TVDAC_SENSE_MASK
    841  */
    842 # define TV_TEST_MODE_MONITOR_DETECT	(7 << 0)
    843 # define TV_TEST_MODE_MASK		(7 << 0)
    844 
    845 #define TV_DAC			0x68004
    846 /**
    847  * Reports that DAC state change logic has reported change (RO).
    848  *
    849  * This gets cleared when TV_DAC_STATE_EN is cleared
    850 */
    851 # define TVDAC_STATE_CHG		(1 << 31)
    852 # define TVDAC_SENSE_MASK		(7 << 28)
    853 /** Reports that DAC A voltage is above the detect threshold */
    854 # define TVDAC_A_SENSE			(1 << 30)
    855 /** Reports that DAC B voltage is above the detect threshold */
    856 # define TVDAC_B_SENSE			(1 << 29)
    857 /** Reports that DAC C voltage is above the detect threshold */
    858 # define TVDAC_C_SENSE			(1 << 28)
    859 /**
    860  * Enables DAC state detection logic, for load-based TV detection.
    861  *
    862  * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
    863  * to off, for load detection to work.
    864  */
    865 # define TVDAC_STATE_CHG_EN		(1 << 27)
    866 /** Sets the DAC A sense value to high */
    867 # define TVDAC_A_SENSE_CTL		(1 << 26)
    868 /** Sets the DAC B sense value to high */
    869 # define TVDAC_B_SENSE_CTL		(1 << 25)
    870 /** Sets the DAC C sense value to high */
    871 # define TVDAC_C_SENSE_CTL		(1 << 24)
    872 /** Overrides the ENC_ENABLE and DAC voltage levels */
    873 # define DAC_CTL_OVERRIDE		(1 << 7)
    874 /** Sets the slew rate.  Must be preserved in software */
    875 # define ENC_TVDAC_SLEW_FAST		(1 << 6)
    876 # define DAC_A_1_3_V			(0 << 4)
    877 # define DAC_A_1_1_V			(1 << 4)
    878 # define DAC_A_0_7_V			(2 << 4)
    879 # define DAC_A_OFF			(3 << 4)
    880 # define DAC_B_1_3_V			(0 << 2)
    881 # define DAC_B_1_1_V			(1 << 2)
    882 # define DAC_B_0_7_V			(2 << 2)
    883 # define DAC_B_OFF			(3 << 2)
    884 # define DAC_C_1_3_V			(0 << 0)
    885 # define DAC_C_1_1_V			(1 << 0)
    886 # define DAC_C_0_7_V			(2 << 0)
    887 # define DAC_C_OFF			(3 << 0)
    888 
    889 /**
    890  * CSC coefficients are stored in a floating point format with 9 bits of
    891  * mantissa and 2 or 3 bits of exponent.  The exponent is represented as 2**-n,
    892  * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
    893  * -1 (0x3) being the only legal negative value.
    894  */
    895 #define TV_CSC_Y		0x68010
    896 # define TV_RY_MASK			0x07ff0000
    897 # define TV_RY_SHIFT			16
    898 # define TV_GY_MASK			0x00000fff
    899 # define TV_GY_SHIFT			0
    900 
    901 #define TV_CSC_Y2		0x68014
    902 # define TV_BY_MASK			0x07ff0000
    903 # define TV_BY_SHIFT			16
    904 /**
    905  * Y attenuation for component video.
    906  *
    907  * Stored in 1.9 fixed point.
    908  */
    909 # define TV_AY_MASK			0x000003ff
    910 # define TV_AY_SHIFT			0
    911 
    912 #define TV_CSC_U		0x68018
    913 # define TV_RU_MASK			0x07ff0000
    914 # define TV_RU_SHIFT			16
    915 # define TV_GU_MASK			0x000007ff
    916 # define TV_GU_SHIFT			0
    917 
    918 #define TV_CSC_U2		0x6801c
    919 # define TV_BU_MASK			0x07ff0000
    920 # define TV_BU_SHIFT			16
    921 /**
    922  * U attenuation for component video.
    923  *
    924  * Stored in 1.9 fixed point.
    925  */
    926 # define TV_AU_MASK			0x000003ff
    927 # define TV_AU_SHIFT			0
    928 
    929 #define TV_CSC_V		0x68020
    930 # define TV_RV_MASK			0x0fff0000
    931 # define TV_RV_SHIFT			16
    932 # define TV_GV_MASK			0x000007ff
    933 # define TV_GV_SHIFT			0
    934 
    935 #define TV_CSC_V2		0x68024
    936 # define TV_BV_MASK			0x07ff0000
    937 # define TV_BV_SHIFT			16
    938 /**
    939  * V attenuation for component video.
    940  *
    941  * Stored in 1.9 fixed point.
    942  */
    943 # define TV_AV_MASK			0x000007ff
    944 # define TV_AV_SHIFT			0
    945 
    946 #define TV_CLR_KNOBS		0x68028
    947 /** 2s-complement brightness adjustment */
    948 # define TV_BRIGHTNESS_MASK		0xff000000
    949 # define TV_BRIGHTNESS_SHIFT		24
    950 /** Contrast adjustment, as a 2.6 unsigned floating point number */
    951 # define TV_CONTRAST_MASK		0x00ff0000
    952 # define TV_CONTRAST_SHIFT		16
    953 /** Saturation adjustment, as a 2.6 unsigned floating point number */
    954 # define TV_SATURATION_MASK		0x0000ff00
    955 # define TV_SATURATION_SHIFT		8
    956 /** Hue adjustment, as an integer phase angle in degrees */
    957 # define TV_HUE_MASK			0x000000ff
    958 # define TV_HUE_SHIFT			0
    959 
    960 #define TV_CLR_LEVEL		0x6802c
    961 /** Controls the DAC level for black */
    962 # define TV_BLACK_LEVEL_MASK		0x01ff0000
    963 # define TV_BLACK_LEVEL_SHIFT		16
    964 /** Controls the DAC level for blanking */
    965 # define TV_BLANK_LEVEL_MASK		0x000001ff
    966 # define TV_BLANK_LEVEL_SHIFT		0
    967 
    968 #define TV_H_CTL_1		0x68030
    969 /** Number of pixels in the hsync. */
    970 # define TV_HSYNC_END_MASK		0x1fff0000
    971 # define TV_HSYNC_END_SHIFT		16
    972 /** Total number of pixels minus one in the line (display and blanking). */
    973 # define TV_HTOTAL_MASK			0x00001fff
    974 # define TV_HTOTAL_SHIFT		0
    975 
    976 #define TV_H_CTL_2		0x68034
    977 /** Enables the colorburst (needed for non-component color) */
    978 # define TV_BURST_ENA			(1 << 31)
    979 /** Offset of the colorburst from the start of hsync, in pixels minus one. */
    980 # define TV_HBURST_START_SHIFT		16
    981 # define TV_HBURST_START_MASK		0x1fff0000
    982 /** Length of the colorburst */
    983 # define TV_HBURST_LEN_SHIFT		0
    984 # define TV_HBURST_LEN_MASK		0x0001fff
    985 
    986 #define TV_H_CTL_3		0x68038
    987 /** End of hblank, measured in pixels minus one from start of hsync */
    988 # define TV_HBLANK_END_SHIFT		16
    989 # define TV_HBLANK_END_MASK		0x1fff0000
    990 /** Start of hblank, measured in pixels minus one from start of hsync */
    991 # define TV_HBLANK_START_SHIFT		0
    992 # define TV_HBLANK_START_MASK		0x0001fff
    993 
    994 #define TV_V_CTL_1		0x6803c
    995 /** XXX */
    996 # define TV_NBR_END_SHIFT		16
    997 # define TV_NBR_END_MASK		0x07ff0000
    998 /** XXX */
    999 # define TV_VI_END_F1_SHIFT		8
   1000 # define TV_VI_END_F1_MASK		0x00003f00
   1001 /** XXX */
   1002 # define TV_VI_END_F2_SHIFT		0
   1003 # define TV_VI_END_F2_MASK		0x0000003f
   1004 
   1005 #define TV_V_CTL_2		0x68040
   1006 /** Length of vsync, in half lines */
   1007 # define TV_VSYNC_LEN_MASK		0x07ff0000
   1008 # define TV_VSYNC_LEN_SHIFT		16
   1009 /** Offset of the start of vsync in field 1, measured in one less than the
   1010  * number of half lines.
   1011  */
   1012 # define TV_VSYNC_START_F1_MASK		0x00007f00
   1013 # define TV_VSYNC_START_F1_SHIFT	8
   1014 /**
   1015  * Offset of the start of vsync in field 2, measured in one less than the
   1016  * number of half lines.
   1017  */
   1018 # define TV_VSYNC_START_F2_MASK		0x0000007f
   1019 # define TV_VSYNC_START_F2_SHIFT	0
   1020 
   1021 #define TV_V_CTL_3		0x68044
   1022 /** Enables generation of the equalization signal */
   1023 # define TV_EQUAL_ENA			(1 << 31)
   1024 /** Length of vsync, in half lines */
   1025 # define TV_VEQ_LEN_MASK		0x007f0000
   1026 # define TV_VEQ_LEN_SHIFT		16
   1027 /** Offset of the start of equalization in field 1, measured in one less than
   1028  * the number of half lines.
   1029  */
   1030 # define TV_VEQ_START_F1_MASK		0x0007f00
   1031 # define TV_VEQ_START_F1_SHIFT		8
   1032 /**
   1033  * Offset of the start of equalization in field 2, measured in one less than
   1034  * the number of half lines.
   1035  */
   1036 # define TV_VEQ_START_F2_MASK		0x000007f
   1037 # define TV_VEQ_START_F2_SHIFT		0
   1038 
   1039 #define TV_V_CTL_4		0x68048
   1040 /**
   1041  * Offset to start of vertical colorburst, measured in one less than the
   1042  * number of lines from vertical start.
   1043  */
   1044 # define TV_VBURST_START_F1_MASK	0x003f0000
   1045 # define TV_VBURST_START_F1_SHIFT	16
   1046 /**
   1047  * Offset to the end of vertical colorburst, measured in one less than the
   1048  * number of lines from the start of NBR.
   1049  */
   1050 # define TV_VBURST_END_F1_MASK		0x000000ff
   1051 # define TV_VBURST_END_F1_SHIFT		0
   1052 
   1053 #define TV_V_CTL_5		0x6804c
   1054 /**
   1055  * Offset to start of vertical colorburst, measured in one less than the
   1056  * number of lines from vertical start.
   1057  */
   1058 # define TV_VBURST_START_F2_MASK	0x003f0000
   1059 # define TV_VBURST_START_F2_SHIFT	16
   1060 /**
   1061  * Offset to the end of vertical colorburst, measured in one less than the
   1062  * number of lines from the start of NBR.
   1063  */
   1064 # define TV_VBURST_END_F2_MASK		0x000000ff
   1065 # define TV_VBURST_END_F2_SHIFT		0
   1066 
   1067 #define TV_V_CTL_6		0x68050
   1068 /**
   1069  * Offset to start of vertical colorburst, measured in one less than the
   1070  * number of lines from vertical start.
   1071  */
   1072 # define TV_VBURST_START_F3_MASK	0x003f0000
   1073 # define TV_VBURST_START_F3_SHIFT	16
   1074 /**
   1075  * Offset to the end of vertical colorburst, measured in one less than the
   1076  * number of lines from the start of NBR.
   1077  */
   1078 # define TV_VBURST_END_F3_MASK		0x000000ff
   1079 # define TV_VBURST_END_F3_SHIFT		0
   1080 
   1081 #define TV_V_CTL_7		0x68054
   1082 /**
   1083  * Offset to start of vertical colorburst, measured in one less than the
   1084  * number of lines from vertical start.
   1085  */
   1086 # define TV_VBURST_START_F4_MASK	0x003f0000
   1087 # define TV_VBURST_START_F4_SHIFT	16
   1088 /**
   1089  * Offset to the end of vertical colorburst, measured in one less than the
   1090  * number of lines from the start of NBR.
   1091  */
   1092 # define TV_VBURST_END_F4_MASK		0x000000ff
   1093 # define TV_VBURST_END_F4_SHIFT		0
   1094 
   1095 #define TV_SC_CTL_1		0x68060
   1096 /** Turns on the first subcarrier phase generation DDA */
   1097 # define TV_SC_DDA1_EN			(1 << 31)
   1098 /** Turns on the first subcarrier phase generation DDA */
   1099 # define TV_SC_DDA2_EN			(1 << 30)
   1100 /** Turns on the first subcarrier phase generation DDA */
   1101 # define TV_SC_DDA3_EN			(1 << 29)
   1102 /** Sets the subcarrier DDA to reset frequency every other field */
   1103 # define TV_SC_RESET_EVERY_2		(0 << 24)
   1104 /** Sets the subcarrier DDA to reset frequency every fourth field */
   1105 # define TV_SC_RESET_EVERY_4		(1 << 24)
   1106 /** Sets the subcarrier DDA to reset frequency every eighth field */
   1107 # define TV_SC_RESET_EVERY_8		(2 << 24)
   1108 /** Sets the subcarrier DDA to never reset the frequency */
   1109 # define TV_SC_RESET_NEVER		(3 << 24)
   1110 /** Sets the peak amplitude of the colorburst.*/
   1111 # define TV_BURST_LEVEL_MASK		0x00ff0000
   1112 # define TV_BURST_LEVEL_SHIFT		16
   1113 /** Sets the increment of the first subcarrier phase generation DDA */
   1114 # define TV_SCDDA1_INC_MASK		0x00000fff
   1115 # define TV_SCDDA1_INC_SHIFT		0
   1116 
   1117 #define TV_SC_CTL_2		0x68064
   1118 /** Sets the rollover for the second subcarrier phase generation DDA */
   1119 # define TV_SCDDA2_SIZE_MASK		0x7fff0000
   1120 # define TV_SCDDA2_SIZE_SHIFT		16
   1121 /** Sets the increent of the second subcarrier phase generation DDA */
   1122 # define TV_SCDDA2_INC_MASK		0x00007fff
   1123 # define TV_SCDDA2_INC_SHIFT		0
   1124 
   1125 #define TV_SC_CTL_3		0x68068
   1126 /** Sets the rollover for the third subcarrier phase generation DDA */
   1127 # define TV_SCDDA3_SIZE_MASK		0x7fff0000
   1128 # define TV_SCDDA3_SIZE_SHIFT		16
   1129 /** Sets the increent of the third subcarrier phase generation DDA */
   1130 # define TV_SCDDA3_INC_MASK		0x00007fff
   1131 # define TV_SCDDA3_INC_SHIFT		0
   1132 
   1133 #define TV_WIN_POS		0x68070
   1134 /** X coordinate of the display from the start of horizontal active */
   1135 # define TV_XPOS_MASK			0x1fff0000
   1136 # define TV_XPOS_SHIFT			16
   1137 /** Y coordinate of the display from the start of vertical active (NBR) */
   1138 # define TV_YPOS_MASK			0x00000fff
   1139 # define TV_YPOS_SHIFT			0
   1140 
   1141 #define TV_WIN_SIZE		0x68074
   1142 /** Horizontal size of the display window, measured in pixels*/
   1143 # define TV_XSIZE_MASK			0x1fff0000
   1144 # define TV_XSIZE_SHIFT			16
   1145 /**
   1146  * Vertical size of the display window, measured in pixels.
   1147  *
   1148  * Must be even for interlaced modes.
   1149  */
   1150 # define TV_YSIZE_MASK			0x00000fff
   1151 # define TV_YSIZE_SHIFT			0
   1152 
   1153 #define TV_FILTER_CTL_1		0x68080
   1154 /**
   1155  * Enables automatic scaling calculation.
   1156  *
   1157  * If set, the rest of the registers are ignored, and the calculated values can
   1158  * be read back from the register.
   1159  */
   1160 # define TV_AUTO_SCALE			(1 << 31)
   1161 /**
   1162  * Disables the vertical filter.
   1163  *
   1164  * This is required on modes more than 1024 pixels wide */
   1165 # define TV_V_FILTER_BYPASS		(1 << 29)
   1166 /** Enables adaptive vertical filtering */
   1167 # define TV_VADAPT			(1 << 28)
   1168 # define TV_VADAPT_MODE_MASK		(3 << 26)
   1169 /** Selects the least adaptive vertical filtering mode */
   1170 # define TV_VADAPT_MODE_LEAST		(0 << 26)
   1171 /** Selects the moderately adaptive vertical filtering mode */
   1172 # define TV_VADAPT_MODE_MODERATE	(1 << 26)
   1173 /** Selects the most adaptive vertical filtering mode */
   1174 # define TV_VADAPT_MODE_MOST		(3 << 26)
   1175 /**
   1176  * Sets the horizontal scaling factor.
   1177  *
   1178  * This should be the fractional part of the horizontal scaling factor divided
   1179  * by the oversampling rate.  TV_HSCALE should be less than 1, and set to:
   1180  *
   1181  * (src width - 1) / ((oversample * dest width) - 1)
   1182  */
   1183 # define TV_HSCALE_FRAC_MASK		0x00003fff
   1184 # define TV_HSCALE_FRAC_SHIFT		0
   1185 
   1186 #define TV_FILTER_CTL_2		0x68084
   1187 /**
   1188  * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
   1189  *
   1190  * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
   1191  */
   1192 # define TV_VSCALE_INT_MASK		0x00038000
   1193 # define TV_VSCALE_INT_SHIFT		15
   1194 /**
   1195  * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
   1196  *
   1197  * \sa TV_VSCALE_INT_MASK
   1198  */
   1199 # define TV_VSCALE_FRAC_MASK		0x00007fff
   1200 # define TV_VSCALE_FRAC_SHIFT		0
   1201 
   1202 #define TV_FILTER_CTL_3		0x68088
   1203 /**
   1204  * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
   1205  *
   1206  * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
   1207  *
   1208  * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
   1209  */
   1210 # define TV_VSCALE_IP_INT_MASK		0x00038000
   1211 # define TV_VSCALE_IP_INT_SHIFT		15
   1212 /**
   1213  * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
   1214  *
   1215  * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
   1216  *
   1217  * \sa TV_VSCALE_IP_INT_MASK
   1218  */
   1219 # define TV_VSCALE_IP_FRAC_MASK		0x00007fff
   1220 # define TV_VSCALE_IP_FRAC_SHIFT		0
   1221 
   1222 #define TV_CC_CONTROL		0x68090
   1223 # define TV_CC_ENABLE			(1 << 31)
   1224 /**
   1225  * Specifies which field to send the CC data in.
   1226  *
   1227  * CC data is usually sent in field 0.
   1228  */
   1229 # define TV_CC_FID_MASK			(1 << 27)
   1230 # define TV_CC_FID_SHIFT		27
   1231 /** Sets the horizontal position of the CC data.  Usually 135. */
   1232 # define TV_CC_HOFF_MASK		0x03ff0000
   1233 # define TV_CC_HOFF_SHIFT		16
   1234 /** Sets the vertical position of the CC data.  Usually 21 */
   1235 # define TV_CC_LINE_MASK		0x0000003f
   1236 # define TV_CC_LINE_SHIFT		0
   1237 
   1238 #define TV_CC_DATA		0x68094
   1239 # define TV_CC_RDY			(1 << 31)
   1240 /** Second word of CC data to be transmitted. */
   1241 # define TV_CC_DATA_2_MASK		0x007f0000
   1242 # define TV_CC_DATA_2_SHIFT		16
   1243 /** First word of CC data to be transmitted. */
   1244 # define TV_CC_DATA_1_MASK		0x0000007f
   1245 # define TV_CC_DATA_1_SHIFT		0
   1246 
   1247 #define TV_H_LUMA_0		0x68100
   1248 #define TV_H_LUMA_59		0x681ec
   1249 #define TV_H_CHROMA_0		0x68200
   1250 #define TV_H_CHROMA_59		0x682ec
   1251 #define TV_V_LUMA_0		0x68300
   1252 #define TV_V_LUMA_42		0x683a8
   1253 #define TV_V_CHROMA_0		0x68400
   1254 #define TV_V_CHROMA_42		0x684a8
   1255 
   1256 /* Display & cursor control */
   1257 
   1258 /* Pipe A */
   1259 #define PIPEADSL		0x70000
   1260 #define PIPEACONF		0x70008
   1261 #define   PIPEACONF_ENABLE	(1<<31)
   1262 #define   PIPEACONF_DISABLE	0
   1263 #define   PIPEACONF_DOUBLE_WIDE	(1<<30)
   1264 #define   I965_PIPECONF_ACTIVE	(1<<30)
   1265 #define   PIPEACONF_SINGLE_WIDE	0
   1266 #define   PIPEACONF_PIPE_UNLOCKED 0
   1267 #define   PIPEACONF_PIPE_LOCKED	(1<<25)
   1268 #define   PIPEACONF_PALETTE	0
   1269 #define   PIPEACONF_GAMMA		(1<<24)
   1270 #define   PIPECONF_FORCE_BORDER	(1<<25)
   1271 #define   PIPECONF_PROGRESSIVE	(0 << 21)
   1272 #define   PIPECONF_INTERLACE_W_FIELD_INDICATION	(6 << 21)
   1273 #define   PIPECONF_INTERLACE_FIELD_0_ONLY		(7 << 21)
   1274 #define PIPEASTAT		0x70024
   1275 #define   PIPE_FIFO_UNDERRUN_STATUS		(1UL<<31)
   1276 #define   PIPE_CRC_ERROR_ENABLE			(1UL<<29)
   1277 #define   PIPE_CRC_DONE_ENABLE			(1UL<<28)
   1278 #define   PIPE_GMBUS_EVENT_ENABLE		(1UL<<27)
   1279 #define   PIPE_HOTPLUG_INTERRUPT_ENABLE		(1UL<<26)
   1280 #define   PIPE_VSYNC_INTERRUPT_ENABLE		(1UL<<25)
   1281 #define   PIPE_DISPLAY_LINE_COMPARE_ENABLE	(1UL<<24)
   1282 #define   PIPE_DPST_EVENT_ENABLE		(1UL<<23)
   1283 #define   PIPE_LEGACY_BLC_EVENT_ENABLE		(1UL<<22)
   1284 #define   PIPE_ODD_FIELD_INTERRUPT_ENABLE	(1UL<<21)
   1285 #define   PIPE_EVEN_FIELD_INTERRUPT_ENABLE	(1UL<<20)
   1286 #define   PIPE_HOTPLUG_TV_INTERRUPT_ENABLE	(1UL<<18) /* pre-965 */
   1287 #define   PIPE_START_VBLANK_INTERRUPT_ENABLE	(1UL<<18) /* 965 or later */
   1288 #define   PIPE_VBLANK_INTERRUPT_ENABLE		(1UL<<17)
   1289 #define   PIPE_OVERLAY_UPDATED_ENABLE		(1UL<<16)
   1290 #define   PIPE_CRC_ERROR_INTERRUPT_STATUS	(1UL<<13)
   1291 #define   PIPE_CRC_DONE_INTERRUPT_STATUS	(1UL<<12)
   1292 #define   PIPE_GMBUS_INTERRUPT_STATUS		(1UL<<11)
   1293 #define   PIPE_HOTPLUG_INTERRUPT_STATUS		(1UL<<10)
   1294 #define   PIPE_VSYNC_INTERRUPT_STATUS		(1UL<<9)
   1295 #define   PIPE_DISPLAY_LINE_COMPARE_STATUS	(1UL<<8)
   1296 #define   PIPE_DPST_EVENT_STATUS		(1UL<<7)
   1297 #define   PIPE_LEGACY_BLC_EVENT_STATUS		(1UL<<6)
   1298 #define   PIPE_ODD_FIELD_INTERRUPT_STATUS	(1UL<<5)
   1299 #define   PIPE_EVEN_FIELD_INTERRUPT_STATUS	(1UL<<4)
   1300 #define   PIPE_HOTPLUG_TV_INTERRUPT_STATUS	(1UL<<2) /* pre-965 */
   1301 #define   PIPE_START_VBLANK_INTERRUPT_STATUS	(1UL<<2) /* 965 or later */
   1302 #define   PIPE_VBLANK_INTERRUPT_STATUS		(1UL<<1)
   1303 #define   PIPE_OVERLAY_UPDATED_STATUS		(1UL<<0)
   1304 
   1305 #define DSPARB			0x70030
   1306 #define   DSPARB_CSTART_MASK	(0x7f << 7)
   1307 #define   DSPARB_CSTART_SHIFT	7
   1308 #define   DSPARB_BSTART_MASK	(0x7f)
   1309 #define   DSPARB_BSTART_SHIFT	0
   1310 /*
   1311  * The two pipe frame counter registers are not synchronized, so
   1312  * reading a stable value is somewhat tricky. The following code
   1313  * should work:
   1314  *
   1315  *  do {
   1316  *    high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
   1317  *             PIPE_FRAME_HIGH_SHIFT;
   1318  *    low1 =  ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
   1319  *             PIPE_FRAME_LOW_SHIFT);
   1320  *    high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
   1321  *             PIPE_FRAME_HIGH_SHIFT);
   1322  *  } while (high1 != high2);
   1323  *  frame = (high1 << 8) | low1;
   1324  */
   1325 #define PIPEAFRAMEHIGH          0x70040
   1326 #define   PIPE_FRAME_HIGH_MASK    0x0000ffff
   1327 #define   PIPE_FRAME_HIGH_SHIFT   0
   1328 #define PIPEAFRAMEPIXEL         0x70044
   1329 #define   PIPE_FRAME_LOW_MASK     0xff000000
   1330 #define   PIPE_FRAME_LOW_SHIFT    24
   1331 #define   PIPE_PIXEL_MASK         0x00ffffff
   1332 #define   PIPE_PIXEL_SHIFT        0
   1333 /* GM45+ just has to be different */
   1334 #define PIPEA_FRMCOUNT_GM45	0x70040
   1335 #define PIPEA_FLIPCOUNT_GM45	0x70044
   1336 
   1337 /* Cursor A & B regs */
   1338 #define CURACNTR		0x70080
   1339 #define   CURSOR_MODE_DISABLE   0x00
   1340 #define   CURSOR_MODE_64_32B_AX 0x07
   1341 #define   CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
   1342 #define   MCURSOR_GAMMA_ENABLE  (1 << 26)
   1343 #define CURABASE		0x70084
   1344 #define CURAPOS			0x70088
   1345 #define   CURSOR_POS_MASK       0x007FF
   1346 #define   CURSOR_POS_SIGN       0x8000
   1347 #define   CURSOR_X_SHIFT        0
   1348 #define   CURSOR_Y_SHIFT        16
   1349 #define CURBCNTR		0x700c0
   1350 #define CURBBASE		0x700c4
   1351 #define CURBPOS			0x700c8
   1352 
   1353 /* Display A control */
   1354 #define DSPACNTR                0x70180
   1355 #define   DISPLAY_PLANE_ENABLE			(1<<31)
   1356 #define   DISPLAY_PLANE_DISABLE			0
   1357 #define   DISPPLANE_GAMMA_ENABLE		(1<<30)
   1358 #define   DISPPLANE_GAMMA_DISABLE		0
   1359 #define   DISPPLANE_PIXFORMAT_MASK		(0xf<<26)
   1360 #define   DISPPLANE_8BPP			(0x2<<26)
   1361 #define   DISPPLANE_15_16BPP			(0x4<<26)
   1362 #define   DISPPLANE_16BPP			(0x5<<26)
   1363 #define   DISPPLANE_32BPP_NO_ALPHA		(0x6<<26)
   1364 #define   DISPPLANE_32BPP			(0x7<<26)
   1365 #define   DISPPLANE_STEREO_ENABLE		(1<<25)
   1366 #define   DISPPLANE_STEREO_DISABLE		0
   1367 #define   DISPPLANE_SEL_PIPE_MASK		(1<<24)
   1368 #define   DISPPLANE_SEL_PIPE_A			0
   1369 #define   DISPPLANE_SEL_PIPE_B			(1<<24)
   1370 #define   DISPPLANE_SRC_KEY_ENABLE		(1<<22)
   1371 #define   DISPPLANE_SRC_KEY_DISABLE		0
   1372 #define   DISPPLANE_LINE_DOUBLE			(1<<20)
   1373 #define   DISPPLANE_NO_LINE_DOUBLE		0
   1374 #define   DISPPLANE_STEREO_POLARITY_FIRST	0
   1375 #define   DISPPLANE_STEREO_POLARITY_SECOND	(1<<18)
   1376 #define DSPAADDR		0x70184
   1377 #define DSPASTRIDE		0x70188
   1378 #define DSPAPOS			0x7018C /* reserved */
   1379 #define DSPASIZE		0x70190
   1380 #define DSPASURF		0x7019C /* 965+ only */
   1381 #define DSPATILEOFF		0x701A4 /* 965+ only */
   1382 
   1383 /* VBIOS flags */
   1384 #define SWF00			0x71410
   1385 #define SWF01			0x71414
   1386 #define SWF02			0x71418
   1387 #define SWF03			0x7141c
   1388 #define SWF04			0x71420
   1389 #define SWF05			0x71424
   1390 #define SWF06			0x71428
   1391 #define SWF10			0x70410
   1392 #define SWF11			0x70414
   1393 #define SWF14			0x71420
   1394 #define SWF30			0x72414
   1395 #define SWF31			0x72418
   1396 #define SWF32			0x7241c
   1397 
   1398 /* Pipe B */
   1399 #define PIPEBDSL		0x71000
   1400 #define PIPEBCONF		0x71008
   1401 #define PIPEBSTAT		0x71024
   1402 #define PIPEBFRAMEHIGH		0x71040
   1403 #define PIPEBFRAMEPIXEL		0x71044
   1404 #define PIPEB_FRMCOUNT_GM45	0x71040
   1405 #define PIPEB_FLIPCOUNT_GM45	0x71044
   1406 
   1407 /* Display B control */
   1408 #define DSPBCNTR		0x71180
   1409 #define   DISPPLANE_ALPHA_TRANS_ENABLE		(1<<15)
   1410 #define   DISPPLANE_ALPHA_TRANS_DISABLE		0
   1411 #define   DISPPLANE_SPRITE_ABOVE_DISPLAY	0
   1412 #define   DISPPLANE_SPRITE_ABOVE_OVERLAY	(1)
   1413 #define DSPBADDR		0x71184
   1414 #define DSPBSTRIDE		0x71188
   1415 #define DSPBPOS			0x7118C
   1416 #define DSPBSIZE		0x71190
   1417 #define DSPBSURF		0x7119C
   1418 #define DSPBTILEOFF		0x711A4
   1419 
   1420 /* VBIOS regs */
   1421 #define VGACNTRL		0x71400
   1422 # define VGA_DISP_DISABLE			(1 << 31)
   1423 # define VGA_2X_MODE				(1 << 30)
   1424 # define VGA_PIPE_B_SELECT			(1 << 29)
   1425 
   1426 #endif /* _I915_REG_H_ */
   1427