1 /* $NetBSD: qdreg.h,v 1.7 2023/02/06 13:13:05 tsutsui Exp $ */ 2 /*- 3 * Copyright (c) 1982, 1986 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. Neither the name of the University nor the names of its contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * @(#)qdreg.h 7.1 (Berkeley) 5/9/91 31 */ 32 33 /************************************************************************ 34 * * 35 * Copyright (c) 1985, 1986 by * 36 * Digital Equipment Corporation, Maynard, MA * 37 * All rights reserved. * 38 * * 39 * This software is furnished under a license and may be used and * 40 * copied only in accordance with the terms of such license and * 41 * with the inclusion of the above copyright notice. This * 42 * software or any other copies thereof may not be provided or * 43 * otherwise made available to any other person. No title to and * 44 * ownership of the software is hereby transferred. * 45 * * 46 * The information in this software is subject to change without * 47 * notice and should not be construed as a commitment by Digital * 48 * Equipment Corporation. * 49 * * 50 * Digital assumes no responsibility for the use or reliability * 51 * of its software on equipment which is not supplied by Digital. * 52 * * 53 ************************************************************************/ 54 55 /* Dragon ADDER reg map */ 56 /* ADDER register bit definitions */ 57 /* Y_SCROLL_CONSTANT */ 58 59 #define SCROLL_ERASE 0x2000 60 #define ADDER_SCROLL_DOWN 0x1000 61 62 /* ADDER status and interrupt enable registers [1], [2], [3] */ 63 64 #define DISABLE 0x0000 65 #define PAUSE_COMPLETE 0x0001 66 #define FRAME_SYNC 0x0002 67 #define INIT_COMPLETE 0x0004 68 #define RASTEROP_COMPLETE 0x0008 69 70 #define ADDRESS_COMPLETE 0x0010 71 #define RX_READY 0x0020 72 #define TX_READY 0x0040 73 #define ID_SCROLL_READY 0x0080 74 75 #define TOP_CLIP 0x0100 76 #define BOTTOM_CLIP 0x0200 77 #define LEFT_CLIP 0x0400 78 #define RIGHT_CLIP 0x0800 79 #define NO_CLIP 0x1000 80 #define VSYNC 0x2000 81 82 /* ADDER command register [8], [10] */ 83 84 #define OCR_zero 0x0000 85 #define Z_BLOCK0 0x0000 86 #define OCRA 0x0000 87 #define OCRB 0x0004 88 #define RASTEROP 0x02c0 89 #define PBT 0x03c0 90 #define BTPZ 0x0bb0 91 #define PTBZ 0x07a0 92 #define DTE 0x0400 93 #define S1E 0x0800 94 #define S2E 0x1000 95 #define VIPER_Z_LOAD 0x01A0 96 #define ID_LOAD 0x0100 97 #define CANCEL 0x0000 98 #define LF_R1 0x0000 99 #define LF_R2 0x0010 100 #define LF_R3 0x0020 101 #define LF_R4 0x0030 102 103 /* ADDER rasterop mode register [9] */ 104 105 #define NORMAL 0x0000 106 #define LINEAR_PATTERN 0x0002 107 #define X_FILL 0x0003 108 #define Y_FILL 0x0007 109 #define BASELINE 0x0008 110 #define HOLE_ENABLE 0x0010 111 #define SRC_1_INDEX_ENABLE 0x0020 112 #define DST_INDEX_ENABLE 0x0040 113 #define DST_WRITE_ENABLE 0x0080 114 115 /* ADDER source 2 size register */ 116 117 #define NO_TILE 0x0080 118 119 /* External registers base addresses */ 120 121 #define CS_UPDATE_MASK 0x0060 122 #define CS_SCROLL_MASK 0x0040 123 124 /* VIPER registers */ 125 126 #define RESOLUTION_MODE 0x0080 127 #define MEMORY_BUS_WIDTH 0x0081 128 #define PLANE_ADDRESS 0x0083 129 #define LU_FUNCTION_R1 0x0084 130 #define LU_FUNCTION_R2 0x0085 131 #define LU_FUNCTION_R3 0x0086 132 #define LU_FUNCTION_R4 0x0087 133 #define MASK_1 0x0088 134 #define MASK_2 0x0089 135 #define SOURCE 0x008a 136 #define SOURCE_Z 0x0000 137 #define BACKGROUND_COLOR 0x008e 138 #define BACKGROUND_COLOR_Z 0x000C 139 #define FOREGROUND_COLOR 0x008f 140 #define FOREGROUND_COLOR_Z 0x0004 141 #define SRC1_OCR_A 0x0090 142 #define SRC2_OCR_A 0x0091 143 #define DST_OCR_A 0x0092 144 #define SRC1_OCR_B 0x0094 145 #define SRC2_OCR_B 0x0095 146 #define DST_OCR_B 0x0096 147 148 /* VIPER scroll registers */ 149 150 #define SCROLL_CONSTANT 0x0082 151 #define SCROLL_FILL 0x008b 152 #define SCROLL_FILL_Z 0x0008 153 #define LEFT_SCROLL_MASK 0x008c 154 #define RIGHT_SCROLL_MASK 0x008d 155 156 /* VIPER register bit definitions */ 157 158 #define EXT_NONE 0x0000 159 #define EXT_SOURCE 0x0001 160 #define EXT_M1_M2 0x0002 161 #define INT_NONE 0x0000 162 #define INT_SOURCE 0x0004 163 #define INT_M1_M2 0x0008 164 #define ID 0x0010 165 #define NO_ID 0x0000 166 #define WAIT 0x0020 167 #define NO_WAIT 0x0000 168 #define BAR_SHIFT_DELAY WAIT 169 #define NO_BAR_SHIFT_DELAY NO_WAIT 170 171 172 /* VIPER logical function unit codes */ 173 174 #define LF_ZEROS 0x0000 175 #define LF_NOT_D 0x0003 176 #define LF_D_XOR_S 0x0006 177 #define LF_SOURCE 0x000a 178 #define LF_D 0x000c 179 #define LF_D_OR_S 0x000d 180 #define LF_ONES 0x000f 181 #define INV_M1_M2 0x0030 182 #define FULL_SRC_RESOLUTION 0X00C0 /* makes second pass like first pass */ 183 184 /* VIPER scroll register [2] */ 185 186 #define SCROLL_DISABLE 0x0040 187 #define SCROLL_ENABLE 0x0020 188 #define VIPER_LEFT 0x0000 189 #define VIPER_RIGHT 0x0010 190 #define VIPER_UP 0x0040 191 #define VIPER_DOWN 0x0000 192 193 /* Adder scroll register */ 194 195 #define ADDER_UP 0x0000 196 #define ADDER_DOWN 0x1000 197 198 /* Misc scroll definitions */ 199 200 #define UP 0 201 #define DOWN 1 202 #define LEFT 2 203 #define RIGHT 3 204 #define NODIR 4 205 #define SCROLL_VMAX 31 206 #define SCROLL_HMAX 15 207 #define NEW 2 208 #define OLD 1 209 #define BUSY 1 210 #define DRAG 1 211 #define SCROLL 0 212 213 /* miscellaneous defines */ 214 215 #define ALL_PLANES 0xffffffff 216 #define UNITY 0x1fff /* Adder scale factor */ 217 #define MAX_SCREEN_X 1024 218 #define MAX_SCREEN_Y 864 219 #define FONT_HEIGHT 32 220 221 struct adder { 222 223 /* adder control registers */ 224 225 u_short register_address; /* ADDER reg pntr for use by DGA */ 226 u_short request_enable; /* DMA request enables */ 227 u_short interrupt_enable; /* interrupt enables */ 228 u_short status; /* ADDER status bits */ 229 u_short reserved1; /* test function only */ 230 u_short spare1; /* spare address (what else?) */ 231 232 u_short reserved2; /* test function only */ 233 u_short id_data; /* data path to I/D bus */ 234 u_short command; /* ADDER chip command register */ 235 u_short rasterop_mode; /* sets rasterop execution modes */ 236 u_short cmd; /* duplicate path to above cmd reg */ 237 u_short reserved3; /* test function only */ 238 239 /* scroll registers */ 240 241 u_short ID_scroll_data; /* I/D bus scroll data */ 242 u_short ID_scroll_command; /* I/D bus scroll command */ 243 u_short scroll_x_min; /* X scroll min - left boundary */ 244 u_short scroll_x_max; /* X scroll max - right boundary */ 245 u_short scroll_y_min; /* Y scroll min - upper boundary */ 246 u_short scroll_y_max; /* Y scroll max - lower boundary */ 247 u_short pause; /* Y coord to set stat when scanned */ 248 u_short y_offset_pending; /* vertical scroll control */ 249 u_short y_scroll_constant; 250 251 /* update control registers */ 252 253 u_short x_index_pending; /* x pending index */ 254 u_short y_index_pending; /* y pending index */ 255 u_short x_index_new; /* new x index */ 256 u_short y_index_new; /* new y index */ 257 u_short x_index_old; /* old x index */ 258 u_short y_index_old; /* old y index */ 259 u_short x_clip_min; /* left clipping boundary */ 260 u_short x_clip_max; /* right clipping boundary */ 261 u_short y_clip_min; /* upper clipping boundary */ 262 u_short y_clip_max; /* lower clipping boundary */ 263 u_short spare2; /* spare address (another!) */ 264 265 /* rasterop control registers */ 266 267 u_short source_1_dx; /* source #1 x vector */ 268 u_short source_1_dy; /* source #1 y vector*/ 269 u_short source_1_x; /* source #1 x origin */ 270 u_short source_1_y; /* source #1 y origin */ 271 u_short destination_x; /* destination x origin */ 272 u_short destination_y; /* destination y origin */ 273 u_short fast_dest_dx; /* destination x fast vector */ 274 u_short fast_dest_dy; /* destination y fast vector */ 275 u_short slow_dest_dx; /* destination x slow vector */ 276 u_short slow_dest_dy; /* destination y slow vector */ 277 u_short fast_scale; /* scale factor for fast vector */ 278 u_short slow_scale; /* scale factor for slow vector */ 279 u_short source_2_x; /* source #2 x origin */ 280 u_short source_2_y; /* source #2 y origin */ 281 u_short source_2_size; /* source #2 height & width */ 282 u_short error_1; /* error regs (?) */ 283 u_short error_2; 284 285 /* screen format control registers */ 286 287 u_short y_scan_count_0; /* y scan counts for vert timing */ 288 u_short y_scan_count_1; 289 u_short y_scan_count_2; 290 u_short y_scan_count_3; 291 u_short x_scan_conf; /* x scan configuration */ 292 u_short x_limit; 293 u_short y_limit; 294 u_short x_scan_count_0; /* x scan count for horiz timing */ 295 u_short x_scan_count_1; 296 u_short x_scan_count_2; 297 u_short x_scan_count_3; 298 u_short x_scan_count_4; 299 u_short x_scan_count_5; 300 u_short x_scan_count_6; 301 u_short sync_phase_adj; /* sync phase (horiz sync count) */ 302 }; 303 304 /*--------------------- 305 * DUART definitions */ 306 307 /* command definitions */ 308 309 #define EN_RCV 0x01 310 #define DIS_RCV 0x02 311 #define EN_XMT 0x04 312 #define DIS_XMT 0x08 313 #define RESET_M 0x10 314 #define RESET_RCV 0x20 315 #define RESET_XMT 0x30 316 #define RESET_ERR 0x40 317 #define RESET_BD 0x50 318 #define START_BREAK 0x60 319 #define STOP_BREAK 0x70 320 321 /* interrupt bit definitions */ 322 323 #define EI_XMT_A 0x01 324 #define EI_RCV_A 0x02 325 #define EI_XMT_B 0x10 326 #define EI_RCV_B 0x20 327 328 #define XMT_RDY_A 0x01 329 #define RCV_RDY_A 0x02 330 #define XMT_RDY_B 0x10 331 #define RCV_RDY_B 0x20 332 333 /* status register bit definitions */ 334 335 #define RCV_RDY 0x01 336 #define FIFO_FULL 0x02 337 #define XMT_RDY 0x04 338 #define XMT_EMT 0x08 339 #define OVER_ERR 0x10 340 #define ERR_PARITY 0x20 341 #define FRAME_ERR 0x40 342 #define RCVD_BREAK 0x80 343 344 345 struct duart { 346 347 /* channel A - LK201 */ 348 349 short modeA; /* ch.A mode reg (read/write) */ 350 short statusA; /* ch.A status reg (read) */ 351 #define clkselA statusA /* ch.A clock select reg (write) */ 352 short cmdA; /* ch.A command reg (write) */ 353 short dataA; /* rcv/xmt data ch.A (read/write) */ 354 short inchng; /* input change state reg (read) */ 355 #define auxctl inchng /* auxiliary control reg (write) */ 356 short istatus; /* interrupt status reg (read) */ 357 #define imask istatus /* interrupt mask reg (write) */ 358 short CThi; /* counter/timer hi byte (read) */ 359 #define CTRhi CThi /* counter/timer hi reg (write) */ 360 short CTlo; /* counter/timer lo byte (read) */ 361 #define CTRlo CTlo /* counter/timer lo reg (write) */ 362 363 /* channel B - pointing device */ 364 365 short modeB; /* ch.B mode reg (read/write) */ 366 short statusB; /* ch.B status reg (read) */ 367 #define clkselB statusB /* ch.B clock select reg (write) */ 368 short cmdB; /* ch.B command reg (write) */ 369 short dataB; /* ch.B rcv/xmt data (read/write) */ 370 short rsrvd; 371 short inport; /* input port (read) */ 372 #define outconf inport /* output port config reg (write) */ 373 short strctr; /* start counter command (read) */ 374 #define setbits setctr /* output bits set command (write) */ 375 short stpctr; /* stop counter command (read) */ 376 #define resetbits stpctr /* output bits reset cmd (write) */ 377 378 }; 379
Indexes created Mon Sep 29 03:10:08 GMT 2025