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    Searched defs:LaneMask (Results 1 - 16 of 16) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
RegisterPressure.h 41 LaneBitmask LaneMask;
43 RegisterMaskPair(Register RegUnit, LaneBitmask LaneMask)
44 : RegUnit(RegUnit), LaneMask(LaneMask) {}
264 LaneBitmask LaneMask;
266 IndexMaskPair(unsigned Index, LaneBitmask LaneMask)
267 : Index(Index), LaneMask(LaneMask) {}
300 return I->LaneMask;
303 /// Mark the \p Pair.LaneMask lanes of \p Pair.Reg as live
    [all...]
ScheduleDAGInstrs.h 54 LaneBitmask LaneMask;
57 VReg2SUnit(unsigned VReg, LaneBitmask LaneMask, SUnit *SU)
58 : VirtReg(VReg), LaneMask(LaneMask), SU(SU) {}
69 VReg2SUnitOperIdx(unsigned VReg, LaneBitmask LaneMask,
71 : VReg2SUnit(VReg, LaneMask, SU), OperandIndex(OperandIndex) {}
TargetRegisterInfo.h 56 const LaneBitmask LaneMask;
205 return LaneMask;
380 /// Try to find one or more subregister indexes to cover \p LaneMask.
386 LaneBitmask LaneMask,
635 /// Transforms a LaneMask computed for one subregister to the lanemask that
645 /// Transform a lanemask given for a virtual register to the corresponding
646 /// lanemask before using subregister with index \p IdxA.
653 LaneBitmask LaneMask) const {
655 return LaneMask;
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MachineBasicBlock.h 104 LaneBitmask LaneMask;
106 RegisterMaskPair(MCPhysReg PhysReg, LaneBitmask LaneMask)
107 : PhysReg(PhysReg), LaneMask(LaneMask) {}
368 LaneBitmask LaneMask = LaneBitmask::getAll()) {
369 LiveIns.push_back(RegisterMaskPair(PhysReg, LaneMask));
390 LaneBitmask LaneMask = LaneBitmask::getAll());
394 LaneBitmask LaneMask = LaneBitmask::getAll()) const;
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
LiveRangeEdit.cpp 49 LI.createSubRange(Alloc, S.LaneMask);
252 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubReg);
254 if ((S.LaneMask & LaneMask).any() && S.Query(Idx).isKill())
RenameIndependentSubregs.cpp 183 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubRegIdx);
187 if ((SR.LaneMask & LaneMask).none())
227 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubRegIdx);
232 if ((SR.LaneMask & LaneMask).none())
285 SubRanges[ID-1] = Intervals[ID]->createSubRange(Allocator, SR.LaneMask);
VirtRegMap.cpp 304 LaneBitmask LaneMask;
313 LaneMask |= SR->LaneMask;
315 if (LaneMask.none())
318 MBB->addLiveIn(PhysReg, LaneMask);
385 if ((SR.LaneMask & UseMask).any() && SR.liveAt(BaseIndex))
SplitKit.cpp 412 if (S.LaneMask == LM)
420 if ((S.LaneMask & LM) == LM)
437 auto &PS = getSubRangeForMask(S.LaneMask, Edit->getParent());
461 if ((S.LaneMask & LM).any())
539 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubIdx);
540 DestLI.refineSubRanges(Allocator, LaneMask,
549 LaneBitmask LaneMask, MachineBasicBlock &MBB,
552 if (LaneMask.all() || LaneMask == MRI.getMaxLaneMaskForVReg(FromReg)) {
566 // exists find the one covering the most lanemask bits
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LiveIntervals.cpp 377 Register Reg, LaneBitmask LaneMask) {
388 if ((SR.LaneMask & M).any()) {
389 assert(SR.LaneMask == M && "Expecting lane masks to match exactly");
397 const LiveRange &OldRange = getSubRange(LI, LaneMask);
444 assert(LaneMask.any() &&
447 LI.computeSubRangeUndefs(Undefs, LaneMask, *MRI, *Indexes);
579 LaneBitmask LaneMask = TRI->getSubRegIndexLaneMask(SubReg);
580 if ((LaneMask & SR.LaneMask).none())
608 extendSegmentsToUses(NewLR, WorkList, Reg, SR.LaneMask);
    [all...]
ScheduleDAGInstrs.cpp 386 return (RegUse->LaneMask & getLaneMaskForMO(MO)).none();
436 LaneBitmask LaneMask = I->LaneMask;
438 if ((LaneMask & KillLaneMask).none()) {
443 if ((LaneMask & DefLaneMask).any()) {
453 LaneMask &= ~KillLaneMask;
455 if (LaneMask.any()) {
456 I->LaneMask = LaneMask;
474 LaneBitmask LaneMask = DefLaneMask
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RegisterCoalescer.cpp 148 /// A LaneMask to remember on which subregister live ranges we need to call
251 /// LaneMask are split as necessary. @p LaneMask are the lanes that
255 LaneBitmask LaneMask, CoalescerPair &CP,
261 LaneBitmask LaneMask, const CoalescerPair &CP);
988 MaskA |= SA.LaneMask;
991 Allocator, SA.LaneMask,
1008 if ((SB.LaneMask & MaskA).any())
1231 IntB.computeSubRangeUndefs(Undefs, SR.LaneMask, *MRI,
1409 // Remap subranges to new lanemask and change register class
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  /src/external/apache2/llvm/dist/llvm/utils/TableGen/
CodeGenRegisters.h 72 mutable LaneBitmask LaneMask;
133 // Compute LaneMask from Composed. Return LaneMask.
336 LaneBitmask LaneMask;
795 // LaneMask is contained in CoveringLanes will be completely covered by
CodeGenRegisters.cpp 107 if (LaneMask.any())
108 return LaneMask;
111 LaneMask = LaneBitmask::getAll();
118 LaneMask = M;
119 return LaneMask;
1443 Twine("Ran out of lanemask bits to represent subregister ")
1446 Idx.LaneMask = LaneBitmask::getLane(Bit);
1449 Idx.LaneMask = LaneBitmask::getNone();
1468 unsigned DstBit = Idx.LaneMask.getHighestLane();
1469 assert(Idx.LaneMask == LaneBitmask::getLane(DstBit) &
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  /src/external/apache2/llvm/dist/llvm/lib/IR/
AutoUpgrade.cpp 2476 unsigned LaneMask = (Imm >> (l * NumControlBits)) & ControlBitsMask;
2479 LaneMask += NumLanes;
2481 ShuffleMask.push_back(LaneMask * NumElementsInLane + i);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelLowering.cpp 8381 int *LaneMask = &Mask[i * ResMultiplier];
8386 LaneMask[j] = ExtractBase + j;
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelLowering.cpp 7897 int *LaneMask = &Mask[i * ResMultiplier];
7902 LaneMask[j] = ExtractBase + j;

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