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      1 /*	$NetBSD: mt8173-larb-port.h,v 1.1.1.4 2021/11/07 16:49:56 jmcneill Exp $	*/
      2 
      3 /* SPDX-License-Identifier: GPL-2.0-only */
      4 /*
      5  * Copyright (c) 2015-2016 MediaTek Inc.
      6  * Author: Yong Wu <yong.wu (at) mediatek.com>
      7  */
      8 #ifndef _DT_BINDINGS_MEMORY_MT8173_LARB_PORT_H_
      9 #define _DT_BINDINGS_MEMORY_MT8173_LARB_PORT_H_
     10 
     11 #include <dt-bindings/memory/mtk-memory-port.h>
     12 
     13 #define M4U_LARB0_ID			0
     14 #define M4U_LARB1_ID			1
     15 #define M4U_LARB2_ID			2
     16 #define M4U_LARB3_ID			3
     17 #define M4U_LARB4_ID			4
     18 #define M4U_LARB5_ID			5
     19 
     20 /* larb0 */
     21 #define M4U_PORT_DISP_OVL0		MTK_M4U_ID(M4U_LARB0_ID, 0)
     22 #define M4U_PORT_DISP_RDMA0		MTK_M4U_ID(M4U_LARB0_ID, 1)
     23 #define M4U_PORT_DISP_WDMA0		MTK_M4U_ID(M4U_LARB0_ID, 2)
     24 #define M4U_PORT_DISP_OD_R		MTK_M4U_ID(M4U_LARB0_ID, 3)
     25 #define M4U_PORT_DISP_OD_W		MTK_M4U_ID(M4U_LARB0_ID, 4)
     26 #define M4U_PORT_MDP_RDMA0		MTK_M4U_ID(M4U_LARB0_ID, 5)
     27 #define M4U_PORT_MDP_WDMA		MTK_M4U_ID(M4U_LARB0_ID, 6)
     28 #define M4U_PORT_MDP_WROT0		MTK_M4U_ID(M4U_LARB0_ID, 7)
     29 
     30 /* larb1 */
     31 #define M4U_PORT_HW_VDEC_MC_EXT		MTK_M4U_ID(M4U_LARB1_ID, 0)
     32 #define M4U_PORT_HW_VDEC_PP_EXT		MTK_M4U_ID(M4U_LARB1_ID, 1)
     33 #define M4U_PORT_HW_VDEC_UFO_EXT	MTK_M4U_ID(M4U_LARB1_ID, 2)
     34 #define M4U_PORT_HW_VDEC_VLD_EXT	MTK_M4U_ID(M4U_LARB1_ID, 3)
     35 #define M4U_PORT_HW_VDEC_VLD2_EXT	MTK_M4U_ID(M4U_LARB1_ID, 4)
     36 #define M4U_PORT_HW_VDEC_AVC_MV_EXT	MTK_M4U_ID(M4U_LARB1_ID, 5)
     37 #define M4U_PORT_HW_VDEC_PRED_RD_EXT	MTK_M4U_ID(M4U_LARB1_ID, 6)
     38 #define M4U_PORT_HW_VDEC_PRED_WR_EXT	MTK_M4U_ID(M4U_LARB1_ID, 7)
     39 #define M4U_PORT_HW_VDEC_PPWRAP_EXT	MTK_M4U_ID(M4U_LARB1_ID, 8)
     40 #define M4U_PORT_HW_VDEC_TILE		MTK_M4U_ID(M4U_LARB1_ID, 9)
     41 
     42 /* larb2 */
     43 #define M4U_PORT_IMGO			MTK_M4U_ID(M4U_LARB2_ID, 0)
     44 #define M4U_PORT_RRZO			MTK_M4U_ID(M4U_LARB2_ID, 1)
     45 #define M4U_PORT_AAO			MTK_M4U_ID(M4U_LARB2_ID, 2)
     46 #define M4U_PORT_LCSO			MTK_M4U_ID(M4U_LARB2_ID, 3)
     47 #define M4U_PORT_ESFKO			MTK_M4U_ID(M4U_LARB2_ID, 4)
     48 #define M4U_PORT_IMGO_D			MTK_M4U_ID(M4U_LARB2_ID, 5)
     49 #define M4U_PORT_LSCI			MTK_M4U_ID(M4U_LARB2_ID, 6)
     50 #define M4U_PORT_LSCI_D			MTK_M4U_ID(M4U_LARB2_ID, 7)
     51 #define M4U_PORT_BPCI			MTK_M4U_ID(M4U_LARB2_ID, 8)
     52 #define M4U_PORT_BPCI_D			MTK_M4U_ID(M4U_LARB2_ID, 9)
     53 #define M4U_PORT_UFDI			MTK_M4U_ID(M4U_LARB2_ID, 10)
     54 #define M4U_PORT_IMGI			MTK_M4U_ID(M4U_LARB2_ID, 11)
     55 #define M4U_PORT_IMG2O			MTK_M4U_ID(M4U_LARB2_ID, 12)
     56 #define M4U_PORT_IMG3O			MTK_M4U_ID(M4U_LARB2_ID, 13)
     57 #define M4U_PORT_VIPI			MTK_M4U_ID(M4U_LARB2_ID, 14)
     58 #define M4U_PORT_VIP2I			MTK_M4U_ID(M4U_LARB2_ID, 15)
     59 #define M4U_PORT_VIP3I			MTK_M4U_ID(M4U_LARB2_ID, 16)
     60 #define M4U_PORT_LCEI			MTK_M4U_ID(M4U_LARB2_ID, 17)
     61 #define M4U_PORT_RB			MTK_M4U_ID(M4U_LARB2_ID, 18)
     62 #define M4U_PORT_RP			MTK_M4U_ID(M4U_LARB2_ID, 19)
     63 #define M4U_PORT_WR			MTK_M4U_ID(M4U_LARB2_ID, 20)
     64 
     65 /* larb3 */
     66 #define M4U_PORT_VENC_RCPU		MTK_M4U_ID(M4U_LARB3_ID, 0)
     67 #define M4U_PORT_VENC_REC		MTK_M4U_ID(M4U_LARB3_ID, 1)
     68 #define M4U_PORT_VENC_BSDMA		MTK_M4U_ID(M4U_LARB3_ID, 2)
     69 #define M4U_PORT_VENC_SV_COMV		MTK_M4U_ID(M4U_LARB3_ID, 3)
     70 #define M4U_PORT_VENC_RD_COMV		MTK_M4U_ID(M4U_LARB3_ID, 4)
     71 #define M4U_PORT_JPGENC_RDMA		MTK_M4U_ID(M4U_LARB3_ID, 5)
     72 #define M4U_PORT_JPGENC_BSDMA		MTK_M4U_ID(M4U_LARB3_ID, 6)
     73 #define M4U_PORT_JPGDEC_WDMA		MTK_M4U_ID(M4U_LARB3_ID, 7)
     74 #define M4U_PORT_JPGDEC_BSDMA		MTK_M4U_ID(M4U_LARB3_ID, 8)
     75 #define M4U_PORT_VENC_CUR_LUMA		MTK_M4U_ID(M4U_LARB3_ID, 9)
     76 #define M4U_PORT_VENC_CUR_CHROMA	MTK_M4U_ID(M4U_LARB3_ID, 10)
     77 #define M4U_PORT_VENC_REF_LUMA		MTK_M4U_ID(M4U_LARB3_ID, 11)
     78 #define M4U_PORT_VENC_REF_CHROMA	MTK_M4U_ID(M4U_LARB3_ID, 12)
     79 #define M4U_PORT_VENC_NBM_RDMA		MTK_M4U_ID(M4U_LARB3_ID, 13)
     80 #define M4U_PORT_VENC_NBM_WDMA		MTK_M4U_ID(M4U_LARB3_ID, 14)
     81 
     82 /* larb4 */
     83 #define M4U_PORT_DISP_OVL1		MTK_M4U_ID(M4U_LARB4_ID, 0)
     84 #define M4U_PORT_DISP_RDMA1		MTK_M4U_ID(M4U_LARB4_ID, 1)
     85 #define M4U_PORT_DISP_RDMA2		MTK_M4U_ID(M4U_LARB4_ID, 2)
     86 #define M4U_PORT_DISP_WDMA1		MTK_M4U_ID(M4U_LARB4_ID, 3)
     87 #define M4U_PORT_MDP_RDMA1		MTK_M4U_ID(M4U_LARB4_ID, 4)
     88 #define M4U_PORT_MDP_WROT1		MTK_M4U_ID(M4U_LARB4_ID, 5)
     89 
     90 /* larb5 */
     91 #define M4U_PORT_VENC_RCPU_SET2		MTK_M4U_ID(M4U_LARB5_ID, 0)
     92 #define M4U_PORT_VENC_REC_FRM_SET2	MTK_M4U_ID(M4U_LARB5_ID, 1)
     93 #define M4U_PORT_VENC_REF_LUMA_SET2	MTK_M4U_ID(M4U_LARB5_ID, 2)
     94 #define M4U_PORT_VENC_REC_CHROMA_SET2	MTK_M4U_ID(M4U_LARB5_ID, 3)
     95 #define M4U_PORT_VENC_BSDMA_SET2	MTK_M4U_ID(M4U_LARB5_ID, 4)
     96 #define M4U_PORT_VENC_CUR_LUMA_SET2	MTK_M4U_ID(M4U_LARB5_ID, 5)
     97 #define M4U_PORT_VENC_CUR_CHROMA_SET2	MTK_M4U_ID(M4U_LARB5_ID, 6)
     98 #define M4U_PORT_VENC_RD_COMA_SET2	MTK_M4U_ID(M4U_LARB5_ID, 7)
     99 #define M4U_PORT_VENC_SV_COMA_SET2	MTK_M4U_ID(M4U_LARB5_ID, 8)
    100 
    101 #endif
    102