1 /* $NetBSD: macereg.h,v 1.3 2007/04/13 03:36:24 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Soren S. Jorvang 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the 18 * NetBSD Project. See http://www.NetBSD.org/ for 19 * information about NetBSD. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #define MACE_BASE 0x1f000000 36 37 /* PCI definitions (offset 0x080000) */ 38 39 #define MACE_PCI_ERROR_ADDR 0x00 40 #define MACE_PCI_ERROR_FLAGS 0x04 41 42 #define MACE_PCI_CONTROL 0x08 43 #define MACE_PCI_CONTROL_INT_MASK 0x000000ff 44 #define MACE_PCI_CONTROL_SERR_ENA 0x00000100 45 #define MACE_PCI_CONTROL_ARB_N6 0x00000200 46 #define MACE_PCI_CONTROL_PARITY_ERR 0x00000400 47 #define MACE_PCI_CONTROL_MRMRA_ENA 0x00000800 48 #define MACE_PCI_CONTROL_ARB_N3 0x00001000 49 #define MACE_PCI_CONTROL_ARB_N4 0x00002000 50 #define MACE_PCI_CONTROL_ARB_N5 0x00004000 51 #define MACE_PCI_CONTROL_PARK_LIU 0x00008000 52 53 #define MACE_PCI_CONTROL_INV_INT_MASK 0x00ff0000 54 #define MACE_PCI_CONTROL_OVERRUN_INT 0x01000000 55 #define MACE_PCI_CONTROL_PARITY_INT 0x02000000 56 #define MACE_PCI_CONTROL_SERR_INT 0x04000000 57 #define MACE_PCI_CONTROL_IT_INT 0x08000000 58 #define MACE_PCI_CONTROL_RE_INT 0x10000000 59 #define MACE_PCI_CONTROL_DPED_INT 0x20000000 60 #define MACE_PCI_CONTROL_TAR_INT 0x40000000 61 #define MACE_PCI_CONTROL_MAR_INT 0x80000000 62 63 64 #define MACE_PCI_REV_INFO_R 0x0c 65 #define MACE_PCI_FLUSH_W 0x0c 66 #define MACE_PCI_CONFIG_ADDR 0xcf8 67 #define MACE_PCI_CONFIG_DATA 0xcfc 68 #define MACE_PCI_LOW_MEMORY 0x1a000000 69 #define MACE_PCI_LOW_IO 0x18000000 70 #define MACE_PCI_NATIVE_VIEW 0x40000000 71 #define MACE_PCI_IO 0x80000000 72 #define MACE_PCI_HI_MEMORY 0x280000000 73 #define MACE_PCI_HI_IO 0x100000000 74 75 #define MACE_VIN1 0x100000 76 #define MACE_VIN2 0x180000 77 #define MACE_VOUT 0x200000 78 #define MACE_PERIF 0x300000 79 #define MACE_ISA_EXT 0x380000 80 81 #define MACE_AUDIO (MACE_PERIF + 0x00000) 82 #define MACE_ISA (MACE_PERIF + 0x10000) 83 #define MACE_KBDMS (MACE_PERIF + 0x20000) 84 #define MACE_I2C (MACE_PERIF + 0x30000) 85 #define MACE_UST_MSC (MACE_PERIF + 0x40000) 86 87 88 89 /*********************** 90 * PCI_ERROR_FLAGS Bits 91 */ 92 #define MACE_PERR_MASTER_ABORT 0x80000000 93 #define MACE_PERR_TARGET_ABORT 0x40000000 94 #define MACE_PERR_DATA_PARITY_ERR 0x20000000 95 #define MACE_PERR_RETRY_ERR 0x10000000 96 #define MACE_PERR_ILLEGAL_CMD 0x08000000 97 #define MACE_PERR_SYSTEM_ERR 0x04000000 98 #define MACE_PERR_INTERRUPT_TEST 0x02000000 99 #define MACE_PERR_PARITY_ERR 0x01000000 100 #define MACE_PERR_OVERRUN 0x00800000 101 #define MACE_PERR_RSVD 0x00400000 102 #define MACE_PERR_MEMORY_ADDR 0x00200000 103 #define MACE_PERR_CONFIG_ADDR 0x00100000 104 #define MACE_PERR_MASTER_ABORT_ADDR_VALID 0x00080000 105 #define MACE_PERR_TARGET_ABORT_ADDR_VALID 0x00040000 106 #define MACE_PERR_DATA_PARITY_ADDR_VALID 0x00020000 107 #define MACE_PERR_RETRY_ADDR_VALID 0x00010000 108 109 110 /******************************* 111 * MACE ISA External Address Map 112 */ 113 #define MACE_ISA_EPP_BASE (MACE_ISA_EXT + 0x00000) 114 #define MACE_ISA_ECP_BASE (MACE_ISA_EXT + 0x08000) 115 #define MACE_ISA_SER1_BASE (MACE_ISA_EXT + 0x10000) 116 #define MACE_ISA_SER2_BASE (MACE_ISA_EXT + 0x18000) 117 #define MACE_ISA_RTC_BASE (MACE_ISA_EXT + 0x20000) 118 #define MACE_ISA_GAME_BASE (MACE_ISA_EXT + 0x30000) 119 120 121 /************************* 122 * ISA Interface Registers 123 */ 124 125 /* ISA Ringbase Address and Reset Register */ 126 127 #define MACE_ISA_RINGBASE (MACE_ISA + 0x0000) 128 #define MACE_ISA_RING_ALIGN 0x00010000 129 130 /* Flash-ROM/LED/DP-RAM/NIC Controller Register */ 131 132 #define MACE_ISA_FLASH_NIC_REG (MACE_ISA + 0x0008) 133 #define MACE_ISA_FLASH_WE 0x01 /* 1=> Enable FLASH writes */ 134 #define MACE_ISA_PWD_CLEAR 0x02 /* 1=> PWD CLEAR jumper detected */ 135 #define MACE_ISA_NIC_DEASSERT 0x04 136 #define MACE_ISA_NIC_DATA 0x08 137 #define MACE_ISA_LED_RED 0x10 /* 1=> Illuminate RED LED */ 138 #define MACE_ISA_LED_GREEN 0x20 /* 1=> Illuminate GREEN LED */ 139 #define MACE_ISA_DP_RAM_ENABLE 0x40 140 141 /* Interrupt Status and Mask Registers (32 bits) */ 142 143 #define MACE_ISA_INT_STATUS (MACE_ISA + 0x0010) 144 #define MACE_ISA_INT_MASK (MACE_ISA + 0x0018) 145 146 /* bit definitions */ 147 #define MACE_ISA_INT_RTC_IRQ 0x00000100 148 #define MACE_ISA_INT_AUDIO_SC 0x02 149 #define MACE_ISA_INT_AUDIO_DMA1 0x04 150 #define MACE_ISA_INT_AUDIO_DMA2 0x10 151 #define MACE_ISA_INT_AUDIO_DMA3 0x40 152 153 154 /******************************** 155 * MACE Timer Interface Registers 156 * 157 * Note: MSC_UST<31:0> is MSC, MSC_UST<63:32> is UST. 158 */ 159 #define MACE_UST (MACE_UST_MSC + 0x00) /* Universial system time */ 160 #define MACE_COMPARE1 (MACE_UST_MSC + 0x08) /* Interrupt compare reg 1 */ 161 #define MACE_COMPARE2 (MACE_UST_MSC + 0x10) /* Interrupt compare reg 2 */ 162 #define MACE_COMPARE3 (MACE_UST_MSC + 0x18) /* Interrupt compare reg 3 */ 163 #define MACE_UST_PERIOD 960 /* UST Period in ns */ 164 165 #define MACE_AIN_MSC_UST (MACE_UST_MSC + 0x20) /* Audio in MSC/UST pair */ 166 #define MACE_AOUT1_MSC_UST (MACE_UST_MSC + 0x28) /* Audio out 1 MSC/UST pair */ 167 #define MACE_AOUT2_MSC_UST (MACE_UST_MSC + 0x30) /* Audio out 2 MSC/UST pair */ 168 #define MACE_VIN1_MSC_UST (MACE_UST_MSC + 0x38) /* Video In 1 MSC/UST pair */ 169 #define MACE_VIN2_MSC_UST (MACE_UST_MSC + 0x40) /* Video In 2 MSC/UST pair */ 170 #define MACE_VOUT_MSC_UST (MACE_UST_MSC + 0x48) /* Video out MSC/UST pair */ 171
Indexes created Sat Sep 20 22:09:52 GMT 2025