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      1 /*	$NetBSD: mbareg.h,v 1.6 2017/05/22 17:13:09 ragge Exp $ */
      2 /*
      3  * Copyright (c) 1994 Ludd, University of Lule}, Sweden
      4  * All rights reserved.
      5  *
      6  * Redistribution and use in source and binary forms, with or without
      7  * modification, are permitted provided that the following conditions
      8  * are met:
      9  * 1. Redistributions of source code must retain the above copyright
     10  *    notice, this list of conditions and the following disclaimer.
     11  * 2. Redistributions in binary form must reproduce the above copyright
     12  *    notice, this list of conditions and the following disclaimer in the
     13  *    documentation and/or other materials provided with the distribution.
     14  *
     15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     20  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     21  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     22  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     23  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     24  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     25  */
     26 
     27 #ifdef notdef
     28 struct mba_hack {
     29 	u_int	pad1;
     30 	u_int	md_ds;		/* unit status */
     31 	u_int	pad4[2];
     32 	u_int	md_as;		/* Attention summary */
     33 	u_int	pad2;
     34 	u_int	md_dt;		/* unit type */
     35 	u_int	pad3[25];
     36 };
     37 
     38 struct mba_regs {
     39 	u_int	mba_csr;
     40 	u_int	mba_cr;
     41 	u_int	mba_sr;
     42 	u_int	mba_var;
     43 	u_int	mba_bc;
     44 	u_int	mba_dr;
     45 	u_int	mba_smr;
     46 	u_int	mba_car;
     47 	u_int	utrymme[248];
     48 	struct	mba_hack mba_md[8];	/* unit specific regs */
     49 	struct	pte mba_map[256];
     50 };
     51 #endif
     52 
     53 #define	MBA_CSR	0
     54 #define	MBA_CR	4
     55 #define	MBA_SR	8
     56 #define	MBA_VAR	12
     57 #define	MBA_BC	16
     58 #define	MBA_DR	20
     59 #define	MBA_SMR	24
     60 #define	MBA_CAR	28
     61 
     62 #define	MUREG(dev,reg)	(1024+(dev)*128+(reg))
     63 #define MAPREG(nr)	(2048+(nr)*4)
     64 
     65 #define	MU_DS	4	/* unit status */
     66 #define	MU_AS	16	/* attention summary */
     67 #define	MU_DT	24	/* drive type */
     68 
     69 /*
     70  * Different states which can be on massbus.
     71  */
     72 /* Write to mba_cr */
     73 #define	MBACR_IBC	0x10
     74 #define	MBACR_MMM	0x8
     75 #define	MBACR_IE	0x4
     76 #define	MBACR_ABORT	0x2
     77 #define	MBACR_INIT	0x1
     78 
     79 /* Read from mba_sr: */
     80 #define	MBASR_DTBUSY	0x80000000
     81 #define	MBASR_NRCONF	0x40000000
     82 #define	MBASR_CRD	0x20000000
     83 #define	MBASR_CBHUNG	0x800000
     84 #define MBASR_PGE	0x80000
     85 #define	MBASR_NED	0x40000		/* NonExistent Drive */
     86 #define	MBASR_MCPE	0x20000		/* Massbuss Control Parity Error */
     87 #define	MBASR_ATTN	0x10000		/* Attention from Massbus */
     88 #define	MBASR_SPE	0x4000		/* Silo Parity Error */
     89 #define MBASR_DTCMP	0x2000		/* Data Transfer CoMPleted */
     90 #define MBASR_DTABT	0x1000		/* Data Transfer ABorTed */
     91 #define MBASR_DLT	0x800		/* Data LaTe */
     92 #define MBASR_WCKUE	0x400		/* Write check upper error */
     93 #define	MBASR_WCKLE	0x200		/* Write check lower error */
     94 #define	MBASR_MXF	0x100		/* Miss transfer fault */
     95 #define	MBASR_MBEXC	0x80		/* Massbuss exception */
     96 #define	MBASR_MDPE	0x40		/* Massbuss data parity error */
     97 #define	MBASR_MAPPE	0x20		/* Page frame map parity error */
     98 #define	MBASR_INVMAP	0x10		/* Invalid map */
     99 #define MBASR_ERR_STAT	0x8		/* Error status */
    100 #define	MBASR_ERRC	0x4		/* Error confirmation */
    101 #define	MBASR_ISTIMO	0x2		/* Interface sequence timeout */
    102 #define	MBASR_RDTIMO	0x1		/* Read data timeout status */
    103 
    104 /* Definitions in mba_device md_ds */
    105 #define	MBADS_DPR	0x100		/* Unit present */
    106 
    107 /* Definitions in mba_device md_dt */
    108 #define	MBADT_RP04	0x2010
    109 #define MBADT_RP05	0x2011
    110 #define MBADT_RP06	0x2012
    111 #define MBADT_RP07	0x2022
    112 #define MBADT_RM02	0x2015
    113 #define MBADT_RM03	0x2014
    114 #define MBADT_RM05	0x2017
    115 #define MBADT_RM80	0x2016
    116 #define	MBADT_DRQ	0x800		/* Dual ported */
    117 #define	MBADT_MOH	0x2000		/* Moving head device */
    118