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    Searched defs:MCID (Results 1 - 25 of 57) sorted by relevancy

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  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZInstrBuilder.h 29 const MCInstrDesc &MCID = MI->getDesc();
31 if (MCID.mayLoad())
33 if (MCID.mayStore())
  /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/
M68kInstrBuilder.h 63 const MCInstrDesc &MCID = MI->getDesc();
65 if (MCID.mayLoad())
67 if (MCID.mayStore())
80 const MCInstrDesc &MCID = MI->getDesc();
82 if (MCID.mayLoad())
84 if (MCID.mayStore())
  /src/external/apache2/llvm/dist/llvm/lib/Target/VE/
LVLGen.cpp 41 const MCInstrDesc &MCID = TII->get(Opcode);
44 if (HAS_VLINDEX(MCID.TSFlags))
45 return GET_VLINDEX(MCID.TSFlags);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
ScoreboardHazardRecognizer.cpp 123 const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
124 if (!MCID) {
128 unsigned idx = MCID->getSchedClass();
178 const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
179 assert(MCID && "The scheduler must filter non-machineinstrs");
180 if (DAG->TII->isZeroCost(MCID->Opcode))
187 unsigned idx = MCID->getSchedClass();
BreakFalseDeps.cpp 189 const MCInstrDesc &MCID = MI->getDesc();
193 for (unsigned i = MCID.getNumDefs(), e = MCID.getNumOperands(); i != e; ++i) {
215 e = MI->isVariadic() ? MI->getNumOperands() : MCID.getNumDefs();
  /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/
LanaiDelaySlotFiller.cpp 229 MCInstrDesc MCID = MI->getDesc();
230 unsigned E = MI->isCall() || MI->isReturn() ? MCID.getNumOperands()
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
InstrEmitter.cpp 311 const MCInstrDesc &MCID = MIB->getDesc();
312 bool isOptDef = IIOpNum < MCID.getNumOperands() &&
313 MCID.OpInfo[IIOpNum].isOptionalDef();
358 bool isTied = MCID.getOperandConstraint(Idx, MCOI::TIED_TO) != -1;
1051 const MCInstrDesc &MCID = TII->get(F->getMachineOpcode());
1052 UsedRegs.append(MCID.getImplicitUses(),
1053 MCID.getImplicitUses() + MCID.getNumImplicitUses());
ScheduleDAGFast.cpp 254 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
255 for (unsigned i = 0; i != MCID.getNumOperands(); ++i) {
256 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) {
261 if (MCID.isCommutable())
432 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
433 assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!");
434 NumRes = MCID.getNumDefs();
435 for (const MCPhysReg *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) {
511 const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode());
512 if (!MCID.ImplicitDefs
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMHazardRecognizer.cpp 29 const MCInstrDesc &MCID = MI->getDesc();
30 unsigned Domain = MCID.TSFlags & ARMII::DomainMask;
33 unsigned Opcode = MCID.getOpcode();
50 const MCInstrDesc &MCID = MI->getDesc();
51 if (LastMI && (MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainGeneral) {
MLxExpansionPass.cpp 184 const MCInstrDesc &MCID = MI->getDesc();
185 unsigned Domain = MCID.TSFlags & ARMII::DomainMask;
188 unsigned Opcode = MCID.getOpcode();
339 const MCInstrDesc &MCID = MI->getDesc();
346 unsigned Domain = MCID.TSFlags & ARMII::DomainMask;
356 if (!TII->isFpMLxInstruction(MCID.getOpcode(),
Thumb2ITBlockPass.cpp 171 const MCInstrDesc &MCID = MI->getDesc();
173 MI->getOperand(MCID.getNumOperands() - 1).getReg() == ARM::CPSR)
ARMBaseRegisterInfo.cpp 659 const MCInstrDesc &MCID = TII.get(ADDriOpc);
661 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
663 MachineInstrBuilder MIB = BuildMI(*MBB, Ins, DL, MCID, BaseReg)
831 const MCInstrDesc &MCID = MI.getDesc();
833 TII.getRegClass(MCID, FIOperandNum, this, *MI.getParent()->getParent());
  /src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/
NVPTXReplaceImageHandles.cpp 81 const MCInstrDesc &MCID = MI.getDesc();
83 if (MCID.TSFlags & NVPTXII::IsTexFlag) {
89 if (!(MCID.TSFlags & NVPTXII::IsTexModeUnifiedFlag)) {
95 } else if (MCID.TSFlags & NVPTXII::IsSuldMask) {
97 1 << (((MCID.TSFlags & NVPTXII::IsSuldMask) >> NVPTXII::IsSuldShift) - 1);
105 } else if (MCID.TSFlags & NVPTXII::IsSustFlag) {
112 } else if (MCID.TSFlags & NVPTXII::IsSurfTexQueryFlag) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCHazardRecognizers.cpp 29 const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
30 if (!MCID)
33 if (!MCID->mayLoad())
55 const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
56 if (!MCID)
59 if (!MCID->isBranch())
85 bool PPCDispatchGroupSBHazardRecognizer::mustComeFirst(const MCInstrDesc *MCID,
90 unsigned IIC = MCID->getSchedClass();
123 if (NSlots == 1 && PPC::getNonRecordFormOpcode(MCID->getOpcode()) != -1)
147 const MCInstrDesc *MCID = DAG->getInstrDesc(SU)
    [all...]
PPCPreEmitPeephole.cpp 439 const MCInstrDesc &MCID = TII->get(Opc);
440 if (MCID.getNumOperands() == 3 &&
449 else if (MCID.getNumOperands() == 2 &&
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86InstrBuilder.h 202 const MCInstrDesc &MCID = MI->getDesc();
204 if (MCID.mayLoad())
206 if (MCID.mayStore())
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/
HexagonAsmBackend.cpp 539 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(*MCII, HMI);
544 MCID.isBranch()) ||
546 MCID.isBranch()) ||
HexagonMCCodeEmitter.cpp 465 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MI);
505 if (MCID.isBranch())
532 switch (MCID.getOpcode()) {
618 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MI);
622 unsigned Opc = MCID.getOpcode();
654 if (UsesGP(MCID))
665 bool BranchOrCR = MCID.isBranch() || IType == HexagonII::TypeCR;
HexagonMCChecker.cpp 90 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MCI);
95 for (unsigned i = MCID.getNumDefs(); i < MCID.getNumOperands(); ++i)
98 for (unsigned i = 0; i < MCID.getNumImplicitUses(); ++i)
99 initReg(MCI, MCID.getImplicitUses()[i], PredReg, isTrue);
102 if (const MCPhysReg *ImpDef = MCID.getImplicitDefs())
106 if (Hexagon::R31 != R && MCID.isCall())
131 for (unsigned i = 0; i < MCID.getNumDefs(); ++i) {
188 for (unsigned i = MCID.getNumDefs(); i < MCID.getNumOperands(); ++i
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsInstrInfo.cpp 110 const MCInstrDesc &MCID = get(Opc);
111 MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
687 const MCInstrDesc &MCID = MI.getDesc();
688 if (!MCID.isCommutable())
  /src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/
Assembler.cpp 96 const MCInstrDesc &MCID = MCII->get(Opcode);
97 MachineInstrBuilder Builder = BuildMI(MBB, DL, MCID);
102 const bool IsDef = OpIndex < MCID.getNumDefs();
104 const MCOperandInfo &OpInfo = MCID.operands().begin()[OpIndex];
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
LegalizerInfo.cpp 695 const MCInstrDesc &MCID = MII.get(Opcode);
697 MCID.opInfo_begin(), MCID.opInfo_end(), 0U,
704 MCID.opInfo_begin(), MCID.opInfo_end(), 0U,
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ConditionalCompares.cpp 632 const MCInstrDesc &MCID = TII->get(Opc);
635 MRI->createVirtualRegister(TII->getRegClass(MCID, 0, TRI, *MF));
637 BuildMI(*Head, Head->end(), TermDL, MCID)
644 TII->getRegClass(MCID, 1, TRI, *MF));
689 const MCInstrDesc &MCID = TII->get(Opc);
691 TII->getRegClass(MCID, 0, TRI, *MF));
694 TII->getRegClass(MCID, 1, TRI, *MF));
695 MachineInstrBuilder MIB = BuildMI(*Head, CmpMI, CmpMI->getDebugLoc(), MCID)
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/MCTargetDesc/
X86MCTargetDesc.cpp 536 const MCInstrDesc &MCID = Info->get(Inst.getOpcode());
537 int MemOpStart = X86II::getMemoryOperandNo(MCID.TSFlags);
540 MemOpStart += X86II::getOperandBias(MCID);
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
MachineInstr.h 116 const MCInstrDesc *MCID; // Instruction descriptor.
475 const MCInstrDesc &getDesc() const { return *MCID; }
478 unsigned getOpcode() const { return MCID->Opcode; }
557 return getNumExplicitDefs() + MCID->getNumImplicitDefs();
779 return hasProperty(MCID::PreISelOpcode, Type);
787 return hasProperty(MCID::Variadic, Type);
793 return hasProperty(MCID::HasOptionalDef, Type);
799 return hasProperty(MCID::Pseudo, Type);
803 return hasProperty(MCID::Return, Type);
809 return hasProperty(MCID::EHScopeReturn, Type)
    [all...]

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