1 /* $NetBSD: dcn10_dwb.h,v 1.2 2021/12/18 23:45:03 riastradh Exp $ */ 2 3 /* Copyright 2012-17 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 #ifndef __DC_DWBC_DCN10_H__ 27 #define __DC_DWBC_DCN10_H__ 28 29 #if defined(CONFIG_DRM_AMD_DC_DCN) 30 31 /* DCN */ 32 #define BASE_INNER(seg) \ 33 DCE_BASE__INST0_SEG ## seg 34 35 #define BASE(seg) \ 36 BASE_INNER(seg) 37 38 #define SR(reg_name)\ 39 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 40 mm ## reg_name 41 42 #define SRI(reg_name, block, id)\ 43 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 44 mm ## block ## id ## _ ## reg_name 45 46 47 #define SRII(reg_name, block, id)\ 48 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 49 mm ## block ## id ## _ ## reg_name 50 51 #define SF(reg_name, field_name, post_fix)\ 52 .field_name = reg_name ## __ ## field_name ## post_fix 53 54 55 #define DWBC_COMMON_REG_LIST_DCN1_0(inst) \ 56 SRI(WB_ENABLE, CNV, inst),\ 57 SRI(WB_EC_CONFIG, CNV, inst),\ 58 SRI(CNV_MODE, CNV, inst),\ 59 SRI(WB_SOFT_RESET, CNV, inst),\ 60 SRI(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\ 61 SRI(MCIF_WB_BUF_PITCH, MCIF_WB, inst),\ 62 SRI(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB, inst),\ 63 SRI(MCIF_WB_SCLK_CHANGE, MCIF_WB, inst),\ 64 SRI(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB, inst),\ 65 SRI(MCIF_WB_BUF_1_ADDR_Y_OFFSET, MCIF_WB, inst),\ 66 SRI(MCIF_WB_BUF_1_ADDR_C, MCIF_WB, inst),\ 67 SRI(MCIF_WB_BUF_1_ADDR_C_OFFSET, MCIF_WB, inst),\ 68 SRI(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB, inst),\ 69 SRI(MCIF_WB_BUF_2_ADDR_Y_OFFSET, MCIF_WB, inst),\ 70 SRI(MCIF_WB_BUF_2_ADDR_C, MCIF_WB, inst),\ 71 SRI(MCIF_WB_BUF_2_ADDR_C_OFFSET, MCIF_WB, inst),\ 72 SRI(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB, inst),\ 73 SRI(MCIF_WB_BUF_3_ADDR_Y_OFFSET, MCIF_WB, inst),\ 74 SRI(MCIF_WB_BUF_3_ADDR_C, MCIF_WB, inst),\ 75 SRI(MCIF_WB_BUF_3_ADDR_C_OFFSET, MCIF_WB, inst),\ 76 SRI(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB, inst),\ 77 SRI(MCIF_WB_BUF_4_ADDR_Y_OFFSET, MCIF_WB, inst),\ 78 SRI(MCIF_WB_BUF_4_ADDR_C, MCIF_WB, inst),\ 79 SRI(MCIF_WB_BUF_4_ADDR_C_OFFSET, MCIF_WB, inst),\ 80 SRI(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB, inst),\ 81 SRI(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, MCIF_WB, inst),\ 82 SRI(MCIF_WB_NB_PSTATE_CONTROL, MCIF_WB, inst),\ 83 SRI(MCIF_WB_WATERMARK, MCIF_WB, inst),\ 84 SRI(MCIF_WB_WARM_UP_CNTL, MCIF_WB, inst),\ 85 SRI(MCIF_WB_BUF_LUMA_SIZE, MCIF_WB, inst),\ 86 SRI(MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB, inst) 87 88 #define DWBC_COMMON_MASK_SH_LIST_DCN1_0(mask_sh) \ 89 SF(CNV0_WB_ENABLE, WB_ENABLE, mask_sh),\ 90 SF(CNV0_WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, mask_sh),\ 91 SF(CNV0_WB_EC_CONFIG, DISPCLK_G_WB_GATE_DIS, mask_sh),\ 92 SF(CNV0_WB_EC_CONFIG, DISPCLK_G_WBSCL_GATE_DIS, mask_sh),\ 93 SF(CNV0_WB_EC_CONFIG, WB_LB_LS_DIS, mask_sh),\ 94 SF(CNV0_WB_EC_CONFIG, WB_LUT_LS_DIS, mask_sh),\ 95 SF(CNV0_CNV_MODE, CNV_WINDOW_CROP_EN, mask_sh),\ 96 SF(CNV0_CNV_MODE, CNV_STEREO_TYPE, mask_sh),\ 97 SF(CNV0_CNV_MODE, CNV_INTERLACED_MODE, mask_sh),\ 98 SF(CNV0_CNV_MODE, CNV_EYE_SELECTION, mask_sh),\ 99 SF(CNV0_CNV_MODE, CNV_STEREO_POLARITY, mask_sh),\ 100 SF(CNV0_CNV_MODE, CNV_INTERLACED_FIELD_ORDER, mask_sh),\ 101 SF(CNV0_CNV_MODE, CNV_STEREO_SPLIT, mask_sh),\ 102 SF(CNV0_CNV_MODE, CNV_NEW_CONTENT, mask_sh),\ 103 SF(CNV0_CNV_MODE, CNV_FRAME_CAPTURE_EN, mask_sh),\ 104 SF(CNV0_WB_SOFT_RESET, WB_SOFT_RESET, mask_sh),\ 105 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, mask_sh),\ 106 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_DUALSIZE_REQ, mask_sh),\ 107 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_EN, mask_sh),\ 108 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_ACK, mask_sh),\ 109 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_SLICE_INT_EN, mask_sh),\ 110 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN, mask_sh),\ 111 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, mask_sh),\ 112 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_P_VMID, mask_sh),\ 113 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, mask_sh),\ 114 SF(MCIF_WB0_MCIF_WB_BUF_PITCH, MCIF_WB_BUF_LUMA_PITCH, mask_sh),\ 115 SF(MCIF_WB0_MCIF_WB_BUF_PITCH, MCIF_WB_BUF_CHROMA_PITCH, mask_sh),\ 116 SF(MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_CLIENT_ARBITRATION_SLICE, mask_sh),\ 117 SF(MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_TIME_PER_PIXEL, mask_sh),\ 118 SF(MCIF_WB0_MCIF_WB_SCLK_CHANGE, WM_CHANGE_ACK_FORCE_ON, mask_sh),\ 119 SF(MCIF_WB0_MCIF_WB_SCLK_CHANGE, MCIF_WB_CLI_WATERMARK_MASK, mask_sh),\ 120 SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, mask_sh),\ 121 SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET, MCIF_WB_BUF_1_ADDR_Y_OFFSET, mask_sh),\ 122 SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_C, MCIF_WB_BUF_1_ADDR_C, mask_sh),\ 123 SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET, MCIF_WB_BUF_1_ADDR_C_OFFSET, mask_sh),\ 124 SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y, MCIF_WB_BUF_2_ADDR_Y, mask_sh),\ 125 SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET, MCIF_WB_BUF_2_ADDR_Y_OFFSET, mask_sh),\ 126 SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_C, MCIF_WB_BUF_2_ADDR_C, mask_sh),\ 127 SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET, MCIF_WB_BUF_2_ADDR_C_OFFSET, mask_sh),\ 128 SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y, MCIF_WB_BUF_3_ADDR_Y, mask_sh),\ 129 SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET, MCIF_WB_BUF_3_ADDR_Y_OFFSET, mask_sh),\ 130 SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_C, MCIF_WB_BUF_3_ADDR_C, mask_sh),\ 131 SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET, MCIF_WB_BUF_3_ADDR_C_OFFSET, mask_sh),\ 132 SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y, MCIF_WB_BUF_4_ADDR_Y, mask_sh),\ 133 SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET, MCIF_WB_BUF_4_ADDR_Y_OFFSET, mask_sh),\ 134 SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_C, MCIF_WB_BUF_4_ADDR_C, mask_sh),\ 135 SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET, MCIF_WB_BUF_4_ADDR_C_OFFSET, mask_sh),\ 136 SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_LOCK_IGNORE, mask_sh),\ 137 SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_INT_EN, mask_sh),\ 138 SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_INT_ACK, mask_sh),\ 139 SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_SLICE_INT_EN, mask_sh),\ 140 SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_LOCK, mask_sh),\ 141 SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_SLICE_SIZE, mask_sh),\ 142 SF(MCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, NB_PSTATE_CHANGE_REFRESH_WATERMARK, mask_sh),\ 143 SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_URGENT_DURING_REQUEST, mask_sh),\ 144 SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_FORCE_ON, mask_sh),\ 145 SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_ALLOW_FOR_URGENT, mask_sh),\ 146 SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\ 147 SF(MCIF_WB0_MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, mask_sh),\ 148 SF(MCIF_WB0_MCIF_WB_WARM_UP_CNTL, MCIF_WB_PITCH_SIZE_WARMUP, mask_sh),\ 149 SF(MCIF_WB0_MCIF_WB_BUF_LUMA_SIZE, MCIF_WB_BUF_LUMA_SIZE, mask_sh),\ 150 SF(MCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB_BUF_CHROMA_SIZE, mask_sh) 151 152 #define DWBC_REG_FIELD_LIST(type) \ 153 type WB_ENABLE;\ 154 type DISPCLK_R_WB_GATE_DIS;\ 155 type DISPCLK_G_WB_GATE_DIS;\ 156 type DISPCLK_G_WBSCL_GATE_DIS;\ 157 type WB_LB_LS_DIS;\ 158 type WB_LB_SD_DIS;\ 159 type WB_LUT_LS_DIS;\ 160 type CNV_WINDOW_CROP_EN;\ 161 type CNV_STEREO_TYPE;\ 162 type CNV_INTERLACED_MODE;\ 163 type CNV_EYE_SELECTION;\ 164 type CNV_STEREO_POLARITY;\ 165 type CNV_INTERLACED_FIELD_ORDER;\ 166 type CNV_STEREO_SPLIT;\ 167 type CNV_NEW_CONTENT;\ 168 type CNV_FRAME_CAPTURE_EN;\ 169 type WB_SOFT_RESET;\ 170 type MCIF_WB_BUFMGR_ENABLE;\ 171 type MCIF_WB_BUF_DUALSIZE_REQ;\ 172 type MCIF_WB_BUFMGR_SW_INT_EN;\ 173 type MCIF_WB_BUFMGR_SW_INT_ACK;\ 174 type MCIF_WB_BUFMGR_SW_SLICE_INT_EN;\ 175 type MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN;\ 176 type MCIF_WB_BUFMGR_SW_LOCK;\ 177 type MCIF_WB_P_VMID;\ 178 type MCIF_WB_BUF_ADDR_FENCE_EN;\ 179 type MCIF_WB_BUF_LUMA_PITCH;\ 180 type MCIF_WB_BUF_CHROMA_PITCH;\ 181 type MCIF_WB_CLIENT_ARBITRATION_SLICE;\ 182 type MCIF_WB_TIME_PER_PIXEL;\ 183 type WM_CHANGE_ACK_FORCE_ON;\ 184 type MCIF_WB_CLI_WATERMARK_MASK;\ 185 type MCIF_WB_BUF_1_ADDR_Y;\ 186 type MCIF_WB_BUF_1_ADDR_Y_OFFSET;\ 187 type MCIF_WB_BUF_1_ADDR_C;\ 188 type MCIF_WB_BUF_1_ADDR_C_OFFSET;\ 189 type MCIF_WB_BUF_2_ADDR_Y;\ 190 type MCIF_WB_BUF_2_ADDR_Y_OFFSET;\ 191 type MCIF_WB_BUF_2_ADDR_C;\ 192 type MCIF_WB_BUF_2_ADDR_C_OFFSET;\ 193 type MCIF_WB_BUF_3_ADDR_Y;\ 194 type MCIF_WB_BUF_3_ADDR_Y_OFFSET;\ 195 type MCIF_WB_BUF_3_ADDR_C;\ 196 type MCIF_WB_BUF_3_ADDR_C_OFFSET;\ 197 type MCIF_WB_BUF_4_ADDR_Y;\ 198 type MCIF_WB_BUF_4_ADDR_Y_OFFSET;\ 199 type MCIF_WB_BUF_4_ADDR_C;\ 200 type MCIF_WB_BUF_4_ADDR_C_OFFSET;\ 201 type MCIF_WB_BUFMGR_VCE_LOCK_IGNORE;\ 202 type MCIF_WB_BUFMGR_VCE_INT_EN;\ 203 type MCIF_WB_BUFMGR_VCE_INT_ACK;\ 204 type MCIF_WB_BUFMGR_VCE_SLICE_INT_EN;\ 205 type MCIF_WB_BUFMGR_VCE_LOCK;\ 206 type MCIF_WB_BUFMGR_SLICE_SIZE;\ 207 type NB_PSTATE_CHANGE_REFRESH_WATERMARK;\ 208 type NB_PSTATE_CHANGE_URGENT_DURING_REQUEST;\ 209 type NB_PSTATE_CHANGE_FORCE_ON;\ 210 type NB_PSTATE_ALLOW_FOR_URGENT;\ 211 type NB_PSTATE_CHANGE_WATERMARK_MASK;\ 212 type MCIF_WB_CLI_WATERMARK;\ 213 type MCIF_WB_CLI_CLOCK_GATER_OVERRIDE;\ 214 type MCIF_WB_PITCH_SIZE_WARMUP;\ 215 type MCIF_WB_BUF_LUMA_SIZE;\ 216 type MCIF_WB_BUF_CHROMA_SIZE;\ 217 218 struct dcn10_dwbc_registers { 219 uint32_t WB_ENABLE; 220 uint32_t WB_EC_CONFIG; 221 uint32_t CNV_MODE; 222 uint32_t WB_SOFT_RESET; 223 uint32_t MCIF_WB_BUFMGR_SW_CONTROL; 224 uint32_t MCIF_WB_BUF_PITCH; 225 uint32_t MCIF_WB_ARBITRATION_CONTROL; 226 uint32_t MCIF_WB_SCLK_CHANGE; 227 uint32_t MCIF_WB_BUF_1_ADDR_Y; 228 uint32_t MCIF_WB_BUF_1_ADDR_Y_OFFSET; 229 uint32_t MCIF_WB_BUF_1_ADDR_C; 230 uint32_t MCIF_WB_BUF_1_ADDR_C_OFFSET; 231 uint32_t MCIF_WB_BUF_2_ADDR_Y; 232 uint32_t MCIF_WB_BUF_2_ADDR_Y_OFFSET; 233 uint32_t MCIF_WB_BUF_2_ADDR_C; 234 uint32_t MCIF_WB_BUF_2_ADDR_C_OFFSET; 235 uint32_t MCIF_WB_BUF_3_ADDR_Y; 236 uint32_t MCIF_WB_BUF_3_ADDR_Y_OFFSET; 237 uint32_t MCIF_WB_BUF_3_ADDR_C; 238 uint32_t MCIF_WB_BUF_3_ADDR_C_OFFSET; 239 uint32_t MCIF_WB_BUF_4_ADDR_Y; 240 uint32_t MCIF_WB_BUF_4_ADDR_Y_OFFSET; 241 uint32_t MCIF_WB_BUF_4_ADDR_C; 242 uint32_t MCIF_WB_BUF_4_ADDR_C_OFFSET; 243 uint32_t MCIF_WB_BUFMGR_VCE_CONTROL; 244 uint32_t MCIF_WB_NB_PSTATE_LATENCY_WATERMARK; 245 uint32_t MCIF_WB_NB_PSTATE_CONTROL; 246 uint32_t MCIF_WB_WATERMARK; 247 uint32_t MCIF_WB_WARM_UP_CNTL; 248 uint32_t MCIF_WB_BUF_LUMA_SIZE; 249 uint32_t MCIF_WB_BUF_CHROMA_SIZE; 250 }; 251 struct dcn10_dwbc_mask { 252 DWBC_REG_FIELD_LIST(uint32_t) 253 }; 254 struct dcn10_dwbc_shift { 255 DWBC_REG_FIELD_LIST(uint8_t) 256 }; 257 struct dcn10_dwbc { 258 struct dwbc base; 259 const struct dcn10_dwbc_registers *dwbc_regs; 260 const struct dcn10_dwbc_shift *dwbc_shift; 261 const struct dcn10_dwbc_mask *dwbc_mask; 262 }; 263 264 void dcn10_dwbc_construct(struct dcn10_dwbc *dwbc10, 265 struct dc_context *ctx, 266 const struct dcn10_dwbc_registers *dwbc_regs, 267 const struct dcn10_dwbc_shift *dwbc_shift, 268 const struct dcn10_dwbc_mask *dwbc_mask, 269 int inst); 270 271 #endif 272 273 #endif 274
Indexes created Mon Sep 29 03:10:08 GMT 2025