1 /* $NetBSD: meshreg.h,v 1.2 2000/10/23 21:04:28 tsubai Exp $ */ 2 3 /*- 4 * Copyright (C) 1999 Internet Research Institute, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by 18 * Internet Research Institute, Inc. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* MESH register offsets */ 35 #define MESH_XFER_COUNT0 0x00 /* transfer count (low) */ 36 #define MESH_XFER_COUNT1 0x10 /* transfer count (high) */ 37 #define MESH_FIFO 0x20 /* FIFO (16byte depth) */ 38 #define MESH_SEQUENCE 0x30 /* command register */ 39 #define MESH_BUS_STATUS0 0x40 40 #define MESH_BUS_STATUS1 0x50 41 #define MESH_FIFO_COUNT 0x60 42 #define MESH_EXCEPTION 0x70 43 #define MESH_ERROR 0x80 44 #define MESH_INTR_MASK 0x90 45 #define MESH_INTERRUPT 0xa0 46 #define MESH_SOURCE_ID 0xb0 47 #define MESH_DEST_ID 0xc0 48 #define MESH_SYNC_PARAM 0xd0 49 #define MESH_MESH_ID 0xe0 /* MESH version */ 50 #define MESH_SEL_TIMEOUT 0xf0 /* selection timeout delay */ 51 52 #define MESH_SIGNATURE 0xe2 /* XXX wrong! */ 53 54 /* MESH commands */ 55 #define MESH_CMD_ARBITRATE 0x01 56 #define MESH_CMD_SELECT 0x02 57 #define MESH_CMD_COMMAND 0x03 58 #define MESH_CMD_STATUS 0x04 59 #define MESH_CMD_DATAOUT 0x05 60 #define MESH_CMD_DATAIN 0x06 61 #define MESH_CMD_MSGOUT 0x07 62 #define MESH_CMD_MSGIN 0x08 63 #define MESH_CMD_BUSFREE 0x09 64 #define MESH_CMD_ENABLE_PARITY 0x0A 65 #define MESH_CMD_DISABLE_PARITY 0x0B 66 #define MESH_CMD_ENABLE_RESEL 0x0C 67 #define MESH_CMD_DISABLE_RESEL 0x0D 68 #define MESH_CMD_RESET_MESH 0x0E 69 #define MESH_CMD_FLUSH_FIFO 0x0F 70 #define MESH_SEQ_DMA 0x80 71 #define MESH_SEQ_TARGET 0x40 72 #define MESH_SEQ_ATN 0x20 73 #define MESH_SEQ_ACTNEG 0x10 74 75 /* INTERRUPT/INTR_MASK register bits */ 76 #define MESH_INTR_ERROR 0x04 77 #define MESH_INTR_EXCEPTION 0x02 78 #define MESH_INTR_CMDDONE 0x01 79 80 /* EXCEPTION register bits */ 81 #define MESH_EXC_SELATN 0x20 /* selected and ATN asserted (T) */ 82 #define MESH_EXC_SELECTED 0x10 /* selected (T) */ 83 #define MESH_EXC_RESEL 0x08 /* reselected */ 84 #define MESH_EXC_ARBLOST 0x04 /* arbitration lost */ 85 #define MESH_EXC_PHASEMM 0x02 /* phase mismatch */ 86 #define MESH_EXC_SELTO 0x01 /* selection timeout */ 87 88 #define MESH_EXC_BITMASK \ 89 "\20\06SELATN\05SELECTED\04RESEL\03ARBLOST\02PHASEMM\01SELTO" 90 91 /* ERROR register bits */ 92 #define MESH_ERR_DISCONNECT 0x40 /* unexpected disconnect */ 93 #define MESH_ERR_SCSI_RESET 0x20 /* Rst signal asserted */ 94 #define MESH_ERR_SEQERR 0x10 /* sequence error */ 95 #define MESH_ERR_PARITY_ERR3 0x08 /* parity error */ 96 #define MESH_ERR_PARITY_ERR2 0x04 97 #define MESH_ERR_PARITY_ERR1 0x02 98 #define MESH_ERR_PARITY_ERR0 0x01 99 100 #define MESH_ERR_BITMASK \ 101 "\20\07DISCON\06RESET\05SEQERR\04PAR3\03PAR2\02PAR1\01PAR0" 102 103 /* BUS_STATUS0 status bits */ 104 #define MESH_STATUS0_REQ32 0x80 105 #define MESH_STATUS0_ACK32 0x40 106 #define MESH_STATUS0_REQ 0x20 107 #define MESH_STATUS0_ACK 0x10 108 #define MESH_STATUS0_ATN 0x08 109 #define MESH_STATUS0_MSG 0x04 110 #define MESH_STATUS0_CD 0x02 111 #define MESH_STATUS0_IO 0x01 112 113 #define MESH_STATUS0_BITMASK "\20\06REQ\05ACK\04ATN\03MSG\02CD\01IO" 114 115 /* BUS_STATUS1 status bits */ 116 #define MESH_STATUS1_RST 0x80 117 #define MESH_STATUS1_BSY 0x40 118 #define MESH_STATUS1_SEL 0x20 119 120 #define MESH_STATUS1_BITMASK "\20\10RST\07BSY\06SEL" 121
Indexes created Mon Sep 22 21:09:42 GMT 2025