1 /* $NetBSD: mesong12_clkc.h,v 1.2 2024/02/07 04:20:26 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2021 Ryo Shimizu 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS 17 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 25 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #ifndef _MESONG12_CLKC_H 30 #define _MESONG12_CLKC_H 31 32 /* 33 * CLOCK IDs. 34 * The values are matched to those in dt-bindings/clock/g12a-clkc.h , 35 * but some are only defined locally. 36 */ 37 #define MESONG12_CLOCK_SYS_PLL 0 38 #define MESONG12_CLOCK_FIXED_PLL 1 39 #define MESONG12_CLOCK_FCLK_DIV2 2 40 #define MESONG12_CLOCK_FCLK_DIV3 3 41 #define MESONG12_CLOCK_FCLK_DIV4 4 42 #define MESONG12_CLOCK_FCLK_DIV5 5 43 #define MESONG12_CLOCK_FCLK_DIV7 6 44 #define MESONG12_CLOCK_GP0_PLL 7 45 46 #define MESONG12_CLOCK_CLK81 10 47 #define MESONG12_CLOCK_MPLL0 11 48 #define MESONG12_CLOCK_MPLL1 12 49 #define MESONG12_CLOCK_MPLL2 13 50 #define MESONG12_CLOCK_MPLL3 14 51 #define MESONG12_CLOCK_DDR 15 52 #define MESONG12_CLOCK_DOS 16 53 #define MESONG12_CLOCK_AUDIO_LOCKER 17 54 #define MESONG12_CLOCK_MIPI_DSI_HOST 18 55 #define MESONG12_CLOCK_ETH_PHY 19 56 #define MESONG12_CLOCK_ISA 20 57 #define MESONG12_CLOCK_PL301 21 58 #define MESONG12_CLOCK_PERIPHS 22 59 #define MESONG12_CLOCK_SPICC0 23 60 #define MESONG12_CLOCK_I2C 24 61 #define MESONG12_CLOCK_SANA 25 62 #define MESONG12_CLOCK_SD 26 63 #define MESONG12_CLOCK_RNG0 27 64 #define MESONG12_CLOCK_UART0 28 65 #define MESONG12_CLOCK_SPICC1 29 66 #define MESONG12_CLOCK_HIU_IFACE 30 67 #define MESONG12_CLOCK_MIPI_DSI_PHY 31 68 #define MESONG12_CLOCK_ASSIST_MISC 32 69 #define MESONG12_CLOCK_SD_EMMC_A 33 70 #define MESONG12_CLOCK_SD_EMMC_B 34 71 #define MESONG12_CLOCK_SD_EMMC_C 35 72 #define MESONG12_CLOCK_AUDIO_CODEC 36 73 #define MESONG12_CLOCK_AUDIO 37 74 #define MESONG12_CLOCK_ETH 38 75 #define MESONG12_CLOCK_DEMUX 39 76 #define MESONG12_CLOCK_AUDIO_IFIFO 40 77 #define MESONG12_CLOCK_ADC 41 78 #define MESONG12_CLOCK_UART1 42 79 #define MESONG12_CLOCK_G2D 43 80 #define MESONG12_CLOCK_RESET 44 81 #define MESONG12_CLOCK_PCIE_COMB 45 82 #define MESONG12_CLOCK_PARSER 46 83 #define MESONG12_CLOCK_USB 47 84 #define MESONG12_CLOCK_PCIE_PHY 48 85 #define MESONG12_CLOCK_AHB_ARB0 49 86 #define MESONG12_CLOCK_AHB_DATA_BUS 50 87 #define MESONG12_CLOCK_AHB_CTRL_BUS 51 88 #define MESONG12_CLOCK_HTX_HDCP22 52 89 #define MESONG12_CLOCK_HTX_PCLK 53 90 #define MESONG12_CLOCK_BT656 54 91 #define MESONG12_CLOCK_USB1_DDR_BRIDGE 55 92 #define MESONG12_CLOCK_MMC_PCLK 56 93 #define MESONG12_CLOCK_UART2 57 94 #define MESONG12_CLOCK_VPU_INTR 58 95 #define MESONG12_CLOCK_GIC 59 96 #define MESONG12_CLOCK_SD_EMMC_A_CLK0 60 97 #define MESONG12_CLOCK_SD_EMMC_B_CLK0 61 98 #define MESONG12_CLOCK_SD_EMMC_C_CLK0 62 99 100 #define MESONG12_CLOCK_HIFI_PLL 74 101 102 #define MESONG12_CLOCK_VCLK2_VENCI0 80 103 #define MESONG12_CLOCK_VCLK2_VENCI1 81 104 #define MESONG12_CLOCK_VCLK2_VENCP0 82 105 #define MESONG12_CLOCK_VCLK2_VENCP1 83 106 #define MESONG12_CLOCK_VCLK2_VENCT0 84 107 #define MESONG12_CLOCK_VCLK2_VENCT1 85 108 #define MESONG12_CLOCK_VCLK2_OTHER 86 109 #define MESONG12_CLOCK_VCLK2_ENCI 87 110 #define MESONG12_CLOCK_VCLK2_ENCP 88 111 #define MESONG12_CLOCK_DAC_CLK 89 112 #define MESONG12_CLOCK_AOCLK 90 113 #define MESONG12_CLOCK_IEC958 91 114 #define MESONG12_CLOCK_ENC480P 92 115 #define MESONG12_CLOCK_RNG1 93 116 #define MESONG12_CLOCK_VCLK2_ENCT 94 117 #define MESONG12_CLOCK_VCLK2_ENCL 95 118 #define MESONG12_CLOCK_VCLK2_VENCLMMC 96 119 #define MESONG12_CLOCK_VCLK2_VENCL 97 120 #define MESONG12_CLOCK_VCLK2_OTHER1 98 121 #define MESONG12_CLOCK_FCLK_DIV2P5 99 122 123 #define MESONG12_CLOCK_DMA 105 124 #define MESONG12_CLOCK_EFUSE 106 125 #define MESONG12_CLOCK_ROM_BOOT 107 126 #define MESONG12_CLOCK_RESET_SEC 108 127 #define MESONG12_CLOCK_SEC_AHB_APB3 109 128 #define MESONG12_CLOCK_VPU_0_SEL 110 129 130 #define MESONG12_CLOCK_VPU_0 112 131 #define MESONG12_CLOCK_VPU_1_SEL 113 132 133 #define MESONG12_CLOCK_VPU_1 115 134 #define MESONG12_CLOCK_VPU 116 135 #define MESONG12_CLOCK_VAPB_0_SEL 117 136 137 #define MESONG12_CLOCK_VAPB_0 119 138 #define MESONG12_CLOCK_VAPB_1_SEL 120 139 140 #define MESONG12_CLOCK_VAPB_1 122 141 #define MESONG12_CLOCK_VAPB_SEL 123 142 #define MESONG12_CLOCK_VAPB 124 143 144 #define MESONG12_CLOCK_HDMI_PLL 128 145 #define MESONG12_CLOCK_VID_PLL 129 146 147 #define MESONG12_CLOCK_VCLK 138 148 #define MESONG12_CLOCK_VCLK2 139 149 150 #define MESONG12_CLOCK_VCLK_DIV1 148 151 #define MESONG12_CLOCK_VCLK_DIV2 149 152 #define MESONG12_CLOCK_VCLK_DIV4 150 153 #define MESONG12_CLOCK_VCLK_DIV6 151 154 #define MESONG12_CLOCK_VCLK_DIV12 152 155 #define MESONG12_CLOCK_VCLK2_DIV1 153 156 #define MESONG12_CLOCK_VCLK2_DIV2 154 157 #define MESONG12_CLOCK_VCLK2_DIV4 155 158 #define MESONG12_CLOCK_VCLK2_DIV6 156 159 #define MESONG12_CLOCK_VCLK2_DIV12 157 160 161 #define MESONG12_CLOCK_CTS_ENCI 162 162 #define MESONG12_CLOCK_CTS_ENCP 163 163 #define MESONG12_CLOCK_CTS_VDAC 164 164 #define MESONG12_CLOCK_HDMI_TX 165 165 166 #define MESONG12_CLOCK_HDMI 168 167 #define MESONG12_CLOCK_MALI_0_SEL 169 168 169 #define MESONG12_CLOCK_MALI_0 171 170 #define MESONG12_CLOCK_MALI_1_SEL 172 171 172 #define MESONG12_CLOCK_MALI_1 174 173 #define MESONG12_CLOCK_MALI 175 174 175 #define MESONG12_CLOCK_MPLL_50M 177 176 177 #define MESONG12_CLOCK_CPU_CLK 187 178 179 #define MESONG12_CLOCK_PCIE_PLL 201 180 181 #define MESONG12_CLOCK_VDEC_1 204 182 183 #define MESONG12_CLOCK_VDEC_HEVC 207 184 185 #define MESONG12_CLOCK_VDEC_HEVCF 210 186 187 #define MESONG12_CLOCK_TS 212 188 189 #define MESONG12_CLOCK_CPUB_CLK 224 190 191 #define MESONG12_CLOCK_GP1_PLL 243 192 193 #define MESONG12_CLOCK_DSU_CLK 252 194 #define MESONG12_CLOCK_CPU1_CLK 253 195 #define MESONG12_CLOCK_CPU2_CLK 254 196 #define MESONG12_CLOCK_CPU3_CLK 255 197 198 199 /* 200 * locally defined 201 */ 202 #define MESONG12_CLOCK_MPEG_SEL 8 203 #define MESONG12_CLOCK_MPEG_DIV 9 204 205 #define MESONG12_CLOCK_SD_EMMC_A_CLK0_SEL 63 206 #define MESONG12_CLOCK_SD_EMMC_A_CLK0_DIV 64 207 #define MESONG12_CLOCK_SD_EMMC_B_CLK0_SEL 65 208 #define MESONG12_CLOCK_SD_EMMC_B_CLK0_DIV 66 209 #define MESONG12_CLOCK_SD_EMMC_C_CLK0_SEL 67 210 #define MESONG12_CLOCK_SD_EMMC_C_CLK0_DIV 68 211 #define MESONG12_CLOCK_MPLL0_DIV 69 212 #define MESONG12_CLOCK_MPLL1_DIV 70 213 #define MESONG12_CLOCK_MPLL2_DIV 71 214 #define MESONG12_CLOCK_MPLL3_DIV 72 215 #define MESONG12_CLOCK_MPLL_PREDIV 73 216 #define MESONG12_CLOCK_FCLK_DIV2_DIV 75 217 #define MESONG12_CLOCK_FCLK_DIV3_DIV 76 218 #define MESONG12_CLOCK_FCLK_DIV4_DIV 77 219 #define MESONG12_CLOCK_FCLK_DIV5_DIV 78 220 #define MESONG12_CLOCK_FCLK_DIV7_DIV 79 221 #define MESONG12_CLOCK_FCLK_DIV2P5_DIV 100 222 #define MESONG12_CLOCK_FIXED_PLL_DCO 101 223 #define MESONG12_CLOCK_SYS_PLL_DCO 102 224 #define MESONG12_CLOCK_GP0_PLL_DCO 103 225 #define MESONG12_CLOCK_HIFI_PLL_DCO 104 226 #define MESONG12_CLOCK_VPU_0_DIV 111 227 #define MESONG12_CLOCK_VPU_1_DIV 114 228 #define MESONG12_CLOCK_VAPB_0_DIV 118 229 #define MESONG12_CLOCK_VAPB_1_DIV 121 230 #define MESONG12_CLOCK_HDMI_PLL_DCO 125 231 #define MESONG12_CLOCK_HDMI_PLL_OD 126 232 #define MESONG12_CLOCK_HDMI_PLL_OD2 127 233 #define MESONG12_CLOCK_VID_PLL_SEL 130 234 #define MESONG12_CLOCK_VID_PLL_DIV 131 235 #define MESONG12_CLOCK_VCLK_SEL 132 236 #define MESONG12_CLOCK_VCLK2_SEL 133 237 #define MESONG12_CLOCK_VCLK_INPUT 134 238 #define MESONG12_CLOCK_VCLK2_INPUT 135 239 #define MESONG12_CLOCK_VCLK_DIV 136 240 #define MESONG12_CLOCK_VCLK2_DIV 137 241 #define MESONG12_CLOCK_VCLK_DIV2_EN 140 242 #define MESONG12_CLOCK_VCLK_DIV4_EN 141 243 #define MESONG12_CLOCK_VCLK_DIV6_EN 142 244 #define MESONG12_CLOCK_VCLK_DIV12_EN 143 245 #define MESONG12_CLOCK_VCLK2_DIV2_EN 144 246 #define MESONG12_CLOCK_VCLK2_DIV4_EN 145 247 #define MESONG12_CLOCK_VCLK2_DIV6_EN 146 248 #define MESONG12_CLOCK_VCLK2_DIV12_EN 147 249 #define MESONG12_CLOCK_CTS_ENCI_SEL 158 250 #define MESONG12_CLOCK_CTS_ENCP_SEL 159 251 #define MESONG12_CLOCK_CTS_VDAC_SEL 160 252 #define MESONG12_CLOCK_HDMI_TX_SEL 161 253 #define MESONG12_CLOCK_HDMI_SEL 166 254 #define MESONG12_CLOCK_HDMI_DIV 167 255 #define MESONG12_CLOCK_MALI_0_DIV 170 256 #define MESONG12_CLOCK_MALI_1_DIV 173 257 #define MESONG12_CLOCK_MPLL_50M_DIV 176 258 #define MESONG12_CLOCK_SYS_PLL_DIV16_EN 178 259 #define MESONG12_CLOCK_SYS_PLL_DIV16 179 260 #define MESONG12_CLOCK_CPU_CLK_DYN0_SEL 180 261 #define MESONG12_CLOCK_CPU_CLK_DYN0_DIV 181 262 #define MESONG12_CLOCK_CPU_CLK_DYN0 182 263 #define MESONG12_CLOCK_CPU_CLK_DYN1_SEL 183 264 #define MESONG12_CLOCK_CPU_CLK_DYN1_DIV 184 265 #define MESONG12_CLOCK_CPU_CLK_DYN1 185 266 #define MESONG12_CLOCK_CPU_CLK_DYN 186 267 #define MESONG12_CLOCK_CPU_CLK_DIV16_EN 188 268 #define MESONG12_CLOCK_CPU_CLK_DIV16 189 269 #define MESONG12_CLOCK_CPU_CLK_APB_DIV 190 270 #define MESONG12_CLOCK_CPU_CLK_APB 191 271 #define MESONG12_CLOCK_CPU_CLK_ATB_DIV 192 272 #define MESONG12_CLOCK_CPU_CLK_ATB 193 273 #define MESONG12_CLOCK_CPU_CLK_AXI_DIV 194 274 #define MESONG12_CLOCK_CPU_CLK_AXI 195 275 #define MESONG12_CLOCK_CPU_CLK_TRACE_DIV 196 276 #define MESONG12_CLOCK_CPU_CLK_TRACE 197 277 #define MESONG12_CLOCK_PCIE_PLL_DCO 198 278 #define MESONG12_CLOCK_PCIE_PLL_DCO_DIV2 199 279 #define MESONG12_CLOCK_PCIE_PLL_OD 200 280 #define MESONG12_CLOCK_VDEC_1_SEL 202 281 #define MESONG12_CLOCK_VDEC_1_DIV 203 282 #define MESONG12_CLOCK_VDEC_HEVC_SEL 205 283 #define MESONG12_CLOCK_VDEC_HEVC_DIV 206 284 #define MESONG12_CLOCK_VDEC_HEVCF_SEL 208 285 #define MESONG12_CLOCK_VDEC_HEVCF_DIV 209 286 #define MESONG12_CLOCK_TS_DIV 211 287 #define MESONG12_CLOCK_SYS1_PLL_DCO 213 288 #define MESONG12_CLOCK_SYS1_PLL 214 289 #define MESONG12_CLOCK_SYS1_PLL_DIV16_EN 215 290 #define MESONG12_CLOCK_SYS1_PLL_DIV16 216 291 #define MESONG12_CLOCK_CPUB_CLK_DYN0_SEL 217 292 #define MESONG12_CLOCK_CPUB_CLK_DYN0_DIV 218 293 #define MESONG12_CLOCK_CPUB_CLK_DYN0 219 294 #define MESONG12_CLOCK_CPUB_CLK_DYN1_SEL 220 295 #define MESONG12_CLOCK_CPUB_CLK_DYN1_DIV 221 296 #define MESONG12_CLOCK_CPUB_CLK_DYN1 222 297 #define MESONG12_CLOCK_CPUB_CLK_DYN 223 298 #define MESONG12_CLOCK_CPUB_CLK_DIV16_EN 225 299 #define MESONG12_CLOCK_CPUB_CLK_DIV16 226 300 #define MESONG12_CLOCK_CPUB_CLK_DIV2 227 301 #define MESONG12_CLOCK_CPUB_CLK_DIV3 228 302 #define MESONG12_CLOCK_CPUB_CLK_DIV4 229 303 #define MESONG12_CLOCK_CPUB_CLK_DIV5 230 304 #define MESONG12_CLOCK_CPUB_CLK_DIV6 231 305 #define MESONG12_CLOCK_CPUB_CLK_DIV7 232 306 #define MESONG12_CLOCK_CPUB_CLK_DIV8 233 307 #define MESONG12_CLOCK_CPUB_CLK_APB_SEL 234 308 #define MESONG12_CLOCK_CPUB_CLK_APB 235 309 #define MESONG12_CLOCK_CPUB_CLK_ATB_SEL 236 310 #define MESONG12_CLOCK_CPUB_CLK_ATB 237 311 #define MESONG12_CLOCK_CPUB_CLK_AXI_SEL 238 312 #define MESONG12_CLOCK_CPUB_CLK_AXI 239 313 #define MESONG12_CLOCK_CPUB_CLK_TRACE_SEL 240 314 #define MESONG12_CLOCK_CPUB_CLK_TRACE 241 315 #define MESONG12_CLOCK_GP1_PLL_DCO 242 316 #define MESONG12_CLOCK_DSU_CLK_DYN0_SEL 244 317 #define MESONG12_CLOCK_DSU_CLK_DYN0_DIV 245 318 #define MESONG12_CLOCK_DSU_CLK_DYN0 246 319 #define MESONG12_CLOCK_DSU_CLK_DYN1_SEL 247 320 #define MESONG12_CLOCK_DSU_CLK_DYN1_DIV 248 321 #define MESONG12_CLOCK_DSU_CLK_DYN1 249 322 #define MESONG12_CLOCK_DSU_CLK_DYN 250 323 #define MESONG12_CLOCK_DSU_CLK_FINAL 251 324 #define MESONG12_CLOCK_SPICC0_SCLK_SEL 256 325 #define MESONG12_CLOCK_SPICC0_SCLK_DIV 257 326 #define MESONG12_CLOCK_SPICC1_SCLK_SEL 259 327 #define MESONG12_CLOCK_SPICC1_SCLK_DIV 260 328 #define MESONG12_CLOCK_NNA_AXI_CLK_SEL 262 329 #define MESONG12_CLOCK_NNA_AXI_CLK_DIV 263 330 #define MESONG12_CLOCK_NNA_CORE_CLK_SEL 265 331 #define MESONG12_CLOCK_NNA_CORE_CLK_DIV 266 332 333 334 #endif /* _MESONG12_CLKC_H */ 335
Indexes created Sun Sep 21 20:09:37 GMT 2025