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    Searched defs:MI2 (Results 1 - 5 of 5) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/
BPFMIPeephole.cpp 462 MachineInstr *MI2 = nullptr;
481 MI2 = MRI->getVRegDef(SrcReg);
484 if (!MI2 ||
485 MI2->getOpcode() != BPF::SLL_ri ||
486 MI2->getOperand(2).getImm() != 32)
490 SrcReg = MI2->getOperand(1).getReg();
541 if (MI2)
542 MI2->eraseFromParent();
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonSubtarget.cpp 225 MachineInstr &MI2 = *SI.getSUnit()->getInstr();
226 if (!QII->isHVXVec(MI2))
228 if ((IsStoreMI1 && MI2.mayStore()) || (IsLoadMI1 && MI2.mayLoad())) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
AVRExpandPseudoInsts.cpp 1444 auto MI2 =
1450 MI2->getOperand(3).setIsDead();
1604 auto MI2 =
1610 MI2->getOperand(3).setIsDead();
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MicroMipsSizeReduction.cpp 197 MachineInstr *MI2 = nullptr,
398 static bool ConsecutiveInstr(MachineInstr *MI1, MachineInstr *MI2) {
403 if (!GetImm(MI2, 2, Offset2))
407 Register Reg2 = MI2->getOperand(0).getReg();
465 MachineInstr *MI2 = &*NextMII;
475 if (!CheckXWPInstr(MI2, ReduceToLwp, Entry))
479 Register Reg2 = MI2->getOperand(1).getReg();
484 bool ConsecutiveForward = ConsecutiveInstr(MI1, MI2);
485 bool ConsecutiveBackward = ConsecutiveInstr(MI2, MI1);
491 return ReplaceInstruction(MI1, Entry, MI2, ConsecutiveForward)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
TargetInstrInfo.cpp 709 MachineInstr *MI2 = nullptr;
713 MI2 = MRI.getUniqueVRegDef(Op2.getReg());
716 return MI1 && MI2 && MI1->getParent() == MBB && MI2->getParent() == MBB;
724 MachineInstr *MI2 = MRI.getUniqueVRegDef(Inst.getOperand(2).getReg());
729 Commuted = MI1->getOpcode() != AssocOpcode && MI2->getOpcode() == AssocOpcode;
731 std::swap(MI1, MI2);

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