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    Searched defs:MII (Results 1 - 25 of 36) sorted by relevancy

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  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/
HexagonInstPrinter.h 27 explicit HexagonInstPrinter(MCAsmInfo const &MAI, MCInstrInfo const &MII,
29 : MCInstPrinter(MAI, MII, MRI), MII(MII) {}
43 MCInstrInfo const &getMII() const { return MII; }
46 MCInstrInfo const &MII;
  /src/external/apache2/llvm/dist/llvm/lib/Target/CSKY/MCTargetDesc/
CSKYMCCodeEmitter.h 25 const MCInstrInfo &MII;
28 CSKYMCCodeEmitter(MCContext &Ctx, const MCInstrInfo &MII)
29 : Ctx(Ctx), MII(MII) {}
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
CSEMIRBuilder.cpp 45 auto MII = MachineBasicBlock::iterator(MI);
46 if (MII == CurrPos) {
49 setInsertPt(*CurMBB, std::next(MII));
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
PseudoProbeInserter.cpp 86 auto MII = MBB.rbegin();
87 while (MII != MBB.rend()) {
90 if (!MII->isPseudo())
92 auto Cur = MII++;
LLVMTargetMachine.cpp 44 MII.reset(TheTarget.createMCInstrInfo());
45 assert(MII && "Unable to create instruction info");
151 const MCInstrInfo &MII = *getMCInstrInfo();
158 getTargetTriple(), MAI.getAssemblerDialect(), MAI, MII, MRI);
163 MCE.reset(getTarget().createMCCodeEmitter(MII, MRI, Context));
178 MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(MII, MRI, Context);
MachineInstrBundle.cpp 51 for (MachineBasicBlock::instr_iterator MII = MBB.instr_begin(),
52 MIE = MBB.instr_end(); MII != MIE; ) {
53 MachineInstr *MI = &*MII;
58 while (++MII != MIE && MII->isBundledWithPred()) {
59 MII->unbundleFromPred();
60 for (unsigned i = 0, e = MII->getNumOperands(); i != e; ++i) {
61 MachineOperand &MO = MII->getOperand(i);
72 ++MII;
111 for (auto MII = FirstMI; MII != LastMI; ++MII
    [all...]
SplitKit.h 86 MachineBasicBlock::iterator MII = MBB.SkipPHIsLabelsAndDebug(MBB.begin());
87 if (MII != MBB.end())
88 Res = LIS.getInstructionIndex(*MII);
InlineSpiller.cpp 416 MachineBasicBlock::iterator MII;
418 MII = MBB->SkipPHIsLabelsAndDebug(MBB->begin());
422 MII = DefMI;
423 ++MII;
425 MachineInstrSpan MIS(MII, MBB);
427 TII.storeRegToStackSlot(*MBB, MII, SrcReg, false, StackSlot,
429 LIS.InsertMachineInstrRangeInMaps(MIS.begin(), MII);
430 for (const MachineInstr &MI : make_range(MIS.begin(), MII))
432 --MII; // Point to store instruction.
433 LLVM_DEBUG(dbgs() << "\thoisted: " << SrcVNI->def << '\t' << *MII);
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonCFGOptimizer.cpp 126 MachineBasicBlock::iterator MII = MBB->getFirstTerminator();
127 if (MII != MBB->end()) {
128 MachineInstr &MI = *MII;
HexagonFixupHwLoops.cpp 70 MachineBasicBlock::iterator &MII);
136 MachineBasicBlock::iterator MII = MBB.begin();
138 while (MII != MIE) {
139 unsigned InstSize = HII->getSize(*MII);
140 if (MII->isMetaInstruction()) {
141 ++MII;
144 if (isHardwareLoop(*MII)) {
145 assert(MII->getOperand(0).isMBB() &&
147 MachineBasicBlock *TargetBB = MII->getOperand(0).getMBB();
151 useExtLoopInstr(MF, MII);
    [all...]
HexagonVectorPrint.cpp 140 MachineBasicBlock::instr_iterator MII = MI.getIterator();
141 for (++MII; MII != MBB.instr_end() && MII->isInsideBundle(); ++MII) {
142 if (MII->getNumOperands() < 1)
145 if (getInstrVecReg(*MII, Reg)) {
146 VecPrintList.push_back((&*MII));
148 MII->dump());
171 MachineBasicBlock::instr_iterator MII = I->getIterator()
    [all...]
HexagonAsmPrinter.cpp 751 MachineBasicBlock::const_instr_iterator MII = MI->getIterator();
753 for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)
754 if (!MII->isDebugInstr() && !MII->isImplicitDef())
755 HexagonLowerToMC(MCII, &*MII, MCB, *this);
  /src/external/apache2/llvm/dist/llvm/include/llvm/DWARFLinker/
DWARFStreamer.h 179 std::unique_ptr<MCInstrInfo> MII;
  /src/external/apache2/llvm/dist/llvm/lib/MC/MCDisassembler/
Disassembler.cpp 67 std::unique_ptr<const MCInstrInfo> MII(TheTarget->createMCInstrInfo());
68 if (!MII)
100 Triple(TT), AsmPrinterVariant, *MAI, *MII, *MRI));
106 std::move(MRI), std::move(STI), std::move(MII), std::move(Ctx),
322 const MCInstrInfo *MII = DC->getInstrInfo();
327 Triple(DC->getTripleName()), AsmPrinterVariant, *MAI, *MII, *MRI);
Disassembler.h 68 std::unique_ptr<const llvm::MCInstrInfo> MII;
92 std::unique_ptr<const MCInstrInfo> &&MII,
99 MII(std::move(MII)), Ctx(std::move(Ctx)), DisAsm(std::move(DisAsm)),
111 const MCInstrInfo *getInstrInfo() const { return MII.get(); }
  /src/external/apache2/llvm/dist/llvm/include/llvm/MC/
MCInstPrinter.h 50 const MCInstrInfo &MII;
79 MCInstPrinter(const MCAsmInfo &mai, const MCInstrInfo &mii,
80 const MCRegisterInfo &mri) : MAI(mai), MII(mii), MRI(mri) {}
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
R600Packetizer.cpp 178 MachineInstr *MII = SUI->getInstr(), *MIJ = SUJ->getInstr();
179 if (getSlot(*MII) == getSlot(*MIJ))
181 // Does MII and MIJ share the same pred_sel ?
182 int OpI = TII->getOperandIdx(MII->getOpcode(), R600::OpName::pred_sel),
184 Register PredI = (OpI > -1)?MII->getOperand(OpI).getReg() : Register(),
196 if (MII->getOperand(0).getReg() != MIJ->getOperand(0).getReg())
203 TII->definesAddressRegister(*MII) || TII->definesAddressRegister(*MIJ);
205 TII->usesAddressRegister(*MII) || TII->usesAddressRegister(*MIJ);
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
MLxExpansionPass.cpp 312 MachineBasicBlock::iterator MII = MI;
313 MII = std::prev(MII);
314 MachineInstr &MI2 = *MII;
315 MII = std::prev(MII);
316 MachineInstr &MI1 = *MII;
332 MachineBasicBlock::reverse_iterator MII = MBB.rbegin(), E = MBB.rend();
333 while (MII != E) {
334 MachineInstr *MI = &*MII++
    [all...]
Thumb2SizeReduction.cpp 1065 MachineBasicBlock::instr_iterator MII = MBB.instr_begin(),E = MBB.instr_end();
1067 for (; MII != E; MII = NextMII) {
1068 NextMII = std::next(MII);
1070 MachineInstr *MI = &*MII;
  /src/external/apache2/llvm/dist/llvm/tools/llvm-cfi-verify/lib/
FileAnalysis.h 209 std::unique_ptr<const MCInstrInfo> MII;
  /src/external/apache2/llvm/dist/llvm/tools/llvm-profgen/
ProfiledBinary.h 110 std::unique_ptr<const MCInstrInfo> MII;
  /src/external/apache2/llvm/dist/llvm/include/llvm/Target/
TargetMachine.h 107 std::unique_ptr<const MCInstrInfo> MII;
205 const MCInstrInfo *getMCInstrInfo() const { return MII.get(); }
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MicroMipsSizeReduction.cpp 154 bool ReduceMI(const MachineBasicBlock::instr_iterator &MII,
414 bool MicroMipsSizeReduce::ReduceMI(const MachineBasicBlock::instr_iterator &MII,
417 MachineInstr *MI = &*MII;
433 ReduceEntryFunArgs Arguments(&(*MII), *Entry, NextMII);
673 MachineBasicBlock::instr_iterator MII = MBB.instr_begin(),
678 for (; MII != E; MII = NextMII) {
679 NextMII = std::next(MII);
680 MachineInstr *MI = &*MII;
687 Modified |= ReduceMI(MII, NextMII)
    [all...]
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
MachinePipeliner.h 32 // initiation interval (MII).
37 // 3) Attempt to schedule the nodes in the specified order using the MII.
109 unsigned MII = 0;
363 void setRecMII(unsigned mii) { RecMII = mii; };
399 /// Sort the node sets by importance. First, rank them by recurrence MII,
  /src/external/apache2/llvm/dist/llvm/include/llvm/MC/MCParser/
MCTargetAsmParser.h 323 const MCInstrInfo &MII);
344 const MCInstrInfo &MII;

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