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      1 /* $NetBSD: pl181reg.h,v 1.1 2015/01/27 16:33:26 jmcneill Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca>
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  *
     16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
     21  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
     22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
     23  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     24  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     26  * SUCH DAMAGE.
     27  */
     28 
     29 #ifndef _PL181REG_H
     30 #define _PL181REG_H
     31 
     32 #define MMCI_POWER_REG		0x000
     33 #define MMCI_CLOCK_REG		0x004
     34 #define	MMCI_ARGUMENT_REG	0x008
     35 #define MMCI_COMMAND_REG	0x00c
     36 #define MMCI_RESP_CMD_REG	0x010
     37 #define MMCI_RESP0_REG		0x014
     38 #define MMCI_RESP1_REG		0x018
     39 #define MMCI_RESP2_REG		0x01c
     40 #define MMCI_RESP3_REG		0x020
     41 #define MMCI_DATA_TIMER_REG	0x024
     42 #define MMCI_DATA_LENGTH_REG	0x028
     43 #define MMCI_DATA_CTRL_REG	0x02c
     44 #define MMCI_DATA_CNT_REG	0x030
     45 #define MMCI_STATUS_REG		0x034
     46 #define MMCI_CLEAR_REG		0x038
     47 #define MMCI_MASK0_REG		0x03c
     48 #define MMCI_MASK1_REG		0x040
     49 #define MMCI_FIFO_CNT_REG	0x048
     50 #define MMCI_FIFO_REG		0x080
     51 #define MMCI_PERIPH_ID0_REG	0xfe0
     52 #define MMCI_PERIPH_ID1_REG	0xfe4
     53 #define MMCI_PERIPH_ID2_REG	0xfe8
     54 #define MMCI_PERIPH_ID3_REG	0xfec
     55 #define MMCI_PCELL_ID0_REG	0xff0
     56 #define MMCI_PCELL_ID1_REG	0xff4
     57 #define MMCI_PCELL_ID2_REG	0xff8
     58 #define MMCI_PCELL_ID3_REG	0xffc
     59 
     60 #define MMCI_POWER_CTRL		__BITS(1,0)
     61 #define MMCI_POWER_CTRL_OFF	0
     62 #define MMCI_POWER_CTRL_POWERUP	2
     63 #define MMCI_POWER_CTRL_POWERON	3
     64 #define MMCI_POWER_VOLTAGE	__BITS(5,2)
     65 #define MMCI_POWER_OD		__BIT(6)
     66 #define MMCI_POWER_ROD		__BIT(7)
     67 
     68 #define MMCI_CLOCK_CLKDIV	__BITS(7,0)
     69 #define MMCI_CLOCK_ENABLE	__BIT(8)
     70 #define MMCI_CLOCK_PWRSAVE	__BIT(9)
     71 #define MMCI_CLOCK_BYPASS	__BIT(10)
     72 
     73 #define MMCI_COMMAND_CMDINDEX	__BITS(5,0)
     74 #define MMCI_COMMAND_RESPONSE	__BIT(6)
     75 #define MMCI_COMMAND_LONGRSP	__BIT(7)
     76 #define MMCI_COMMAND_INTERRUPT	__BIT(8)
     77 #define MMCI_COMMAND_PENDING	__BIT(9)
     78 #define MMCI_COMMAND_ENABLE	__BIT(10)
     79 
     80 #define MMCI_RESP_CMD		__BITS(5,0)
     81 
     82 #define MMCI_DATA_LENGTH	__BITS(15,0)
     83 
     84 #define MMCI_DATA_CTRL_ENABLE		__BIT(0)
     85 #define MMCI_DATA_CTRL_DIRECTION	__BIT(1)
     86 #define MMCI_DATA_CTRL_MODE		__BIT(2)
     87 #define MMCI_DATA_CTRL_DMAENABLE	__BIT(3)
     88 #define MMCI_DATA_CTRL_BLOCKSIZE	__BITS(7,4)
     89 
     90 #define MMCI_DATA_CNT		__BITS(15,0)
     91 
     92 #define MMCI_INT_CMD_CRC_FAIL		__BIT(0)
     93 #define MMCI_INT_DATA_CRC_FAIL		__BIT(1)
     94 #define MMCI_INT_CMD_TIMEOUT		__BIT(2)
     95 #define MMCI_INT_DATA_TIMEOUT		__BIT(3)
     96 #define MMCI_INT_TX_UNDERRUN		__BIT(4)
     97 #define MMCI_INT_RX_OVERRUN		__BIT(5)
     98 #define MMCI_INT_CMD_RESP_END		__BIT(6)
     99 #define MMCI_INT_CMD_SENT		__BIT(7)
    100 #define MMCI_INT_DATA_END		__BIT(8)
    101 #define MMCI_INT_DATA_BLOCK_END		__BIT(10)
    102 #define MMCI_INT_CMD_ACTIVE		__BIT(11)
    103 #define MMCI_INT_TX_ACTIVE		__BIT(12)
    104 #define MMCI_INT_RX_ACTIVE		__BIT(13)
    105 #define MMCI_INT_TX_FIFO_HALF_EMPTY	__BIT(14)
    106 #define MMCI_INT_RX_FIFO_HALF_FULL	__BIT(15)
    107 #define MMCI_INT_TX_FIFO_FULL		__BIT(16)
    108 #define MMCI_INT_RX_FIFO_FULL		__BIT(17)
    109 #define MMCI_INT_TX_FIFO_EMPTY		__BIT(18)
    110 #define MMCI_INT_RX_FIFO_EMPTY		__BIT(19)
    111 #define MMCI_INT_TX_DATA_AVAIL		__BIT(20)
    112 #define MMCI_INT_RX_DATA_AVAIL		__BIT(21)
    113 
    114 #define MMCI_FIFO_CNT		__BITS(14,0)
    115 
    116 #endif /* !_PL181REG_H */
    117