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      1 /*	$NetBSD: pte3x.h,v 1.9 2024/12/20 23:50:00 tsutsui Exp $	*/
      2 
      3 /*-
      4  * Copyright (c) 1997 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by Jeremy Cooper.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  *
     19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29  * POSSIBILITY OF SUCH DAMAGE.
     30  */
     31 
     32 /*
     33  * This file should contain the machine-dependent details about
     34  * Page Table Entries (PTEs) and related things.  For example,
     35  * things that depend on the MMU configuration (number of levels
     36  * in the translation structure) should go here.
     37  */
     38 
     39 #ifndef _MACHINE_PTE3X_H
     40 #define _MACHINE_PTE3X_H
     41 
     42 #include <machine/mc68851.h>
     43 
     44 /*************************************************************************
     45  * Translation Control Register Settings                                 *
     46  *************************************************************************
     47  * The following settings are set by the ROM monitor and used by the
     48  * kernel.  If they are changed, appropriate code must be written into
     49  * the kernel startup to set them.
     50  *
     51  * A virtual address is translated into a physical address by dividing its
     52  * bits into four fields.  The first three fields are used as indexes into
     53  * descriptor tables and the last field (the 13 lowest significant
     54  * bits) is an offset to be added to the base address found at the final
     55  * table.  The first three fields are named TIA, TIB and TIC respectively.
     56  *  31                                    12                        0
     57  *  +-.-.-.-.-.-.-+-.-.-.-.-.-+-.-.-.-.-.-+-.-.-.-.-.-.-.-.-.-.-.-.-+
     58  *  |     TIA     |    TIB    |    TIC    |        OFFSET           |
     59  *  +-.-.-.-.-.-.-+-.-.-.-.-.-+-.-.-.-.-.-+-.-.-.-.-.-.-.-.-.-.-.-.-+
     60  */
     61 #define MMU_TIA_SHIFT (13+6+6)
     62 #define MMU_TIA_MASK  (0xfe000000)
     63 #define MMU_TIA_RANGE (0x02000000)
     64 #define MMU_TIB_SHIFT (13+6)
     65 #define MMU_TIB_MASK  (0x01f80000)
     66 #define MMU_TIB_RANGE (0x00080000)
     67 #define MMU_TIC_SHIFT (13)
     68 #define MMU_TIC_MASK  (0x0007e000)
     69 #define MMU_TIC_RANGE (0x00002000)
     70 #define MMU_PAGE_SHIFT (13)
     71 #define MMU_PAGE_MASK (0xffffe000)
     72 #define MMU_PAGE_SIZE (0x00002000)
     73 
     74 /*
     75  * Macros which extract each of these fields out of a given
     76  * VA.
     77  */
     78 #define MMU_TIA(va) \
     79 	((unsigned long) ((va) & MMU_TIA_MASK) >> MMU_TIA_SHIFT)
     80 #define MMU_TIB(va) \
     81 	((unsigned long) ((va) & MMU_TIB_MASK) >> MMU_TIB_SHIFT)
     82 #define MMU_TIC(va) \
     83 	((unsigned long) ((va) & MMU_TIC_MASK) >> MMU_TIC_SHIFT)
     84 
     85 /*
     86  * The widths of the TIA, TIB, and TIC fields determine the size (in
     87  * elements) of the tables they index.
     88  */
     89 #define MMU_A_TBL_SIZE (128)
     90 #define MMU_B_TBL_SIZE (64)
     91 #define MMU_C_TBL_SIZE (64)
     92 
     93 /*
     94  * Rounding macros.
     95  * The MMU_ROUND macros are named misleadingly.  MMU_ROUND_A actually
     96  * rounds an address to the nearest B table boundary, and so on.
     97  * MMU_ROUND_C() is synonmous with m68k_round_page().
     98  */
     99 #define	MMU_ROUND_A(pa)\
    100 	((unsigned long) (pa) & MMU_TIA_MASK)
    101 #define	MMU_ROUND_UP_A(pa)\
    102 	((unsigned long) (pa + MMU_TIA_RANGE - 1) & MMU_TIA_MASK)
    103 #define	MMU_ROUND_B(pa)\
    104 	((unsigned long) (pa) & (MMU_TIA_MASK|MMU_TIB_MASK))
    105 #define	MMU_ROUND_UP_B(pa)\
    106 	((unsigned long) (pa + MMU_TIB_RANGE - 1) & (MMU_TIA_MASK|MMU_TIB_MASK))
    107 #define	MMU_ROUND_C(pa)\
    108 	((unsigned long) (pa) & MMU_PAGE_MASK)
    109 #define	MMU_ROUND_UP_C(pa)\
    110 	((unsigned long) (pa + MMU_PAGE_SIZE - 1) & MMU_PAGE_MASK)
    111 
    112 /* Compatibility... */
    113 #define PG_FRAME MMU_SHORT_PTE_BASEADDR
    114 #define PG_PA(pte)  	((pte) & PG_FRAME)
    115 #define PG_PFNUM(pte)	(PG_PA(pte) >> PGSHIFT)
    116 #define PG_VALID    	MMU_DT_PAGE
    117 
    118 #endif	/* _MACHINE_PTE3X_H */
    119