1 /* $NetBSD: mmhub_2_0_0_sh_mask.h,v 1.2 2021/12/18 23:45:16 riastradh Exp $ */ 2 3 /* 4 * Copyright (C) 2019 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 #ifndef _mmhub_2_0_0_SH_MASK_HEADER 24 #define _mmhub_2_0_0_SH_MASK_HEADER 25 26 27 // addressBlock: mmhub_dagbdec 28 //DAGB0_RDCLI0 29 #define DAGB0_RDCLI0__VIRT_CHAN__SHIFT 0x0 30 #define DAGB0_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 31 #define DAGB0_RDCLI0__URG_HIGH__SHIFT 0x4 32 #define DAGB0_RDCLI0__URG_LOW__SHIFT 0x8 33 #define DAGB0_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc 34 #define DAGB0_RDCLI0__MAX_BW__SHIFT 0xd 35 #define DAGB0_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15 36 #define DAGB0_RDCLI0__MIN_BW__SHIFT 0x16 37 #define DAGB0_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 38 #define DAGB0_RDCLI0__MAX_OSD__SHIFT 0x1a 39 #define DAGB0_RDCLI0__VIRT_CHAN_MASK 0x00000007L 40 #define DAGB0_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L 41 #define DAGB0_RDCLI0__URG_HIGH_MASK 0x000000F0L 42 #define DAGB0_RDCLI0__URG_LOW_MASK 0x00000F00L 43 #define DAGB0_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L 44 #define DAGB0_RDCLI0__MAX_BW_MASK 0x001FE000L 45 #define DAGB0_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L 46 #define DAGB0_RDCLI0__MIN_BW_MASK 0x01C00000L 47 #define DAGB0_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L 48 #define DAGB0_RDCLI0__MAX_OSD_MASK 0xFC000000L 49 //DAGB0_RDCLI1 50 #define DAGB0_RDCLI1__VIRT_CHAN__SHIFT 0x0 51 #define DAGB0_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 52 #define DAGB0_RDCLI1__URG_HIGH__SHIFT 0x4 53 #define DAGB0_RDCLI1__URG_LOW__SHIFT 0x8 54 #define DAGB0_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc 55 #define DAGB0_RDCLI1__MAX_BW__SHIFT 0xd 56 #define DAGB0_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15 57 #define DAGB0_RDCLI1__MIN_BW__SHIFT 0x16 58 #define DAGB0_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 59 #define DAGB0_RDCLI1__MAX_OSD__SHIFT 0x1a 60 #define DAGB0_RDCLI1__VIRT_CHAN_MASK 0x00000007L 61 #define DAGB0_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L 62 #define DAGB0_RDCLI1__URG_HIGH_MASK 0x000000F0L 63 #define DAGB0_RDCLI1__URG_LOW_MASK 0x00000F00L 64 #define DAGB0_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L 65 #define DAGB0_RDCLI1__MAX_BW_MASK 0x001FE000L 66 #define DAGB0_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L 67 #define DAGB0_RDCLI1__MIN_BW_MASK 0x01C00000L 68 #define DAGB0_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L 69 #define DAGB0_RDCLI1__MAX_OSD_MASK 0xFC000000L 70 //DAGB0_RDCLI2 71 #define DAGB0_RDCLI2__VIRT_CHAN__SHIFT 0x0 72 #define DAGB0_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 73 #define DAGB0_RDCLI2__URG_HIGH__SHIFT 0x4 74 #define DAGB0_RDCLI2__URG_LOW__SHIFT 0x8 75 #define DAGB0_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc 76 #define DAGB0_RDCLI2__MAX_BW__SHIFT 0xd 77 #define DAGB0_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15 78 #define DAGB0_RDCLI2__MIN_BW__SHIFT 0x16 79 #define DAGB0_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 80 #define DAGB0_RDCLI2__MAX_OSD__SHIFT 0x1a 81 #define DAGB0_RDCLI2__VIRT_CHAN_MASK 0x00000007L 82 #define DAGB0_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L 83 #define DAGB0_RDCLI2__URG_HIGH_MASK 0x000000F0L 84 #define DAGB0_RDCLI2__URG_LOW_MASK 0x00000F00L 85 #define DAGB0_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L 86 #define DAGB0_RDCLI2__MAX_BW_MASK 0x001FE000L 87 #define DAGB0_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L 88 #define DAGB0_RDCLI2__MIN_BW_MASK 0x01C00000L 89 #define DAGB0_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L 90 #define DAGB0_RDCLI2__MAX_OSD_MASK 0xFC000000L 91 //DAGB0_RDCLI3 92 #define DAGB0_RDCLI3__VIRT_CHAN__SHIFT 0x0 93 #define DAGB0_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 94 #define DAGB0_RDCLI3__URG_HIGH__SHIFT 0x4 95 #define DAGB0_RDCLI3__URG_LOW__SHIFT 0x8 96 #define DAGB0_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc 97 #define DAGB0_RDCLI3__MAX_BW__SHIFT 0xd 98 #define DAGB0_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15 99 #define DAGB0_RDCLI3__MIN_BW__SHIFT 0x16 100 #define DAGB0_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 101 #define DAGB0_RDCLI3__MAX_OSD__SHIFT 0x1a 102 #define DAGB0_RDCLI3__VIRT_CHAN_MASK 0x00000007L 103 #define DAGB0_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L 104 #define DAGB0_RDCLI3__URG_HIGH_MASK 0x000000F0L 105 #define DAGB0_RDCLI3__URG_LOW_MASK 0x00000F00L 106 #define DAGB0_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L 107 #define DAGB0_RDCLI3__MAX_BW_MASK 0x001FE000L 108 #define DAGB0_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L 109 #define DAGB0_RDCLI3__MIN_BW_MASK 0x01C00000L 110 #define DAGB0_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L 111 #define DAGB0_RDCLI3__MAX_OSD_MASK 0xFC000000L 112 //DAGB0_RDCLI4 113 #define DAGB0_RDCLI4__VIRT_CHAN__SHIFT 0x0 114 #define DAGB0_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 115 #define DAGB0_RDCLI4__URG_HIGH__SHIFT 0x4 116 #define DAGB0_RDCLI4__URG_LOW__SHIFT 0x8 117 #define DAGB0_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc 118 #define DAGB0_RDCLI4__MAX_BW__SHIFT 0xd 119 #define DAGB0_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15 120 #define DAGB0_RDCLI4__MIN_BW__SHIFT 0x16 121 #define DAGB0_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 122 #define DAGB0_RDCLI4__MAX_OSD__SHIFT 0x1a 123 #define DAGB0_RDCLI4__VIRT_CHAN_MASK 0x00000007L 124 #define DAGB0_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L 125 #define DAGB0_RDCLI4__URG_HIGH_MASK 0x000000F0L 126 #define DAGB0_RDCLI4__URG_LOW_MASK 0x00000F00L 127 #define DAGB0_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L 128 #define DAGB0_RDCLI4__MAX_BW_MASK 0x001FE000L 129 #define DAGB0_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L 130 #define DAGB0_RDCLI4__MIN_BW_MASK 0x01C00000L 131 #define DAGB0_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L 132 #define DAGB0_RDCLI4__MAX_OSD_MASK 0xFC000000L 133 //DAGB0_RDCLI5 134 #define DAGB0_RDCLI5__VIRT_CHAN__SHIFT 0x0 135 #define DAGB0_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 136 #define DAGB0_RDCLI5__URG_HIGH__SHIFT 0x4 137 #define DAGB0_RDCLI5__URG_LOW__SHIFT 0x8 138 #define DAGB0_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc 139 #define DAGB0_RDCLI5__MAX_BW__SHIFT 0xd 140 #define DAGB0_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15 141 #define DAGB0_RDCLI5__MIN_BW__SHIFT 0x16 142 #define DAGB0_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 143 #define DAGB0_RDCLI5__MAX_OSD__SHIFT 0x1a 144 #define DAGB0_RDCLI5__VIRT_CHAN_MASK 0x00000007L 145 #define DAGB0_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L 146 #define DAGB0_RDCLI5__URG_HIGH_MASK 0x000000F0L 147 #define DAGB0_RDCLI5__URG_LOW_MASK 0x00000F00L 148 #define DAGB0_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L 149 #define DAGB0_RDCLI5__MAX_BW_MASK 0x001FE000L 150 #define DAGB0_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L 151 #define DAGB0_RDCLI5__MIN_BW_MASK 0x01C00000L 152 #define DAGB0_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L 153 #define DAGB0_RDCLI5__MAX_OSD_MASK 0xFC000000L 154 //DAGB0_RDCLI6 155 #define DAGB0_RDCLI6__VIRT_CHAN__SHIFT 0x0 156 #define DAGB0_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 157 #define DAGB0_RDCLI6__URG_HIGH__SHIFT 0x4 158 #define DAGB0_RDCLI6__URG_LOW__SHIFT 0x8 159 #define DAGB0_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc 160 #define DAGB0_RDCLI6__MAX_BW__SHIFT 0xd 161 #define DAGB0_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15 162 #define DAGB0_RDCLI6__MIN_BW__SHIFT 0x16 163 #define DAGB0_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 164 #define DAGB0_RDCLI6__MAX_OSD__SHIFT 0x1a 165 #define DAGB0_RDCLI6__VIRT_CHAN_MASK 0x00000007L 166 #define DAGB0_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L 167 #define DAGB0_RDCLI6__URG_HIGH_MASK 0x000000F0L 168 #define DAGB0_RDCLI6__URG_LOW_MASK 0x00000F00L 169 #define DAGB0_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L 170 #define DAGB0_RDCLI6__MAX_BW_MASK 0x001FE000L 171 #define DAGB0_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L 172 #define DAGB0_RDCLI6__MIN_BW_MASK 0x01C00000L 173 #define DAGB0_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L 174 #define DAGB0_RDCLI6__MAX_OSD_MASK 0xFC000000L 175 //DAGB0_RDCLI7 176 #define DAGB0_RDCLI7__VIRT_CHAN__SHIFT 0x0 177 #define DAGB0_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 178 #define DAGB0_RDCLI7__URG_HIGH__SHIFT 0x4 179 #define DAGB0_RDCLI7__URG_LOW__SHIFT 0x8 180 #define DAGB0_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc 181 #define DAGB0_RDCLI7__MAX_BW__SHIFT 0xd 182 #define DAGB0_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15 183 #define DAGB0_RDCLI7__MIN_BW__SHIFT 0x16 184 #define DAGB0_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 185 #define DAGB0_RDCLI7__MAX_OSD__SHIFT 0x1a 186 #define DAGB0_RDCLI7__VIRT_CHAN_MASK 0x00000007L 187 #define DAGB0_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L 188 #define DAGB0_RDCLI7__URG_HIGH_MASK 0x000000F0L 189 #define DAGB0_RDCLI7__URG_LOW_MASK 0x00000F00L 190 #define DAGB0_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L 191 #define DAGB0_RDCLI7__MAX_BW_MASK 0x001FE000L 192 #define DAGB0_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L 193 #define DAGB0_RDCLI7__MIN_BW_MASK 0x01C00000L 194 #define DAGB0_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L 195 #define DAGB0_RDCLI7__MAX_OSD_MASK 0xFC000000L 196 //DAGB0_RDCLI8 197 #define DAGB0_RDCLI8__VIRT_CHAN__SHIFT 0x0 198 #define DAGB0_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 199 #define DAGB0_RDCLI8__URG_HIGH__SHIFT 0x4 200 #define DAGB0_RDCLI8__URG_LOW__SHIFT 0x8 201 #define DAGB0_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc 202 #define DAGB0_RDCLI8__MAX_BW__SHIFT 0xd 203 #define DAGB0_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15 204 #define DAGB0_RDCLI8__MIN_BW__SHIFT 0x16 205 #define DAGB0_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 206 #define DAGB0_RDCLI8__MAX_OSD__SHIFT 0x1a 207 #define DAGB0_RDCLI8__VIRT_CHAN_MASK 0x00000007L 208 #define DAGB0_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L 209 #define DAGB0_RDCLI8__URG_HIGH_MASK 0x000000F0L 210 #define DAGB0_RDCLI8__URG_LOW_MASK 0x00000F00L 211 #define DAGB0_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L 212 #define DAGB0_RDCLI8__MAX_BW_MASK 0x001FE000L 213 #define DAGB0_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L 214 #define DAGB0_RDCLI8__MIN_BW_MASK 0x01C00000L 215 #define DAGB0_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L 216 #define DAGB0_RDCLI8__MAX_OSD_MASK 0xFC000000L 217 //DAGB0_RDCLI9 218 #define DAGB0_RDCLI9__VIRT_CHAN__SHIFT 0x0 219 #define DAGB0_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 220 #define DAGB0_RDCLI9__URG_HIGH__SHIFT 0x4 221 #define DAGB0_RDCLI9__URG_LOW__SHIFT 0x8 222 #define DAGB0_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc 223 #define DAGB0_RDCLI9__MAX_BW__SHIFT 0xd 224 #define DAGB0_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15 225 #define DAGB0_RDCLI9__MIN_BW__SHIFT 0x16 226 #define DAGB0_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 227 #define DAGB0_RDCLI9__MAX_OSD__SHIFT 0x1a 228 #define DAGB0_RDCLI9__VIRT_CHAN_MASK 0x00000007L 229 #define DAGB0_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L 230 #define DAGB0_RDCLI9__URG_HIGH_MASK 0x000000F0L 231 #define DAGB0_RDCLI9__URG_LOW_MASK 0x00000F00L 232 #define DAGB0_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L 233 #define DAGB0_RDCLI9__MAX_BW_MASK 0x001FE000L 234 #define DAGB0_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L 235 #define DAGB0_RDCLI9__MIN_BW_MASK 0x01C00000L 236 #define DAGB0_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L 237 #define DAGB0_RDCLI9__MAX_OSD_MASK 0xFC000000L 238 //DAGB0_RDCLI10 239 #define DAGB0_RDCLI10__VIRT_CHAN__SHIFT 0x0 240 #define DAGB0_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 241 #define DAGB0_RDCLI10__URG_HIGH__SHIFT 0x4 242 #define DAGB0_RDCLI10__URG_LOW__SHIFT 0x8 243 #define DAGB0_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc 244 #define DAGB0_RDCLI10__MAX_BW__SHIFT 0xd 245 #define DAGB0_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15 246 #define DAGB0_RDCLI10__MIN_BW__SHIFT 0x16 247 #define DAGB0_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 248 #define DAGB0_RDCLI10__MAX_OSD__SHIFT 0x1a 249 #define DAGB0_RDCLI10__VIRT_CHAN_MASK 0x00000007L 250 #define DAGB0_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L 251 #define DAGB0_RDCLI10__URG_HIGH_MASK 0x000000F0L 252 #define DAGB0_RDCLI10__URG_LOW_MASK 0x00000F00L 253 #define DAGB0_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L 254 #define DAGB0_RDCLI10__MAX_BW_MASK 0x001FE000L 255 #define DAGB0_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L 256 #define DAGB0_RDCLI10__MIN_BW_MASK 0x01C00000L 257 #define DAGB0_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L 258 #define DAGB0_RDCLI10__MAX_OSD_MASK 0xFC000000L 259 //DAGB0_RDCLI11 260 #define DAGB0_RDCLI11__VIRT_CHAN__SHIFT 0x0 261 #define DAGB0_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 262 #define DAGB0_RDCLI11__URG_HIGH__SHIFT 0x4 263 #define DAGB0_RDCLI11__URG_LOW__SHIFT 0x8 264 #define DAGB0_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc 265 #define DAGB0_RDCLI11__MAX_BW__SHIFT 0xd 266 #define DAGB0_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15 267 #define DAGB0_RDCLI11__MIN_BW__SHIFT 0x16 268 #define DAGB0_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 269 #define DAGB0_RDCLI11__MAX_OSD__SHIFT 0x1a 270 #define DAGB0_RDCLI11__VIRT_CHAN_MASK 0x00000007L 271 #define DAGB0_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L 272 #define DAGB0_RDCLI11__URG_HIGH_MASK 0x000000F0L 273 #define DAGB0_RDCLI11__URG_LOW_MASK 0x00000F00L 274 #define DAGB0_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L 275 #define DAGB0_RDCLI11__MAX_BW_MASK 0x001FE000L 276 #define DAGB0_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L 277 #define DAGB0_RDCLI11__MIN_BW_MASK 0x01C00000L 278 #define DAGB0_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L 279 #define DAGB0_RDCLI11__MAX_OSD_MASK 0xFC000000L 280 //DAGB0_RDCLI12 281 #define DAGB0_RDCLI12__VIRT_CHAN__SHIFT 0x0 282 #define DAGB0_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 283 #define DAGB0_RDCLI12__URG_HIGH__SHIFT 0x4 284 #define DAGB0_RDCLI12__URG_LOW__SHIFT 0x8 285 #define DAGB0_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc 286 #define DAGB0_RDCLI12__MAX_BW__SHIFT 0xd 287 #define DAGB0_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15 288 #define DAGB0_RDCLI12__MIN_BW__SHIFT 0x16 289 #define DAGB0_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 290 #define DAGB0_RDCLI12__MAX_OSD__SHIFT 0x1a 291 #define DAGB0_RDCLI12__VIRT_CHAN_MASK 0x00000007L 292 #define DAGB0_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L 293 #define DAGB0_RDCLI12__URG_HIGH_MASK 0x000000F0L 294 #define DAGB0_RDCLI12__URG_LOW_MASK 0x00000F00L 295 #define DAGB0_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L 296 #define DAGB0_RDCLI12__MAX_BW_MASK 0x001FE000L 297 #define DAGB0_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L 298 #define DAGB0_RDCLI12__MIN_BW_MASK 0x01C00000L 299 #define DAGB0_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L 300 #define DAGB0_RDCLI12__MAX_OSD_MASK 0xFC000000L 301 //DAGB0_RDCLI13 302 #define DAGB0_RDCLI13__VIRT_CHAN__SHIFT 0x0 303 #define DAGB0_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 304 #define DAGB0_RDCLI13__URG_HIGH__SHIFT 0x4 305 #define DAGB0_RDCLI13__URG_LOW__SHIFT 0x8 306 #define DAGB0_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc 307 #define DAGB0_RDCLI13__MAX_BW__SHIFT 0xd 308 #define DAGB0_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15 309 #define DAGB0_RDCLI13__MIN_BW__SHIFT 0x16 310 #define DAGB0_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 311 #define DAGB0_RDCLI13__MAX_OSD__SHIFT 0x1a 312 #define DAGB0_RDCLI13__VIRT_CHAN_MASK 0x00000007L 313 #define DAGB0_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L 314 #define DAGB0_RDCLI13__URG_HIGH_MASK 0x000000F0L 315 #define DAGB0_RDCLI13__URG_LOW_MASK 0x00000F00L 316 #define DAGB0_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L 317 #define DAGB0_RDCLI13__MAX_BW_MASK 0x001FE000L 318 #define DAGB0_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L 319 #define DAGB0_RDCLI13__MIN_BW_MASK 0x01C00000L 320 #define DAGB0_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L 321 #define DAGB0_RDCLI13__MAX_OSD_MASK 0xFC000000L 322 //DAGB0_RDCLI14 323 #define DAGB0_RDCLI14__VIRT_CHAN__SHIFT 0x0 324 #define DAGB0_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 325 #define DAGB0_RDCLI14__URG_HIGH__SHIFT 0x4 326 #define DAGB0_RDCLI14__URG_LOW__SHIFT 0x8 327 #define DAGB0_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc 328 #define DAGB0_RDCLI14__MAX_BW__SHIFT 0xd 329 #define DAGB0_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15 330 #define DAGB0_RDCLI14__MIN_BW__SHIFT 0x16 331 #define DAGB0_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 332 #define DAGB0_RDCLI14__MAX_OSD__SHIFT 0x1a 333 #define DAGB0_RDCLI14__VIRT_CHAN_MASK 0x00000007L 334 #define DAGB0_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L 335 #define DAGB0_RDCLI14__URG_HIGH_MASK 0x000000F0L 336 #define DAGB0_RDCLI14__URG_LOW_MASK 0x00000F00L 337 #define DAGB0_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L 338 #define DAGB0_RDCLI14__MAX_BW_MASK 0x001FE000L 339 #define DAGB0_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L 340 #define DAGB0_RDCLI14__MIN_BW_MASK 0x01C00000L 341 #define DAGB0_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L 342 #define DAGB0_RDCLI14__MAX_OSD_MASK 0xFC000000L 343 //DAGB0_RDCLI15 344 #define DAGB0_RDCLI15__VIRT_CHAN__SHIFT 0x0 345 #define DAGB0_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 346 #define DAGB0_RDCLI15__URG_HIGH__SHIFT 0x4 347 #define DAGB0_RDCLI15__URG_LOW__SHIFT 0x8 348 #define DAGB0_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc 349 #define DAGB0_RDCLI15__MAX_BW__SHIFT 0xd 350 #define DAGB0_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15 351 #define DAGB0_RDCLI15__MIN_BW__SHIFT 0x16 352 #define DAGB0_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 353 #define DAGB0_RDCLI15__MAX_OSD__SHIFT 0x1a 354 #define DAGB0_RDCLI15__VIRT_CHAN_MASK 0x00000007L 355 #define DAGB0_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L 356 #define DAGB0_RDCLI15__URG_HIGH_MASK 0x000000F0L 357 #define DAGB0_RDCLI15__URG_LOW_MASK 0x00000F00L 358 #define DAGB0_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L 359 #define DAGB0_RDCLI15__MAX_BW_MASK 0x001FE000L 360 #define DAGB0_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L 361 #define DAGB0_RDCLI15__MIN_BW_MASK 0x01C00000L 362 #define DAGB0_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L 363 #define DAGB0_RDCLI15__MAX_OSD_MASK 0xFC000000L 364 //DAGB0_RDCLI16 365 #define DAGB0_RDCLI16__VIRT_CHAN__SHIFT 0x0 366 #define DAGB0_RDCLI16__CHECK_TLB_CREDIT__SHIFT 0x3 367 #define DAGB0_RDCLI16__URG_HIGH__SHIFT 0x4 368 #define DAGB0_RDCLI16__URG_LOW__SHIFT 0x8 369 #define DAGB0_RDCLI16__MAX_BW_ENABLE__SHIFT 0xc 370 #define DAGB0_RDCLI16__MAX_BW__SHIFT 0xd 371 #define DAGB0_RDCLI16__MIN_BW_ENABLE__SHIFT 0x15 372 #define DAGB0_RDCLI16__MIN_BW__SHIFT 0x16 373 #define DAGB0_RDCLI16__OSD_LIMITER_ENABLE__SHIFT 0x19 374 #define DAGB0_RDCLI16__MAX_OSD__SHIFT 0x1a 375 #define DAGB0_RDCLI16__VIRT_CHAN_MASK 0x00000007L 376 #define DAGB0_RDCLI16__CHECK_TLB_CREDIT_MASK 0x00000008L 377 #define DAGB0_RDCLI16__URG_HIGH_MASK 0x000000F0L 378 #define DAGB0_RDCLI16__URG_LOW_MASK 0x00000F00L 379 #define DAGB0_RDCLI16__MAX_BW_ENABLE_MASK 0x00001000L 380 #define DAGB0_RDCLI16__MAX_BW_MASK 0x001FE000L 381 #define DAGB0_RDCLI16__MIN_BW_ENABLE_MASK 0x00200000L 382 #define DAGB0_RDCLI16__MIN_BW_MASK 0x01C00000L 383 #define DAGB0_RDCLI16__OSD_LIMITER_ENABLE_MASK 0x02000000L 384 #define DAGB0_RDCLI16__MAX_OSD_MASK 0xFC000000L 385 //DAGB0_RDCLI17 386 #define DAGB0_RDCLI17__VIRT_CHAN__SHIFT 0x0 387 #define DAGB0_RDCLI17__CHECK_TLB_CREDIT__SHIFT 0x3 388 #define DAGB0_RDCLI17__URG_HIGH__SHIFT 0x4 389 #define DAGB0_RDCLI17__URG_LOW__SHIFT 0x8 390 #define DAGB0_RDCLI17__MAX_BW_ENABLE__SHIFT 0xc 391 #define DAGB0_RDCLI17__MAX_BW__SHIFT 0xd 392 #define DAGB0_RDCLI17__MIN_BW_ENABLE__SHIFT 0x15 393 #define DAGB0_RDCLI17__MIN_BW__SHIFT 0x16 394 #define DAGB0_RDCLI17__OSD_LIMITER_ENABLE__SHIFT 0x19 395 #define DAGB0_RDCLI17__MAX_OSD__SHIFT 0x1a 396 #define DAGB0_RDCLI17__VIRT_CHAN_MASK 0x00000007L 397 #define DAGB0_RDCLI17__CHECK_TLB_CREDIT_MASK 0x00000008L 398 #define DAGB0_RDCLI17__URG_HIGH_MASK 0x000000F0L 399 #define DAGB0_RDCLI17__URG_LOW_MASK 0x00000F00L 400 #define DAGB0_RDCLI17__MAX_BW_ENABLE_MASK 0x00001000L 401 #define DAGB0_RDCLI17__MAX_BW_MASK 0x001FE000L 402 #define DAGB0_RDCLI17__MIN_BW_ENABLE_MASK 0x00200000L 403 #define DAGB0_RDCLI17__MIN_BW_MASK 0x01C00000L 404 #define DAGB0_RDCLI17__OSD_LIMITER_ENABLE_MASK 0x02000000L 405 #define DAGB0_RDCLI17__MAX_OSD_MASK 0xFC000000L 406 //DAGB0_RDCLI18 407 #define DAGB0_RDCLI18__VIRT_CHAN__SHIFT 0x0 408 #define DAGB0_RDCLI18__CHECK_TLB_CREDIT__SHIFT 0x3 409 #define DAGB0_RDCLI18__URG_HIGH__SHIFT 0x4 410 #define DAGB0_RDCLI18__URG_LOW__SHIFT 0x8 411 #define DAGB0_RDCLI18__MAX_BW_ENABLE__SHIFT 0xc 412 #define DAGB0_RDCLI18__MAX_BW__SHIFT 0xd 413 #define DAGB0_RDCLI18__MIN_BW_ENABLE__SHIFT 0x15 414 #define DAGB0_RDCLI18__MIN_BW__SHIFT 0x16 415 #define DAGB0_RDCLI18__OSD_LIMITER_ENABLE__SHIFT 0x19 416 #define DAGB0_RDCLI18__MAX_OSD__SHIFT 0x1a 417 #define DAGB0_RDCLI18__VIRT_CHAN_MASK 0x00000007L 418 #define DAGB0_RDCLI18__CHECK_TLB_CREDIT_MASK 0x00000008L 419 #define DAGB0_RDCLI18__URG_HIGH_MASK 0x000000F0L 420 #define DAGB0_RDCLI18__URG_LOW_MASK 0x00000F00L 421 #define DAGB0_RDCLI18__MAX_BW_ENABLE_MASK 0x00001000L 422 #define DAGB0_RDCLI18__MAX_BW_MASK 0x001FE000L 423 #define DAGB0_RDCLI18__MIN_BW_ENABLE_MASK 0x00200000L 424 #define DAGB0_RDCLI18__MIN_BW_MASK 0x01C00000L 425 #define DAGB0_RDCLI18__OSD_LIMITER_ENABLE_MASK 0x02000000L 426 #define DAGB0_RDCLI18__MAX_OSD_MASK 0xFC000000L 427 //DAGB0_RD_CNTL 428 #define DAGB0_RD_CNTL__SCLK_FREQ__SHIFT 0x0 429 #define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 430 #define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa 431 #define DAGB0_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 432 #define DAGB0_RD_CNTL__IO_LEVEL__SHIFT 0x11 433 #define DAGB0_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 434 #define DAGB0_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17 435 #define DAGB0_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL 436 #define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L 437 #define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L 438 #define DAGB0_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L 439 #define DAGB0_RD_CNTL__IO_LEVEL_MASK 0x000E0000L 440 #define DAGB0_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L 441 #define DAGB0_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L 442 //DAGB0_RD_GMI_CNTL 443 #define DAGB0_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0 444 #define DAGB0_RD_GMI_CNTL__LEVEL__SHIFT 0x6 445 #define DAGB0_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9 446 #define DAGB0_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd 447 #define DAGB0_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL 448 #define DAGB0_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L 449 #define DAGB0_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L 450 #define DAGB0_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L 451 //DAGB0_RD_ADDR_DAGB 452 #define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 453 #define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 454 #define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 455 #define DAGB0_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7 456 #define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L 457 #define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 458 #define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 459 #define DAGB0_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L 460 //DAGB0_RD_OUTPUT_DAGB_MAX_BURST 461 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 462 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 463 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 464 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc 465 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 466 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 467 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 468 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c 469 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL 470 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L 471 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L 472 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L 473 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L 474 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L 475 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L 476 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L 477 //DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER 478 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 479 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 480 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 481 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc 482 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 483 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 484 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 485 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c 486 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL 487 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L 488 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L 489 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L 490 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L 491 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L 492 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L 493 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L 494 //DAGB0_RD_CGTT_CLK_CTRL 495 #define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 496 #define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 497 #define DAGB0_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 498 #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 499 #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 500 #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 501 #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 502 #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 503 #define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 504 #define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 505 #define DAGB0_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 506 #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 507 #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 508 #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 509 #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 510 #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 511 //DAGB0_L1TLB_RD_CGTT_CLK_CTRL 512 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 513 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 514 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 515 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 516 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 517 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 518 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 519 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 520 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 521 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 522 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 523 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 524 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 525 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 526 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 527 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 528 //DAGB0_ATCVM_RD_CGTT_CLK_CTRL 529 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 530 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 531 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 532 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 533 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 534 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 535 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 536 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 537 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 538 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 539 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 540 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 541 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 542 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 543 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 544 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 545 //DAGB0_RD_ADDR_DAGB_MAX_BURST0 546 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 547 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 548 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 549 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 550 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 551 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 552 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 553 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 554 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 555 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 556 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 557 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 558 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 559 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 560 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 561 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 562 //DAGB0_RD_ADDR_DAGB_LAZY_TIMER0 563 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 564 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 565 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 566 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 567 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 568 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 569 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 570 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 571 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 572 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 573 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 574 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 575 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 576 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 577 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 578 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 579 //DAGB0_RD_ADDR_DAGB_MAX_BURST1 580 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 581 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 582 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 583 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 584 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 585 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 586 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 587 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 588 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 589 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 590 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 591 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 592 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 593 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 594 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 595 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 596 //DAGB0_RD_ADDR_DAGB_LAZY_TIMER1 597 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 598 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 599 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 600 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 601 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 602 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 603 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 604 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 605 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 606 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 607 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 608 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 609 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 610 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 611 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 612 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 613 //DAGB0_RD_ADDR_DAGB_MAX_BURST2 614 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0 615 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4 616 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8 617 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc 618 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10 619 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14 620 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18 621 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c 622 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL 623 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L 624 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L 625 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L 626 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L 627 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L 628 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L 629 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L 630 //DAGB0_RD_ADDR_DAGB_LAZY_TIMER2 631 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0 632 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4 633 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8 634 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc 635 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10 636 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14 637 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18 638 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c 639 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL 640 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L 641 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L 642 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L 643 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L 644 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L 645 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L 646 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L 647 //DAGB0_RD_VC0_CNTL 648 #define DAGB0_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 649 #define DAGB0_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5 650 #define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb 651 #define DAGB0_RD_VC0_CNTL__MAX_BW__SHIFT 0xc 652 #define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 653 #define DAGB0_RD_VC0_CNTL__MIN_BW__SHIFT 0x15 654 #define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 655 #define DAGB0_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19 656 #define DAGB0_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL 657 #define DAGB0_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L 658 #define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 659 #define DAGB0_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L 660 #define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 661 #define DAGB0_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L 662 #define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 663 #define DAGB0_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L 664 //DAGB0_RD_VC1_CNTL 665 #define DAGB0_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 666 #define DAGB0_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5 667 #define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb 668 #define DAGB0_RD_VC1_CNTL__MAX_BW__SHIFT 0xc 669 #define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 670 #define DAGB0_RD_VC1_CNTL__MIN_BW__SHIFT 0x15 671 #define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 672 #define DAGB0_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19 673 #define DAGB0_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL 674 #define DAGB0_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L 675 #define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 676 #define DAGB0_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L 677 #define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 678 #define DAGB0_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L 679 #define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 680 #define DAGB0_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L 681 //DAGB0_RD_VC2_CNTL 682 #define DAGB0_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 683 #define DAGB0_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5 684 #define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb 685 #define DAGB0_RD_VC2_CNTL__MAX_BW__SHIFT 0xc 686 #define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 687 #define DAGB0_RD_VC2_CNTL__MIN_BW__SHIFT 0x15 688 #define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 689 #define DAGB0_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19 690 #define DAGB0_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL 691 #define DAGB0_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L 692 #define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 693 #define DAGB0_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L 694 #define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 695 #define DAGB0_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L 696 #define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 697 #define DAGB0_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L 698 //DAGB0_RD_VC3_CNTL 699 #define DAGB0_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 700 #define DAGB0_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5 701 #define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb 702 #define DAGB0_RD_VC3_CNTL__MAX_BW__SHIFT 0xc 703 #define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 704 #define DAGB0_RD_VC3_CNTL__MIN_BW__SHIFT 0x15 705 #define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 706 #define DAGB0_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19 707 #define DAGB0_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL 708 #define DAGB0_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L 709 #define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 710 #define DAGB0_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L 711 #define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 712 #define DAGB0_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L 713 #define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 714 #define DAGB0_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L 715 //DAGB0_RD_VC4_CNTL 716 #define DAGB0_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 717 #define DAGB0_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5 718 #define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb 719 #define DAGB0_RD_VC4_CNTL__MAX_BW__SHIFT 0xc 720 #define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 721 #define DAGB0_RD_VC4_CNTL__MIN_BW__SHIFT 0x15 722 #define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 723 #define DAGB0_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19 724 #define DAGB0_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL 725 #define DAGB0_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L 726 #define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 727 #define DAGB0_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L 728 #define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 729 #define DAGB0_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L 730 #define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 731 #define DAGB0_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L 732 //DAGB0_RD_VC5_CNTL 733 #define DAGB0_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 734 #define DAGB0_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5 735 #define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb 736 #define DAGB0_RD_VC5_CNTL__MAX_BW__SHIFT 0xc 737 #define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 738 #define DAGB0_RD_VC5_CNTL__MIN_BW__SHIFT 0x15 739 #define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 740 #define DAGB0_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19 741 #define DAGB0_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL 742 #define DAGB0_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L 743 #define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 744 #define DAGB0_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L 745 #define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 746 #define DAGB0_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L 747 #define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 748 #define DAGB0_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L 749 //DAGB0_RD_VC6_CNTL 750 #define DAGB0_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 751 #define DAGB0_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5 752 #define DAGB0_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb 753 #define DAGB0_RD_VC6_CNTL__MAX_BW__SHIFT 0xc 754 #define DAGB0_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 755 #define DAGB0_RD_VC6_CNTL__MIN_BW__SHIFT 0x15 756 #define DAGB0_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 757 #define DAGB0_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19 758 #define DAGB0_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL 759 #define DAGB0_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L 760 #define DAGB0_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 761 #define DAGB0_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L 762 #define DAGB0_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 763 #define DAGB0_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L 764 #define DAGB0_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 765 #define DAGB0_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L 766 //DAGB0_RD_VC7_CNTL 767 #define DAGB0_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 768 #define DAGB0_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5 769 #define DAGB0_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb 770 #define DAGB0_RD_VC7_CNTL__MAX_BW__SHIFT 0xc 771 #define DAGB0_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 772 #define DAGB0_RD_VC7_CNTL__MIN_BW__SHIFT 0x15 773 #define DAGB0_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 774 #define DAGB0_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19 775 #define DAGB0_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL 776 #define DAGB0_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L 777 #define DAGB0_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 778 #define DAGB0_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L 779 #define DAGB0_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 780 #define DAGB0_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L 781 #define DAGB0_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 782 #define DAGB0_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L 783 //DAGB0_RD_CNTL_MISC 784 #define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 785 #define DAGB0_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 786 #define DAGB0_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd 787 #define DAGB0_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 788 #define DAGB0_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 789 #define DAGB0_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15 790 #define DAGB0_RD_CNTL_MISC__HDP_CID__SHIFT 0x1a 791 #define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL 792 #define DAGB0_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L 793 #define DAGB0_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L 794 #define DAGB0_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L 795 #define DAGB0_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L 796 #define DAGB0_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L 797 #define DAGB0_RD_CNTL_MISC__HDP_CID_MASK 0x7C000000L 798 //DAGB0_RD_TLB_CREDIT 799 #define DAGB0_RD_TLB_CREDIT__TLB0__SHIFT 0x0 800 #define DAGB0_RD_TLB_CREDIT__TLB1__SHIFT 0x5 801 #define DAGB0_RD_TLB_CREDIT__TLB2__SHIFT 0xa 802 #define DAGB0_RD_TLB_CREDIT__TLB3__SHIFT 0xf 803 #define DAGB0_RD_TLB_CREDIT__TLB4__SHIFT 0x14 804 #define DAGB0_RD_TLB_CREDIT__TLB5__SHIFT 0x19 805 #define DAGB0_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL 806 #define DAGB0_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L 807 #define DAGB0_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L 808 #define DAGB0_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L 809 #define DAGB0_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L 810 #define DAGB0_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L 811 //DAGB0_RDCLI_ASK_PENDING 812 #define DAGB0_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0 813 #define DAGB0_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 814 //DAGB0_RDCLI_GO_PENDING 815 #define DAGB0_RDCLI_GO_PENDING__BUSY__SHIFT 0x0 816 #define DAGB0_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 817 //DAGB0_RDCLI_GBLSEND_PENDING 818 #define DAGB0_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 819 #define DAGB0_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL 820 //DAGB0_RDCLI_TLB_PENDING 821 #define DAGB0_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0 822 #define DAGB0_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL 823 //DAGB0_RDCLI_OARB_PENDING 824 #define DAGB0_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0 825 #define DAGB0_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL 826 //DAGB0_RDCLI_OSD_PENDING 827 #define DAGB0_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0 828 #define DAGB0_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 829 //DAGB0_WRCLI0 830 #define DAGB0_WRCLI0__VIRT_CHAN__SHIFT 0x0 831 #define DAGB0_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 832 #define DAGB0_WRCLI0__URG_HIGH__SHIFT 0x4 833 #define DAGB0_WRCLI0__URG_LOW__SHIFT 0x8 834 #define DAGB0_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc 835 #define DAGB0_WRCLI0__MAX_BW__SHIFT 0xd 836 #define DAGB0_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15 837 #define DAGB0_WRCLI0__MIN_BW__SHIFT 0x16 838 #define DAGB0_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 839 #define DAGB0_WRCLI0__MAX_OSD__SHIFT 0x1a 840 #define DAGB0_WRCLI0__VIRT_CHAN_MASK 0x00000007L 841 #define DAGB0_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L 842 #define DAGB0_WRCLI0__URG_HIGH_MASK 0x000000F0L 843 #define DAGB0_WRCLI0__URG_LOW_MASK 0x00000F00L 844 #define DAGB0_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L 845 #define DAGB0_WRCLI0__MAX_BW_MASK 0x001FE000L 846 #define DAGB0_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L 847 #define DAGB0_WRCLI0__MIN_BW_MASK 0x01C00000L 848 #define DAGB0_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L 849 #define DAGB0_WRCLI0__MAX_OSD_MASK 0xFC000000L 850 //DAGB0_WRCLI1 851 #define DAGB0_WRCLI1__VIRT_CHAN__SHIFT 0x0 852 #define DAGB0_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 853 #define DAGB0_WRCLI1__URG_HIGH__SHIFT 0x4 854 #define DAGB0_WRCLI1__URG_LOW__SHIFT 0x8 855 #define DAGB0_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc 856 #define DAGB0_WRCLI1__MAX_BW__SHIFT 0xd 857 #define DAGB0_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15 858 #define DAGB0_WRCLI1__MIN_BW__SHIFT 0x16 859 #define DAGB0_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 860 #define DAGB0_WRCLI1__MAX_OSD__SHIFT 0x1a 861 #define DAGB0_WRCLI1__VIRT_CHAN_MASK 0x00000007L 862 #define DAGB0_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L 863 #define DAGB0_WRCLI1__URG_HIGH_MASK 0x000000F0L 864 #define DAGB0_WRCLI1__URG_LOW_MASK 0x00000F00L 865 #define DAGB0_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L 866 #define DAGB0_WRCLI1__MAX_BW_MASK 0x001FE000L 867 #define DAGB0_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L 868 #define DAGB0_WRCLI1__MIN_BW_MASK 0x01C00000L 869 #define DAGB0_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L 870 #define DAGB0_WRCLI1__MAX_OSD_MASK 0xFC000000L 871 //DAGB0_WRCLI2 872 #define DAGB0_WRCLI2__VIRT_CHAN__SHIFT 0x0 873 #define DAGB0_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 874 #define DAGB0_WRCLI2__URG_HIGH__SHIFT 0x4 875 #define DAGB0_WRCLI2__URG_LOW__SHIFT 0x8 876 #define DAGB0_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc 877 #define DAGB0_WRCLI2__MAX_BW__SHIFT 0xd 878 #define DAGB0_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15 879 #define DAGB0_WRCLI2__MIN_BW__SHIFT 0x16 880 #define DAGB0_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 881 #define DAGB0_WRCLI2__MAX_OSD__SHIFT 0x1a 882 #define DAGB0_WRCLI2__VIRT_CHAN_MASK 0x00000007L 883 #define DAGB0_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L 884 #define DAGB0_WRCLI2__URG_HIGH_MASK 0x000000F0L 885 #define DAGB0_WRCLI2__URG_LOW_MASK 0x00000F00L 886 #define DAGB0_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L 887 #define DAGB0_WRCLI2__MAX_BW_MASK 0x001FE000L 888 #define DAGB0_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L 889 #define DAGB0_WRCLI2__MIN_BW_MASK 0x01C00000L 890 #define DAGB0_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L 891 #define DAGB0_WRCLI2__MAX_OSD_MASK 0xFC000000L 892 //DAGB0_WRCLI3 893 #define DAGB0_WRCLI3__VIRT_CHAN__SHIFT 0x0 894 #define DAGB0_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 895 #define DAGB0_WRCLI3__URG_HIGH__SHIFT 0x4 896 #define DAGB0_WRCLI3__URG_LOW__SHIFT 0x8 897 #define DAGB0_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc 898 #define DAGB0_WRCLI3__MAX_BW__SHIFT 0xd 899 #define DAGB0_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15 900 #define DAGB0_WRCLI3__MIN_BW__SHIFT 0x16 901 #define DAGB0_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 902 #define DAGB0_WRCLI3__MAX_OSD__SHIFT 0x1a 903 #define DAGB0_WRCLI3__VIRT_CHAN_MASK 0x00000007L 904 #define DAGB0_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L 905 #define DAGB0_WRCLI3__URG_HIGH_MASK 0x000000F0L 906 #define DAGB0_WRCLI3__URG_LOW_MASK 0x00000F00L 907 #define DAGB0_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L 908 #define DAGB0_WRCLI3__MAX_BW_MASK 0x001FE000L 909 #define DAGB0_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L 910 #define DAGB0_WRCLI3__MIN_BW_MASK 0x01C00000L 911 #define DAGB0_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L 912 #define DAGB0_WRCLI3__MAX_OSD_MASK 0xFC000000L 913 //DAGB0_WRCLI4 914 #define DAGB0_WRCLI4__VIRT_CHAN__SHIFT 0x0 915 #define DAGB0_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 916 #define DAGB0_WRCLI4__URG_HIGH__SHIFT 0x4 917 #define DAGB0_WRCLI4__URG_LOW__SHIFT 0x8 918 #define DAGB0_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc 919 #define DAGB0_WRCLI4__MAX_BW__SHIFT 0xd 920 #define DAGB0_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15 921 #define DAGB0_WRCLI4__MIN_BW__SHIFT 0x16 922 #define DAGB0_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 923 #define DAGB0_WRCLI4__MAX_OSD__SHIFT 0x1a 924 #define DAGB0_WRCLI4__VIRT_CHAN_MASK 0x00000007L 925 #define DAGB0_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L 926 #define DAGB0_WRCLI4__URG_HIGH_MASK 0x000000F0L 927 #define DAGB0_WRCLI4__URG_LOW_MASK 0x00000F00L 928 #define DAGB0_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L 929 #define DAGB0_WRCLI4__MAX_BW_MASK 0x001FE000L 930 #define DAGB0_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L 931 #define DAGB0_WRCLI4__MIN_BW_MASK 0x01C00000L 932 #define DAGB0_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L 933 #define DAGB0_WRCLI4__MAX_OSD_MASK 0xFC000000L 934 //DAGB0_WRCLI5 935 #define DAGB0_WRCLI5__VIRT_CHAN__SHIFT 0x0 936 #define DAGB0_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 937 #define DAGB0_WRCLI5__URG_HIGH__SHIFT 0x4 938 #define DAGB0_WRCLI5__URG_LOW__SHIFT 0x8 939 #define DAGB0_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc 940 #define DAGB0_WRCLI5__MAX_BW__SHIFT 0xd 941 #define DAGB0_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15 942 #define DAGB0_WRCLI5__MIN_BW__SHIFT 0x16 943 #define DAGB0_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 944 #define DAGB0_WRCLI5__MAX_OSD__SHIFT 0x1a 945 #define DAGB0_WRCLI5__VIRT_CHAN_MASK 0x00000007L 946 #define DAGB0_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L 947 #define DAGB0_WRCLI5__URG_HIGH_MASK 0x000000F0L 948 #define DAGB0_WRCLI5__URG_LOW_MASK 0x00000F00L 949 #define DAGB0_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L 950 #define DAGB0_WRCLI5__MAX_BW_MASK 0x001FE000L 951 #define DAGB0_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L 952 #define DAGB0_WRCLI5__MIN_BW_MASK 0x01C00000L 953 #define DAGB0_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L 954 #define DAGB0_WRCLI5__MAX_OSD_MASK 0xFC000000L 955 //DAGB0_WRCLI6 956 #define DAGB0_WRCLI6__VIRT_CHAN__SHIFT 0x0 957 #define DAGB0_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 958 #define DAGB0_WRCLI6__URG_HIGH__SHIFT 0x4 959 #define DAGB0_WRCLI6__URG_LOW__SHIFT 0x8 960 #define DAGB0_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc 961 #define DAGB0_WRCLI6__MAX_BW__SHIFT 0xd 962 #define DAGB0_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15 963 #define DAGB0_WRCLI6__MIN_BW__SHIFT 0x16 964 #define DAGB0_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 965 #define DAGB0_WRCLI6__MAX_OSD__SHIFT 0x1a 966 #define DAGB0_WRCLI6__VIRT_CHAN_MASK 0x00000007L 967 #define DAGB0_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L 968 #define DAGB0_WRCLI6__URG_HIGH_MASK 0x000000F0L 969 #define DAGB0_WRCLI6__URG_LOW_MASK 0x00000F00L 970 #define DAGB0_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L 971 #define DAGB0_WRCLI6__MAX_BW_MASK 0x001FE000L 972 #define DAGB0_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L 973 #define DAGB0_WRCLI6__MIN_BW_MASK 0x01C00000L 974 #define DAGB0_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L 975 #define DAGB0_WRCLI6__MAX_OSD_MASK 0xFC000000L 976 //DAGB0_WRCLI7 977 #define DAGB0_WRCLI7__VIRT_CHAN__SHIFT 0x0 978 #define DAGB0_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 979 #define DAGB0_WRCLI7__URG_HIGH__SHIFT 0x4 980 #define DAGB0_WRCLI7__URG_LOW__SHIFT 0x8 981 #define DAGB0_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc 982 #define DAGB0_WRCLI7__MAX_BW__SHIFT 0xd 983 #define DAGB0_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15 984 #define DAGB0_WRCLI7__MIN_BW__SHIFT 0x16 985 #define DAGB0_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 986 #define DAGB0_WRCLI7__MAX_OSD__SHIFT 0x1a 987 #define DAGB0_WRCLI7__VIRT_CHAN_MASK 0x00000007L 988 #define DAGB0_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L 989 #define DAGB0_WRCLI7__URG_HIGH_MASK 0x000000F0L 990 #define DAGB0_WRCLI7__URG_LOW_MASK 0x00000F00L 991 #define DAGB0_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L 992 #define DAGB0_WRCLI7__MAX_BW_MASK 0x001FE000L 993 #define DAGB0_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L 994 #define DAGB0_WRCLI7__MIN_BW_MASK 0x01C00000L 995 #define DAGB0_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L 996 #define DAGB0_WRCLI7__MAX_OSD_MASK 0xFC000000L 997 //DAGB0_WRCLI8 998 #define DAGB0_WRCLI8__VIRT_CHAN__SHIFT 0x0 999 #define DAGB0_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 1000 #define DAGB0_WRCLI8__URG_HIGH__SHIFT 0x4 1001 #define DAGB0_WRCLI8__URG_LOW__SHIFT 0x8 1002 #define DAGB0_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc 1003 #define DAGB0_WRCLI8__MAX_BW__SHIFT 0xd 1004 #define DAGB0_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15 1005 #define DAGB0_WRCLI8__MIN_BW__SHIFT 0x16 1006 #define DAGB0_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 1007 #define DAGB0_WRCLI8__MAX_OSD__SHIFT 0x1a 1008 #define DAGB0_WRCLI8__VIRT_CHAN_MASK 0x00000007L 1009 #define DAGB0_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L 1010 #define DAGB0_WRCLI8__URG_HIGH_MASK 0x000000F0L 1011 #define DAGB0_WRCLI8__URG_LOW_MASK 0x00000F00L 1012 #define DAGB0_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L 1013 #define DAGB0_WRCLI8__MAX_BW_MASK 0x001FE000L 1014 #define DAGB0_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L 1015 #define DAGB0_WRCLI8__MIN_BW_MASK 0x01C00000L 1016 #define DAGB0_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L 1017 #define DAGB0_WRCLI8__MAX_OSD_MASK 0xFC000000L 1018 //DAGB0_WRCLI9 1019 #define DAGB0_WRCLI9__VIRT_CHAN__SHIFT 0x0 1020 #define DAGB0_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 1021 #define DAGB0_WRCLI9__URG_HIGH__SHIFT 0x4 1022 #define DAGB0_WRCLI9__URG_LOW__SHIFT 0x8 1023 #define DAGB0_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc 1024 #define DAGB0_WRCLI9__MAX_BW__SHIFT 0xd 1025 #define DAGB0_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15 1026 #define DAGB0_WRCLI9__MIN_BW__SHIFT 0x16 1027 #define DAGB0_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 1028 #define DAGB0_WRCLI9__MAX_OSD__SHIFT 0x1a 1029 #define DAGB0_WRCLI9__VIRT_CHAN_MASK 0x00000007L 1030 #define DAGB0_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L 1031 #define DAGB0_WRCLI9__URG_HIGH_MASK 0x000000F0L 1032 #define DAGB0_WRCLI9__URG_LOW_MASK 0x00000F00L 1033 #define DAGB0_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L 1034 #define DAGB0_WRCLI9__MAX_BW_MASK 0x001FE000L 1035 #define DAGB0_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L 1036 #define DAGB0_WRCLI9__MIN_BW_MASK 0x01C00000L 1037 #define DAGB0_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L 1038 #define DAGB0_WRCLI9__MAX_OSD_MASK 0xFC000000L 1039 //DAGB0_WRCLI10 1040 #define DAGB0_WRCLI10__VIRT_CHAN__SHIFT 0x0 1041 #define DAGB0_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 1042 #define DAGB0_WRCLI10__URG_HIGH__SHIFT 0x4 1043 #define DAGB0_WRCLI10__URG_LOW__SHIFT 0x8 1044 #define DAGB0_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc 1045 #define DAGB0_WRCLI10__MAX_BW__SHIFT 0xd 1046 #define DAGB0_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15 1047 #define DAGB0_WRCLI10__MIN_BW__SHIFT 0x16 1048 #define DAGB0_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 1049 #define DAGB0_WRCLI10__MAX_OSD__SHIFT 0x1a 1050 #define DAGB0_WRCLI10__VIRT_CHAN_MASK 0x00000007L 1051 #define DAGB0_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L 1052 #define DAGB0_WRCLI10__URG_HIGH_MASK 0x000000F0L 1053 #define DAGB0_WRCLI10__URG_LOW_MASK 0x00000F00L 1054 #define DAGB0_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L 1055 #define DAGB0_WRCLI10__MAX_BW_MASK 0x001FE000L 1056 #define DAGB0_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L 1057 #define DAGB0_WRCLI10__MIN_BW_MASK 0x01C00000L 1058 #define DAGB0_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L 1059 #define DAGB0_WRCLI10__MAX_OSD_MASK 0xFC000000L 1060 //DAGB0_WRCLI11 1061 #define DAGB0_WRCLI11__VIRT_CHAN__SHIFT 0x0 1062 #define DAGB0_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 1063 #define DAGB0_WRCLI11__URG_HIGH__SHIFT 0x4 1064 #define DAGB0_WRCLI11__URG_LOW__SHIFT 0x8 1065 #define DAGB0_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc 1066 #define DAGB0_WRCLI11__MAX_BW__SHIFT 0xd 1067 #define DAGB0_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15 1068 #define DAGB0_WRCLI11__MIN_BW__SHIFT 0x16 1069 #define DAGB0_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 1070 #define DAGB0_WRCLI11__MAX_OSD__SHIFT 0x1a 1071 #define DAGB0_WRCLI11__VIRT_CHAN_MASK 0x00000007L 1072 #define DAGB0_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L 1073 #define DAGB0_WRCLI11__URG_HIGH_MASK 0x000000F0L 1074 #define DAGB0_WRCLI11__URG_LOW_MASK 0x00000F00L 1075 #define DAGB0_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L 1076 #define DAGB0_WRCLI11__MAX_BW_MASK 0x001FE000L 1077 #define DAGB0_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L 1078 #define DAGB0_WRCLI11__MIN_BW_MASK 0x01C00000L 1079 #define DAGB0_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L 1080 #define DAGB0_WRCLI11__MAX_OSD_MASK 0xFC000000L 1081 //DAGB0_WRCLI12 1082 #define DAGB0_WRCLI12__VIRT_CHAN__SHIFT 0x0 1083 #define DAGB0_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 1084 #define DAGB0_WRCLI12__URG_HIGH__SHIFT 0x4 1085 #define DAGB0_WRCLI12__URG_LOW__SHIFT 0x8 1086 #define DAGB0_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc 1087 #define DAGB0_WRCLI12__MAX_BW__SHIFT 0xd 1088 #define DAGB0_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15 1089 #define DAGB0_WRCLI12__MIN_BW__SHIFT 0x16 1090 #define DAGB0_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 1091 #define DAGB0_WRCLI12__MAX_OSD__SHIFT 0x1a 1092 #define DAGB0_WRCLI12__VIRT_CHAN_MASK 0x00000007L 1093 #define DAGB0_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L 1094 #define DAGB0_WRCLI12__URG_HIGH_MASK 0x000000F0L 1095 #define DAGB0_WRCLI12__URG_LOW_MASK 0x00000F00L 1096 #define DAGB0_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L 1097 #define DAGB0_WRCLI12__MAX_BW_MASK 0x001FE000L 1098 #define DAGB0_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L 1099 #define DAGB0_WRCLI12__MIN_BW_MASK 0x01C00000L 1100 #define DAGB0_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L 1101 #define DAGB0_WRCLI12__MAX_OSD_MASK 0xFC000000L 1102 //DAGB0_WRCLI13 1103 #define DAGB0_WRCLI13__VIRT_CHAN__SHIFT 0x0 1104 #define DAGB0_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 1105 #define DAGB0_WRCLI13__URG_HIGH__SHIFT 0x4 1106 #define DAGB0_WRCLI13__URG_LOW__SHIFT 0x8 1107 #define DAGB0_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc 1108 #define DAGB0_WRCLI13__MAX_BW__SHIFT 0xd 1109 #define DAGB0_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15 1110 #define DAGB0_WRCLI13__MIN_BW__SHIFT 0x16 1111 #define DAGB0_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 1112 #define DAGB0_WRCLI13__MAX_OSD__SHIFT 0x1a 1113 #define DAGB0_WRCLI13__VIRT_CHAN_MASK 0x00000007L 1114 #define DAGB0_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L 1115 #define DAGB0_WRCLI13__URG_HIGH_MASK 0x000000F0L 1116 #define DAGB0_WRCLI13__URG_LOW_MASK 0x00000F00L 1117 #define DAGB0_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L 1118 #define DAGB0_WRCLI13__MAX_BW_MASK 0x001FE000L 1119 #define DAGB0_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L 1120 #define DAGB0_WRCLI13__MIN_BW_MASK 0x01C00000L 1121 #define DAGB0_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L 1122 #define DAGB0_WRCLI13__MAX_OSD_MASK 0xFC000000L 1123 //DAGB0_WRCLI14 1124 #define DAGB0_WRCLI14__VIRT_CHAN__SHIFT 0x0 1125 #define DAGB0_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 1126 #define DAGB0_WRCLI14__URG_HIGH__SHIFT 0x4 1127 #define DAGB0_WRCLI14__URG_LOW__SHIFT 0x8 1128 #define DAGB0_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc 1129 #define DAGB0_WRCLI14__MAX_BW__SHIFT 0xd 1130 #define DAGB0_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15 1131 #define DAGB0_WRCLI14__MIN_BW__SHIFT 0x16 1132 #define DAGB0_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 1133 #define DAGB0_WRCLI14__MAX_OSD__SHIFT 0x1a 1134 #define DAGB0_WRCLI14__VIRT_CHAN_MASK 0x00000007L 1135 #define DAGB0_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L 1136 #define DAGB0_WRCLI14__URG_HIGH_MASK 0x000000F0L 1137 #define DAGB0_WRCLI14__URG_LOW_MASK 0x00000F00L 1138 #define DAGB0_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L 1139 #define DAGB0_WRCLI14__MAX_BW_MASK 0x001FE000L 1140 #define DAGB0_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L 1141 #define DAGB0_WRCLI14__MIN_BW_MASK 0x01C00000L 1142 #define DAGB0_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L 1143 #define DAGB0_WRCLI14__MAX_OSD_MASK 0xFC000000L 1144 //DAGB0_WRCLI15 1145 #define DAGB0_WRCLI15__VIRT_CHAN__SHIFT 0x0 1146 #define DAGB0_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 1147 #define DAGB0_WRCLI15__URG_HIGH__SHIFT 0x4 1148 #define DAGB0_WRCLI15__URG_LOW__SHIFT 0x8 1149 #define DAGB0_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc 1150 #define DAGB0_WRCLI15__MAX_BW__SHIFT 0xd 1151 #define DAGB0_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15 1152 #define DAGB0_WRCLI15__MIN_BW__SHIFT 0x16 1153 #define DAGB0_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 1154 #define DAGB0_WRCLI15__MAX_OSD__SHIFT 0x1a 1155 #define DAGB0_WRCLI15__VIRT_CHAN_MASK 0x00000007L 1156 #define DAGB0_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L 1157 #define DAGB0_WRCLI15__URG_HIGH_MASK 0x000000F0L 1158 #define DAGB0_WRCLI15__URG_LOW_MASK 0x00000F00L 1159 #define DAGB0_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L 1160 #define DAGB0_WRCLI15__MAX_BW_MASK 0x001FE000L 1161 #define DAGB0_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L 1162 #define DAGB0_WRCLI15__MIN_BW_MASK 0x01C00000L 1163 #define DAGB0_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L 1164 #define DAGB0_WRCLI15__MAX_OSD_MASK 0xFC000000L 1165 //DAGB0_WRCLI16 1166 #define DAGB0_WRCLI16__VIRT_CHAN__SHIFT 0x0 1167 #define DAGB0_WRCLI16__CHECK_TLB_CREDIT__SHIFT 0x3 1168 #define DAGB0_WRCLI16__URG_HIGH__SHIFT 0x4 1169 #define DAGB0_WRCLI16__URG_LOW__SHIFT 0x8 1170 #define DAGB0_WRCLI16__MAX_BW_ENABLE__SHIFT 0xc 1171 #define DAGB0_WRCLI16__MAX_BW__SHIFT 0xd 1172 #define DAGB0_WRCLI16__MIN_BW_ENABLE__SHIFT 0x15 1173 #define DAGB0_WRCLI16__MIN_BW__SHIFT 0x16 1174 #define DAGB0_WRCLI16__OSD_LIMITER_ENABLE__SHIFT 0x19 1175 #define DAGB0_WRCLI16__MAX_OSD__SHIFT 0x1a 1176 #define DAGB0_WRCLI16__VIRT_CHAN_MASK 0x00000007L 1177 #define DAGB0_WRCLI16__CHECK_TLB_CREDIT_MASK 0x00000008L 1178 #define DAGB0_WRCLI16__URG_HIGH_MASK 0x000000F0L 1179 #define DAGB0_WRCLI16__URG_LOW_MASK 0x00000F00L 1180 #define DAGB0_WRCLI16__MAX_BW_ENABLE_MASK 0x00001000L 1181 #define DAGB0_WRCLI16__MAX_BW_MASK 0x001FE000L 1182 #define DAGB0_WRCLI16__MIN_BW_ENABLE_MASK 0x00200000L 1183 #define DAGB0_WRCLI16__MIN_BW_MASK 0x01C00000L 1184 #define DAGB0_WRCLI16__OSD_LIMITER_ENABLE_MASK 0x02000000L 1185 #define DAGB0_WRCLI16__MAX_OSD_MASK 0xFC000000L 1186 //DAGB0_WRCLI17 1187 #define DAGB0_WRCLI17__VIRT_CHAN__SHIFT 0x0 1188 #define DAGB0_WRCLI17__CHECK_TLB_CREDIT__SHIFT 0x3 1189 #define DAGB0_WRCLI17__URG_HIGH__SHIFT 0x4 1190 #define DAGB0_WRCLI17__URG_LOW__SHIFT 0x8 1191 #define DAGB0_WRCLI17__MAX_BW_ENABLE__SHIFT 0xc 1192 #define DAGB0_WRCLI17__MAX_BW__SHIFT 0xd 1193 #define DAGB0_WRCLI17__MIN_BW_ENABLE__SHIFT 0x15 1194 #define DAGB0_WRCLI17__MIN_BW__SHIFT 0x16 1195 #define DAGB0_WRCLI17__OSD_LIMITER_ENABLE__SHIFT 0x19 1196 #define DAGB0_WRCLI17__MAX_OSD__SHIFT 0x1a 1197 #define DAGB0_WRCLI17__VIRT_CHAN_MASK 0x00000007L 1198 #define DAGB0_WRCLI17__CHECK_TLB_CREDIT_MASK 0x00000008L 1199 #define DAGB0_WRCLI17__URG_HIGH_MASK 0x000000F0L 1200 #define DAGB0_WRCLI17__URG_LOW_MASK 0x00000F00L 1201 #define DAGB0_WRCLI17__MAX_BW_ENABLE_MASK 0x00001000L 1202 #define DAGB0_WRCLI17__MAX_BW_MASK 0x001FE000L 1203 #define DAGB0_WRCLI17__MIN_BW_ENABLE_MASK 0x00200000L 1204 #define DAGB0_WRCLI17__MIN_BW_MASK 0x01C00000L 1205 #define DAGB0_WRCLI17__OSD_LIMITER_ENABLE_MASK 0x02000000L 1206 #define DAGB0_WRCLI17__MAX_OSD_MASK 0xFC000000L 1207 //DAGB0_WRCLI18 1208 #define DAGB0_WRCLI18__VIRT_CHAN__SHIFT 0x0 1209 #define DAGB0_WRCLI18__CHECK_TLB_CREDIT__SHIFT 0x3 1210 #define DAGB0_WRCLI18__URG_HIGH__SHIFT 0x4 1211 #define DAGB0_WRCLI18__URG_LOW__SHIFT 0x8 1212 #define DAGB0_WRCLI18__MAX_BW_ENABLE__SHIFT 0xc 1213 #define DAGB0_WRCLI18__MAX_BW__SHIFT 0xd 1214 #define DAGB0_WRCLI18__MIN_BW_ENABLE__SHIFT 0x15 1215 #define DAGB0_WRCLI18__MIN_BW__SHIFT 0x16 1216 #define DAGB0_WRCLI18__OSD_LIMITER_ENABLE__SHIFT 0x19 1217 #define DAGB0_WRCLI18__MAX_OSD__SHIFT 0x1a 1218 #define DAGB0_WRCLI18__VIRT_CHAN_MASK 0x00000007L 1219 #define DAGB0_WRCLI18__CHECK_TLB_CREDIT_MASK 0x00000008L 1220 #define DAGB0_WRCLI18__URG_HIGH_MASK 0x000000F0L 1221 #define DAGB0_WRCLI18__URG_LOW_MASK 0x00000F00L 1222 #define DAGB0_WRCLI18__MAX_BW_ENABLE_MASK 0x00001000L 1223 #define DAGB0_WRCLI18__MAX_BW_MASK 0x001FE000L 1224 #define DAGB0_WRCLI18__MIN_BW_ENABLE_MASK 0x00200000L 1225 #define DAGB0_WRCLI18__MIN_BW_MASK 0x01C00000L 1226 #define DAGB0_WRCLI18__OSD_LIMITER_ENABLE_MASK 0x02000000L 1227 #define DAGB0_WRCLI18__MAX_OSD_MASK 0xFC000000L 1228 //DAGB0_WR_CNTL 1229 #define DAGB0_WR_CNTL__SCLK_FREQ__SHIFT 0x0 1230 #define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 1231 #define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa 1232 #define DAGB0_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 1233 #define DAGB0_WR_CNTL__IO_LEVEL__SHIFT 0x11 1234 #define DAGB0_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 1235 #define DAGB0_WR_CNTL__SHARE_VC_NUM__SHIFT 0x17 1236 #define DAGB0_WR_CNTL__SCLK_FREQ_MASK 0x0000000FL 1237 #define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L 1238 #define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L 1239 #define DAGB0_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L 1240 #define DAGB0_WR_CNTL__IO_LEVEL_MASK 0x000E0000L 1241 #define DAGB0_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L 1242 #define DAGB0_WR_CNTL__SHARE_VC_NUM_MASK 0x03800000L 1243 //DAGB0_WR_GMI_CNTL 1244 #define DAGB0_WR_GMI_CNTL__EA_CREDIT__SHIFT 0x0 1245 #define DAGB0_WR_GMI_CNTL__LEVEL__SHIFT 0x6 1246 #define DAGB0_WR_GMI_CNTL__MAX_BURST__SHIFT 0x9 1247 #define DAGB0_WR_GMI_CNTL__LAZY_TIMER__SHIFT 0xd 1248 #define DAGB0_WR_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL 1249 #define DAGB0_WR_GMI_CNTL__LEVEL_MASK 0x000001C0L 1250 #define DAGB0_WR_GMI_CNTL__MAX_BURST_MASK 0x00001E00L 1251 #define DAGB0_WR_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L 1252 //DAGB0_WR_ADDR_DAGB 1253 #define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 1254 #define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 1255 #define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 1256 #define DAGB0_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7 1257 #define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L 1258 #define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 1259 #define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 1260 #define DAGB0_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L 1261 //DAGB0_WR_OUTPUT_DAGB_MAX_BURST 1262 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 1263 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 1264 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 1265 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc 1266 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 1267 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 1268 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 1269 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c 1270 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL 1271 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L 1272 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L 1273 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L 1274 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L 1275 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L 1276 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L 1277 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L 1278 //DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER 1279 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 1280 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 1281 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 1282 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc 1283 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 1284 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 1285 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 1286 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c 1287 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL 1288 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L 1289 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L 1290 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L 1291 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L 1292 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L 1293 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L 1294 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L 1295 //DAGB0_WR_CGTT_CLK_CTRL 1296 #define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 1297 #define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 1298 #define DAGB0_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 1299 #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 1300 #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 1301 #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 1302 #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 1303 #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 1304 #define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 1305 #define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 1306 #define DAGB0_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 1307 #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 1308 #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 1309 #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 1310 #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 1311 #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 1312 //DAGB0_L1TLB_WR_CGTT_CLK_CTRL 1313 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 1314 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 1315 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 1316 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 1317 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 1318 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 1319 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 1320 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 1321 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 1322 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 1323 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 1324 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 1325 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 1326 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 1327 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 1328 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 1329 //DAGB0_ATCVM_WR_CGTT_CLK_CTRL 1330 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 1331 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 1332 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 1333 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 1334 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 1335 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 1336 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 1337 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 1338 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 1339 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 1340 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 1341 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 1342 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 1343 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 1344 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 1345 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 1346 //DAGB0_WR_ADDR_DAGB_MAX_BURST0 1347 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 1348 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 1349 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 1350 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 1351 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 1352 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 1353 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 1354 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 1355 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 1356 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 1357 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 1358 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 1359 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 1360 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 1361 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 1362 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 1363 //DAGB0_WR_ADDR_DAGB_LAZY_TIMER0 1364 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 1365 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 1366 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 1367 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 1368 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 1369 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 1370 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 1371 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 1372 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 1373 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 1374 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 1375 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 1376 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 1377 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 1378 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 1379 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 1380 //DAGB0_WR_ADDR_DAGB_MAX_BURST1 1381 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 1382 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 1383 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 1384 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 1385 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 1386 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 1387 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 1388 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 1389 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 1390 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 1391 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 1392 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 1393 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 1394 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 1395 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 1396 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 1397 //DAGB0_WR_ADDR_DAGB_LAZY_TIMER1 1398 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 1399 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 1400 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 1401 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 1402 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 1403 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 1404 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 1405 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 1406 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 1407 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 1408 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 1409 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 1410 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 1411 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 1412 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 1413 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 1414 //DAGB0_WR_ADDR_DAGB_MAX_BURST2 1415 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0 1416 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4 1417 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8 1418 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc 1419 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10 1420 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14 1421 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18 1422 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c 1423 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL 1424 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L 1425 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L 1426 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L 1427 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L 1428 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L 1429 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L 1430 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L 1431 //DAGB0_WR_ADDR_DAGB_LAZY_TIMER2 1432 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0 1433 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4 1434 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8 1435 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc 1436 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10 1437 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14 1438 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18 1439 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c 1440 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL 1441 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L 1442 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L 1443 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L 1444 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L 1445 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L 1446 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L 1447 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L 1448 //DAGB0_WR_DATA_DAGB 1449 #define DAGB0_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0 1450 #define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 1451 #define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 1452 #define DAGB0_WR_DATA_DAGB__WHOAMI__SHIFT 0x7 1453 #define DAGB0_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L 1454 #define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 1455 #define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 1456 #define DAGB0_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L 1457 //DAGB0_WR_DATA_DAGB_MAX_BURST0 1458 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 1459 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 1460 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 1461 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 1462 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 1463 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 1464 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 1465 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 1466 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 1467 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 1468 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 1469 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 1470 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 1471 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 1472 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 1473 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 1474 //DAGB0_WR_DATA_DAGB_LAZY_TIMER0 1475 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 1476 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 1477 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 1478 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 1479 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 1480 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 1481 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 1482 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 1483 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 1484 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 1485 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 1486 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 1487 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 1488 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 1489 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 1490 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 1491 //DAGB0_WR_DATA_DAGB_MAX_BURST1 1492 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 1493 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 1494 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 1495 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 1496 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 1497 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 1498 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 1499 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 1500 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 1501 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 1502 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 1503 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 1504 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 1505 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 1506 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 1507 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 1508 //DAGB0_WR_DATA_DAGB_LAZY_TIMER1 1509 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 1510 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 1511 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 1512 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 1513 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 1514 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 1515 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 1516 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 1517 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 1518 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 1519 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 1520 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 1521 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 1522 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 1523 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 1524 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 1525 //DAGB0_WR_DATA_DAGB_MAX_BURST2 1526 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0 1527 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4 1528 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8 1529 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc 1530 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10 1531 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14 1532 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18 1533 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c 1534 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL 1535 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L 1536 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L 1537 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L 1538 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L 1539 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L 1540 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L 1541 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L 1542 //DAGB0_WR_DATA_DAGB_LAZY_TIMER2 1543 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0 1544 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4 1545 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8 1546 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc 1547 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10 1548 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14 1549 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18 1550 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c 1551 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL 1552 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L 1553 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L 1554 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L 1555 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L 1556 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L 1557 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L 1558 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L 1559 //DAGB0_WR_VC0_CNTL 1560 #define DAGB0_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 1561 #define DAGB0_WR_VC0_CNTL__EA_CREDIT__SHIFT 0x5 1562 #define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1563 #define DAGB0_WR_VC0_CNTL__MAX_BW__SHIFT 0xc 1564 #define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1565 #define DAGB0_WR_VC0_CNTL__MIN_BW__SHIFT 0x15 1566 #define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1567 #define DAGB0_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19 1568 #define DAGB0_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL 1569 #define DAGB0_WR_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L 1570 #define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1571 #define DAGB0_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L 1572 #define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1573 #define DAGB0_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L 1574 #define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1575 #define DAGB0_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L 1576 //DAGB0_WR_VC1_CNTL 1577 #define DAGB0_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 1578 #define DAGB0_WR_VC1_CNTL__EA_CREDIT__SHIFT 0x5 1579 #define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1580 #define DAGB0_WR_VC1_CNTL__MAX_BW__SHIFT 0xc 1581 #define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1582 #define DAGB0_WR_VC1_CNTL__MIN_BW__SHIFT 0x15 1583 #define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1584 #define DAGB0_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19 1585 #define DAGB0_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL 1586 #define DAGB0_WR_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L 1587 #define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1588 #define DAGB0_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L 1589 #define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1590 #define DAGB0_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L 1591 #define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1592 #define DAGB0_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L 1593 //DAGB0_WR_VC2_CNTL 1594 #define DAGB0_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 1595 #define DAGB0_WR_VC2_CNTL__EA_CREDIT__SHIFT 0x5 1596 #define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1597 #define DAGB0_WR_VC2_CNTL__MAX_BW__SHIFT 0xc 1598 #define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1599 #define DAGB0_WR_VC2_CNTL__MIN_BW__SHIFT 0x15 1600 #define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1601 #define DAGB0_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19 1602 #define DAGB0_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL 1603 #define DAGB0_WR_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L 1604 #define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1605 #define DAGB0_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L 1606 #define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1607 #define DAGB0_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L 1608 #define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1609 #define DAGB0_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L 1610 //DAGB0_WR_VC3_CNTL 1611 #define DAGB0_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 1612 #define DAGB0_WR_VC3_CNTL__EA_CREDIT__SHIFT 0x5 1613 #define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1614 #define DAGB0_WR_VC3_CNTL__MAX_BW__SHIFT 0xc 1615 #define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1616 #define DAGB0_WR_VC3_CNTL__MIN_BW__SHIFT 0x15 1617 #define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1618 #define DAGB0_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19 1619 #define DAGB0_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL 1620 #define DAGB0_WR_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L 1621 #define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1622 #define DAGB0_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L 1623 #define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1624 #define DAGB0_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L 1625 #define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1626 #define DAGB0_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L 1627 //DAGB0_WR_VC4_CNTL 1628 #define DAGB0_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 1629 #define DAGB0_WR_VC4_CNTL__EA_CREDIT__SHIFT 0x5 1630 #define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1631 #define DAGB0_WR_VC4_CNTL__MAX_BW__SHIFT 0xc 1632 #define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1633 #define DAGB0_WR_VC4_CNTL__MIN_BW__SHIFT 0x15 1634 #define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1635 #define DAGB0_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19 1636 #define DAGB0_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL 1637 #define DAGB0_WR_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L 1638 #define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1639 #define DAGB0_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L 1640 #define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1641 #define DAGB0_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L 1642 #define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1643 #define DAGB0_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L 1644 //DAGB0_WR_VC5_CNTL 1645 #define DAGB0_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 1646 #define DAGB0_WR_VC5_CNTL__EA_CREDIT__SHIFT 0x5 1647 #define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1648 #define DAGB0_WR_VC5_CNTL__MAX_BW__SHIFT 0xc 1649 #define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1650 #define DAGB0_WR_VC5_CNTL__MIN_BW__SHIFT 0x15 1651 #define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1652 #define DAGB0_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19 1653 #define DAGB0_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL 1654 #define DAGB0_WR_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L 1655 #define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1656 #define DAGB0_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L 1657 #define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1658 #define DAGB0_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L 1659 #define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1660 #define DAGB0_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L 1661 //DAGB0_WR_VC6_CNTL 1662 #define DAGB0_WR_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 1663 #define DAGB0_WR_VC6_CNTL__EA_CREDIT__SHIFT 0x5 1664 #define DAGB0_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1665 #define DAGB0_WR_VC6_CNTL__MAX_BW__SHIFT 0xc 1666 #define DAGB0_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1667 #define DAGB0_WR_VC6_CNTL__MIN_BW__SHIFT 0x15 1668 #define DAGB0_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1669 #define DAGB0_WR_VC6_CNTL__MAX_OSD__SHIFT 0x19 1670 #define DAGB0_WR_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL 1671 #define DAGB0_WR_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L 1672 #define DAGB0_WR_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1673 #define DAGB0_WR_VC6_CNTL__MAX_BW_MASK 0x000FF000L 1674 #define DAGB0_WR_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1675 #define DAGB0_WR_VC6_CNTL__MIN_BW_MASK 0x00E00000L 1676 #define DAGB0_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1677 #define DAGB0_WR_VC6_CNTL__MAX_OSD_MASK 0xFE000000L 1678 //DAGB0_WR_VC7_CNTL 1679 #define DAGB0_WR_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 1680 #define DAGB0_WR_VC7_CNTL__EA_CREDIT__SHIFT 0x5 1681 #define DAGB0_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1682 #define DAGB0_WR_VC7_CNTL__MAX_BW__SHIFT 0xc 1683 #define DAGB0_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1684 #define DAGB0_WR_VC7_CNTL__MIN_BW__SHIFT 0x15 1685 #define DAGB0_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1686 #define DAGB0_WR_VC7_CNTL__MAX_OSD__SHIFT 0x19 1687 #define DAGB0_WR_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL 1688 #define DAGB0_WR_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L 1689 #define DAGB0_WR_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1690 #define DAGB0_WR_VC7_CNTL__MAX_BW_MASK 0x000FF000L 1691 #define DAGB0_WR_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1692 #define DAGB0_WR_VC7_CNTL__MIN_BW_MASK 0x00E00000L 1693 #define DAGB0_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1694 #define DAGB0_WR_VC7_CNTL__MAX_OSD_MASK 0xFE000000L 1695 //DAGB0_WR_CNTL_MISC 1696 #define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 1697 #define DAGB0_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 1698 #define DAGB0_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd 1699 #define DAGB0_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 1700 #define DAGB0_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 1701 #define DAGB0_WR_CNTL_MISC__UTCL2_CID__SHIFT 0x15 1702 #define DAGB0_WR_CNTL_MISC__HDP_CID__SHIFT 0x1a 1703 #define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL 1704 #define DAGB0_WR_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L 1705 #define DAGB0_WR_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L 1706 #define DAGB0_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L 1707 #define DAGB0_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L 1708 #define DAGB0_WR_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L 1709 #define DAGB0_WR_CNTL_MISC__HDP_CID_MASK 0x7C000000L 1710 //DAGB0_WR_TLB_CREDIT 1711 #define DAGB0_WR_TLB_CREDIT__TLB0__SHIFT 0x0 1712 #define DAGB0_WR_TLB_CREDIT__TLB1__SHIFT 0x5 1713 #define DAGB0_WR_TLB_CREDIT__TLB2__SHIFT 0xa 1714 #define DAGB0_WR_TLB_CREDIT__TLB3__SHIFT 0xf 1715 #define DAGB0_WR_TLB_CREDIT__TLB4__SHIFT 0x14 1716 #define DAGB0_WR_TLB_CREDIT__TLB5__SHIFT 0x19 1717 #define DAGB0_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL 1718 #define DAGB0_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L 1719 #define DAGB0_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L 1720 #define DAGB0_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L 1721 #define DAGB0_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L 1722 #define DAGB0_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L 1723 //DAGB0_WR_DATA_CREDIT 1724 #define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0 1725 #define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8 1726 #define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10 1727 #define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18 1728 #define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL 1729 #define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L 1730 #define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L 1731 #define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L 1732 //DAGB0_WR_MISC_CREDIT 1733 #define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0 1734 #define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6 1735 #define DAGB0_WR_MISC_CREDIT__OSD_CREDIT__SHIFT 0x9 1736 #define DAGB0_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT 0x10 1737 #define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL 1738 #define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L 1739 #define DAGB0_WR_MISC_CREDIT__OSD_CREDIT_MASK 0x0000FE00L 1740 #define DAGB0_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK 0x007F0000L 1741 //DAGB0_WRCLI_ASK_PENDING 1742 #define DAGB0_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0 1743 #define DAGB0_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 1744 //DAGB0_WRCLI_GO_PENDING 1745 #define DAGB0_WRCLI_GO_PENDING__BUSY__SHIFT 0x0 1746 #define DAGB0_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 1747 //DAGB0_WRCLI_GBLSEND_PENDING 1748 #define DAGB0_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 1749 #define DAGB0_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL 1750 //DAGB0_WRCLI_TLB_PENDING 1751 #define DAGB0_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0 1752 #define DAGB0_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL 1753 //DAGB0_WRCLI_OARB_PENDING 1754 #define DAGB0_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0 1755 #define DAGB0_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL 1756 //DAGB0_WRCLI_OSD_PENDING 1757 #define DAGB0_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0 1758 #define DAGB0_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 1759 //DAGB0_WRCLI_DBUS_ASK_PENDING 1760 #define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0 1761 #define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 1762 //DAGB0_WRCLI_DBUS_GO_PENDING 1763 #define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0 1764 #define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 1765 //DAGB0_WRCLI_GPU_SNOOP_OVERRIDE 1766 #define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE__SHIFT 0x0 1767 #define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE_MASK 0xFFFFFFFFL 1768 //DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 1769 #define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE__SHIFT 0x0 1770 #define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE_MASK 0xFFFFFFFFL 1771 //DAGB0_DAGB_DLY 1772 #define DAGB0_DAGB_DLY__DLY__SHIFT 0x0 1773 #define DAGB0_DAGB_DLY__CLI__SHIFT 0x8 1774 #define DAGB0_DAGB_DLY__POS__SHIFT 0x10 1775 #define DAGB0_DAGB_DLY__DLY_MASK 0x000000FFL 1776 #define DAGB0_DAGB_DLY__CLI_MASK 0x0000FF00L 1777 #define DAGB0_DAGB_DLY__POS_MASK 0x000F0000L 1778 //DAGB0_CNTL_MISC 1779 #define DAGB0_CNTL_MISC__EA_VC0_REMAP__SHIFT 0x0 1780 #define DAGB0_CNTL_MISC__EA_VC1_REMAP__SHIFT 0x3 1781 #define DAGB0_CNTL_MISC__EA_VC2_REMAP__SHIFT 0x6 1782 #define DAGB0_CNTL_MISC__EA_VC3_REMAP__SHIFT 0x9 1783 #define DAGB0_CNTL_MISC__EA_VC4_REMAP__SHIFT 0xc 1784 #define DAGB0_CNTL_MISC__EA_VC5_REMAP__SHIFT 0xf 1785 #define DAGB0_CNTL_MISC__EA_VC6_REMAP__SHIFT 0x12 1786 #define DAGB0_CNTL_MISC__EA_VC7_REMAP__SHIFT 0x15 1787 #define DAGB0_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x18 1788 #define DAGB0_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT 0x1e 1789 #define DAGB0_CNTL_MISC__EA_VC0_REMAP_MASK 0x00000007L 1790 #define DAGB0_CNTL_MISC__EA_VC1_REMAP_MASK 0x00000038L 1791 #define DAGB0_CNTL_MISC__EA_VC2_REMAP_MASK 0x000001C0L 1792 #define DAGB0_CNTL_MISC__EA_VC3_REMAP_MASK 0x00000E00L 1793 #define DAGB0_CNTL_MISC__EA_VC4_REMAP_MASK 0x00007000L 1794 #define DAGB0_CNTL_MISC__EA_VC5_REMAP_MASK 0x00038000L 1795 #define DAGB0_CNTL_MISC__EA_VC6_REMAP_MASK 0x001C0000L 1796 #define DAGB0_CNTL_MISC__EA_VC7_REMAP_MASK 0x00E00000L 1797 #define DAGB0_CNTL_MISC__BW_INIT_CYCLE_MASK 0x3F000000L 1798 #define DAGB0_CNTL_MISC__BW_RW_GAP_CYCLE_MASK 0xC0000000L 1799 //DAGB0_CNTL_MISC2 1800 #define DAGB0_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT 0x0 1801 #define DAGB0_CNTL_MISC2__URG_HALT_ENABLE__SHIFT 0x1 1802 #define DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT 0x2 1803 #define DAGB0_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT 0x3 1804 #define DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT 0x4 1805 #define DAGB0_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT 0x5 1806 #define DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT 0x6 1807 #define DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT 0x7 1808 #define DAGB0_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT 0x8 1809 #define DAGB0_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT 0x9 1810 #define DAGB0_CNTL_MISC2__SWAP_CTL__SHIFT 0xa 1811 #define DAGB0_CNTL_MISC2__ENABLE_PARITY_CHECK__SHIFT 0xb 1812 #define DAGB0_CNTL_MISC2__URG_BOOST_ENABLE_MASK 0x00000001L 1813 #define DAGB0_CNTL_MISC2__URG_HALT_ENABLE_MASK 0x00000002L 1814 #define DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK 0x00000004L 1815 #define DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK 0x00000008L 1816 #define DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK 0x00000010L 1817 #define DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK 0x00000020L 1818 #define DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK 0x00000040L 1819 #define DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK 0x00000080L 1820 #define DAGB0_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK 0x00000100L 1821 #define DAGB0_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK 0x00000200L 1822 #define DAGB0_CNTL_MISC2__SWAP_CTL_MASK 0x00000400L 1823 #define DAGB0_CNTL_MISC2__ENABLE_PARITY_CHECK_MASK 0x00000800L 1824 //DAGB0_FIFO_EMPTY 1825 #define DAGB0_FIFO_EMPTY__EMPTY__SHIFT 0x0 1826 #define DAGB0_FIFO_EMPTY__EMPTY_MASK 0x00FFFFFFL 1827 //DAGB0_FIFO_FULL 1828 #define DAGB0_FIFO_FULL__FULL__SHIFT 0x0 1829 #define DAGB0_FIFO_FULL__FULL_MASK 0x007FFFFFL 1830 //DAGB0_WR_CREDITS_FULL 1831 #define DAGB0_WR_CREDITS_FULL__FULL__SHIFT 0x0 1832 #define DAGB0_WR_CREDITS_FULL__FULL_MASK 0x0007FFFFL 1833 //DAGB0_RD_CREDITS_FULL 1834 #define DAGB0_RD_CREDITS_FULL__FULL__SHIFT 0x0 1835 #define DAGB0_RD_CREDITS_FULL__FULL_MASK 0x0003FFFFL 1836 //DAGB0_PERFCOUNTER_LO 1837 #define DAGB0_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 1838 #define DAGB0_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 1839 //DAGB0_PERFCOUNTER_HI 1840 #define DAGB0_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 1841 #define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 1842 #define DAGB0_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 1843 #define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 1844 //DAGB0_PERFCOUNTER0_CFG 1845 #define DAGB0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 1846 #define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 1847 #define DAGB0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 1848 #define DAGB0_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 1849 #define DAGB0_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 1850 #define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 1851 #define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 1852 #define DAGB0_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 1853 #define DAGB0_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 1854 #define DAGB0_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 1855 //DAGB0_PERFCOUNTER1_CFG 1856 #define DAGB0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 1857 #define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 1858 #define DAGB0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 1859 #define DAGB0_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 1860 #define DAGB0_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 1861 #define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 1862 #define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 1863 #define DAGB0_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 1864 #define DAGB0_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 1865 #define DAGB0_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 1866 //DAGB0_PERFCOUNTER2_CFG 1867 #define DAGB0_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 1868 #define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 1869 #define DAGB0_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 1870 #define DAGB0_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 1871 #define DAGB0_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 1872 #define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 1873 #define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 1874 #define DAGB0_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 1875 #define DAGB0_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 1876 #define DAGB0_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 1877 //DAGB0_PERFCOUNTER_RSLT_CNTL 1878 #define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 1879 #define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 1880 #define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 1881 #define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 1882 #define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 1883 #define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 1884 #define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 1885 #define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 1886 #define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 1887 #define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 1888 #define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 1889 #define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 1890 //DAGB0_RESERVE0 1891 #define DAGB0_RESERVE0__RESERVE__SHIFT 0x0 1892 #define DAGB0_RESERVE0__RESERVE_MASK 0xFFFFFFFFL 1893 //DAGB0_RESERVE1 1894 #define DAGB0_RESERVE1__RESERVE__SHIFT 0x0 1895 #define DAGB0_RESERVE1__RESERVE_MASK 0xFFFFFFFFL 1896 //DAGB0_RESERVE2 1897 #define DAGB0_RESERVE2__RESERVE__SHIFT 0x0 1898 #define DAGB0_RESERVE2__RESERVE_MASK 0xFFFFFFFFL 1899 //DAGB0_RESERVE3 1900 #define DAGB0_RESERVE3__RESERVE__SHIFT 0x0 1901 #define DAGB0_RESERVE3__RESERVE_MASK 0xFFFFFFFFL 1902 //DAGB0_RESERVE4 1903 #define DAGB0_RESERVE4__RESERVE__SHIFT 0x0 1904 #define DAGB0_RESERVE4__RESERVE_MASK 0xFFFFFFFFL 1905 //DAGB0_RESERVE5 1906 #define DAGB0_RESERVE5__RESERVE__SHIFT 0x0 1907 #define DAGB0_RESERVE5__RESERVE_MASK 0xFFFFFFFFL 1908 //DAGB0_RESERVE6 1909 #define DAGB0_RESERVE6__RESERVE__SHIFT 0x0 1910 #define DAGB0_RESERVE6__RESERVE_MASK 0xFFFFFFFFL 1911 //DAGB0_RESERVE7 1912 #define DAGB0_RESERVE7__RESERVE__SHIFT 0x0 1913 #define DAGB0_RESERVE7__RESERVE_MASK 0xFFFFFFFFL 1914 //DAGB0_RESERVE8 1915 #define DAGB0_RESERVE8__RESERVE__SHIFT 0x0 1916 #define DAGB0_RESERVE8__RESERVE_MASK 0xFFFFFFFFL 1917 //DAGB0_RESERVE9 1918 #define DAGB0_RESERVE9__RESERVE__SHIFT 0x0 1919 #define DAGB0_RESERVE9__RESERVE_MASK 0xFFFFFFFFL 1920 //DAGB0_RESERVE10 1921 #define DAGB0_RESERVE10__RESERVE__SHIFT 0x0 1922 #define DAGB0_RESERVE10__RESERVE_MASK 0xFFFFFFFFL 1923 //DAGB0_RESERVE11 1924 #define DAGB0_RESERVE11__RESERVE__SHIFT 0x0 1925 #define DAGB0_RESERVE11__RESERVE_MASK 0xFFFFFFFFL 1926 //DAGB0_RESERVE12 1927 #define DAGB0_RESERVE12__RESERVE__SHIFT 0x0 1928 #define DAGB0_RESERVE12__RESERVE_MASK 0xFFFFFFFFL 1929 //DAGB0_RESERVE13 1930 #define DAGB0_RESERVE13__RESERVE__SHIFT 0x0 1931 #define DAGB0_RESERVE13__RESERVE_MASK 0xFFFFFFFFL 1932 //DAGB0_RESERVE14 1933 #define DAGB0_RESERVE14__RESERVE__SHIFT 0x0 1934 #define DAGB0_RESERVE14__RESERVE_MASK 0xFFFFFFFFL 1935 //DAGB0_RESERVE15 1936 #define DAGB0_RESERVE15__RESERVE__SHIFT 0x0 1937 #define DAGB0_RESERVE15__RESERVE_MASK 0xFFFFFFFFL 1938 //DAGB0_RESERVE16 1939 #define DAGB0_RESERVE16__RESERVE__SHIFT 0x0 1940 #define DAGB0_RESERVE16__RESERVE_MASK 0xFFFFFFFFL 1941 //DAGB0_RESERVE17 1942 #define DAGB0_RESERVE17__RESERVE__SHIFT 0x0 1943 #define DAGB0_RESERVE17__RESERVE_MASK 0xFFFFFFFFL 1944 //DAGB0_RESERVE18 1945 #define DAGB0_RESERVE18__RESERVE__SHIFT 0x0 1946 #define DAGB0_RESERVE18__RESERVE_MASK 0xFFFFFFFFL 1947 //DAGB0_RESERVE19 1948 #define DAGB0_RESERVE19__RESERVE__SHIFT 0x0 1949 #define DAGB0_RESERVE19__RESERVE_MASK 0xFFFFFFFFL 1950 //DAGB0_RESERVE20 1951 #define DAGB0_RESERVE20__RESERVE__SHIFT 0x0 1952 #define DAGB0_RESERVE20__RESERVE_MASK 0xFFFFFFFFL 1953 //DAGB0_RESERVE21 1954 #define DAGB0_RESERVE21__RESERVE__SHIFT 0x0 1955 #define DAGB0_RESERVE21__RESERVE_MASK 0xFFFFFFFFL 1956 //DAGB0_RESERVE22 1957 #define DAGB0_RESERVE22__RESERVE__SHIFT 0x0 1958 #define DAGB0_RESERVE22__RESERVE_MASK 0xFFFFFFFFL 1959 //DAGB0_RESERVE23 1960 #define DAGB0_RESERVE23__RESERVE__SHIFT 0x0 1961 #define DAGB0_RESERVE23__RESERVE_MASK 0xFFFFFFFFL 1962 //DAGB0_RESERVE24 1963 #define DAGB0_RESERVE24__RESERVE__SHIFT 0x0 1964 #define DAGB0_RESERVE24__RESERVE_MASK 0xFFFFFFFFL 1965 //DAGB0_RESERVE25 1966 #define DAGB0_RESERVE25__RESERVE__SHIFT 0x0 1967 #define DAGB0_RESERVE25__RESERVE_MASK 0xFFFFFFFFL 1968 //DAGB0_RESERVE26 1969 #define DAGB0_RESERVE26__RESERVE__SHIFT 0x0 1970 #define DAGB0_RESERVE26__RESERVE_MASK 0xFFFFFFFFL 1971 //DAGB0_RESERVE27 1972 #define DAGB0_RESERVE27__RESERVE__SHIFT 0x0 1973 #define DAGB0_RESERVE27__RESERVE_MASK 0xFFFFFFFFL 1974 //DAGB0_RESERVE28 1975 #define DAGB0_RESERVE28__RESERVE__SHIFT 0x0 1976 #define DAGB0_RESERVE28__RESERVE_MASK 0xFFFFFFFFL 1977 //DAGB0_RESERVE29 1978 #define DAGB0_RESERVE29__RESERVE__SHIFT 0x0 1979 #define DAGB0_RESERVE29__RESERVE_MASK 0xFFFFFFFFL 1980 //DAGB0_RESERVE30 1981 #define DAGB0_RESERVE30__RESERVE__SHIFT 0x0 1982 #define DAGB0_RESERVE30__RESERVE_MASK 0xFFFFFFFFL 1983 //DAGB0_RESERVE31 1984 #define DAGB0_RESERVE31__RESERVE__SHIFT 0x0 1985 #define DAGB0_RESERVE31__RESERVE_MASK 0xFFFFFFFFL 1986 //DAGB0_RESERVE32 1987 #define DAGB0_RESERVE32__RESERVE__SHIFT 0x0 1988 #define DAGB0_RESERVE32__RESERVE_MASK 0xFFFFFFFFL 1989 //DAGB0_RESERVE33 1990 #define DAGB0_RESERVE33__RESERVE__SHIFT 0x0 1991 #define DAGB0_RESERVE33__RESERVE_MASK 0xFFFFFFFFL 1992 //DAGB0_RESERVE34 1993 #define DAGB0_RESERVE34__RESERVE__SHIFT 0x0 1994 #define DAGB0_RESERVE34__RESERVE_MASK 0xFFFFFFFFL 1995 //DAGB0_RESERVE35 1996 #define DAGB0_RESERVE35__RESERVE__SHIFT 0x0 1997 #define DAGB0_RESERVE35__RESERVE_MASK 0xFFFFFFFFL 1998 //DAGB0_RESERVE36 1999 #define DAGB0_RESERVE36__RESERVE__SHIFT 0x0 2000 #define DAGB0_RESERVE36__RESERVE_MASK 0xFFFFFFFFL 2001 //DAGB0_RESERVE37 2002 #define DAGB0_RESERVE37__RESERVE__SHIFT 0x0 2003 #define DAGB0_RESERVE37__RESERVE_MASK 0xFFFFFFFFL 2004 //DAGB0_RESERVE38 2005 #define DAGB0_RESERVE38__RESERVE__SHIFT 0x0 2006 #define DAGB0_RESERVE38__RESERVE_MASK 0xFFFFFFFFL 2007 //DAGB0_RESERVE39 2008 #define DAGB0_RESERVE39__RESERVE__SHIFT 0x0 2009 #define DAGB0_RESERVE39__RESERVE_MASK 0xFFFFFFFFL 2010 //DAGB0_RESERVE40 2011 #define DAGB0_RESERVE40__RESERVE__SHIFT 0x0 2012 #define DAGB0_RESERVE40__RESERVE_MASK 0xFFFFFFFFL 2013 //DAGB0_RESERVE41 2014 #define DAGB0_RESERVE41__RESERVE__SHIFT 0x0 2015 #define DAGB0_RESERVE41__RESERVE_MASK 0xFFFFFFFFL 2016 //DAGB0_RESERVE42 2017 #define DAGB0_RESERVE42__RESERVE__SHIFT 0x0 2018 #define DAGB0_RESERVE42__RESERVE_MASK 0xFFFFFFFFL 2019 //DAGB0_RESERVE43 2020 #define DAGB0_RESERVE43__RESERVE__SHIFT 0x0 2021 #define DAGB0_RESERVE43__RESERVE_MASK 0xFFFFFFFFL 2022 //DAGB0_RESERVE44 2023 #define DAGB0_RESERVE44__RESERVE__SHIFT 0x0 2024 #define DAGB0_RESERVE44__RESERVE_MASK 0xFFFFFFFFL 2025 //DAGB0_RESERVE45 2026 #define DAGB0_RESERVE45__RESERVE__SHIFT 0x0 2027 #define DAGB0_RESERVE45__RESERVE_MASK 0xFFFFFFFFL 2028 //DAGB0_RESERVE46 2029 #define DAGB0_RESERVE46__RESERVE__SHIFT 0x0 2030 #define DAGB0_RESERVE46__RESERVE_MASK 0xFFFFFFFFL 2031 //DAGB0_RESERVE47 2032 #define DAGB0_RESERVE47__RESERVE__SHIFT 0x0 2033 #define DAGB0_RESERVE47__RESERVE_MASK 0xFFFFFFFFL 2034 //DAGB0_RESERVE48 2035 #define DAGB0_RESERVE48__RESERVE__SHIFT 0x0 2036 #define DAGB0_RESERVE48__RESERVE_MASK 0xFFFFFFFFL 2037 //DAGB0_RESERVE49 2038 #define DAGB0_RESERVE49__RESERVE__SHIFT 0x0 2039 #define DAGB0_RESERVE49__RESERVE_MASK 0xFFFFFFFFL 2040 //DAGB0_RESERVE50 2041 #define DAGB0_RESERVE50__RESERVE__SHIFT 0x0 2042 #define DAGB0_RESERVE50__RESERVE_MASK 0xFFFFFFFFL 2043 //DAGB0_RESERVE51 2044 #define DAGB0_RESERVE51__RESERVE__SHIFT 0x0 2045 #define DAGB0_RESERVE51__RESERVE_MASK 0xFFFFFFFFL 2046 //DAGB0_RESERVE52 2047 #define DAGB0_RESERVE52__RESERVE__SHIFT 0x0 2048 #define DAGB0_RESERVE52__RESERVE_MASK 0xFFFFFFFFL 2049 //DAGB0_RESERVE53 2050 #define DAGB0_RESERVE53__RESERVE__SHIFT 0x0 2051 #define DAGB0_RESERVE53__RESERVE_MASK 0xFFFFFFFFL 2052 //DAGB0_RESERVE54 2053 #define DAGB0_RESERVE54__RESERVE__SHIFT 0x0 2054 #define DAGB0_RESERVE54__RESERVE_MASK 0xFFFFFFFFL 2055 //DAGB0_RESERVE55 2056 #define DAGB0_RESERVE55__RESERVE__SHIFT 0x0 2057 #define DAGB0_RESERVE55__RESERVE_MASK 0xFFFFFFFFL 2058 //DAGB0_RESERVE56 2059 #define DAGB0_RESERVE56__RESERVE__SHIFT 0x0 2060 #define DAGB0_RESERVE56__RESERVE_MASK 0xFFFFFFFFL 2061 //DAGB0_RESERVE57 2062 #define DAGB0_RESERVE57__RESERVE__SHIFT 0x0 2063 #define DAGB0_RESERVE57__RESERVE_MASK 0xFFFFFFFFL 2064 //DAGB0_RESERVE58 2065 #define DAGB0_RESERVE58__RESERVE__SHIFT 0x0 2066 #define DAGB0_RESERVE58__RESERVE_MASK 0xFFFFFFFFL 2067 //DAGB0_RESERVE59 2068 #define DAGB0_RESERVE59__RESERVE__SHIFT 0x0 2069 #define DAGB0_RESERVE59__RESERVE_MASK 0xFFFFFFFFL 2070 //DAGB0_RESERVE60 2071 #define DAGB0_RESERVE60__RESERVE__SHIFT 0x0 2072 #define DAGB0_RESERVE60__RESERVE_MASK 0xFFFFFFFFL 2073 //DAGB0_RESERVE61 2074 #define DAGB0_RESERVE61__RESERVE__SHIFT 0x0 2075 #define DAGB0_RESERVE61__RESERVE_MASK 0xFFFFFFFFL 2076 //DAGB0_RESERVE62 2077 #define DAGB0_RESERVE62__RESERVE__SHIFT 0x0 2078 #define DAGB0_RESERVE62__RESERVE_MASK 0xFFFFFFFFL 2079 //DAGB0_RESERVE63 2080 #define DAGB0_RESERVE63__RESERVE__SHIFT 0x0 2081 #define DAGB0_RESERVE63__RESERVE_MASK 0xFFFFFFFFL 2082 //DAGB0_RESERVE64 2083 #define DAGB0_RESERVE64__RESERVE__SHIFT 0x0 2084 #define DAGB0_RESERVE64__RESERVE_MASK 0xFFFFFFFFL 2085 //DAGB0_RESERVE65 2086 #define DAGB0_RESERVE65__RESERVE__SHIFT 0x0 2087 #define DAGB0_RESERVE65__RESERVE_MASK 0xFFFFFFFFL 2088 //DAGB0_RESERVE66 2089 #define DAGB0_RESERVE66__RESERVE__SHIFT 0x0 2090 #define DAGB0_RESERVE66__RESERVE_MASK 0xFFFFFFFFL 2091 //DAGB0_RESERVE67 2092 #define DAGB0_RESERVE67__RESERVE__SHIFT 0x0 2093 #define DAGB0_RESERVE67__RESERVE_MASK 0xFFFFFFFFL 2094 //DAGB0_RESERVE68 2095 #define DAGB0_RESERVE68__RESERVE__SHIFT 0x0 2096 #define DAGB0_RESERVE68__RESERVE_MASK 0xFFFFFFFFL 2097 //DAGB0_RESERVE69 2098 #define DAGB0_RESERVE69__RESERVE__SHIFT 0x0 2099 #define DAGB0_RESERVE69__RESERVE_MASK 0xFFFFFFFFL 2100 //DAGB0_RESERVE70 2101 #define DAGB0_RESERVE70__RESERVE__SHIFT 0x0 2102 #define DAGB0_RESERVE70__RESERVE_MASK 0xFFFFFFFFL 2103 //DAGB0_RESERVE71 2104 #define DAGB0_RESERVE71__RESERVE__SHIFT 0x0 2105 #define DAGB0_RESERVE71__RESERVE_MASK 0xFFFFFFFFL 2106 //DAGB0_RESERVE72 2107 #define DAGB0_RESERVE72__RESERVE__SHIFT 0x0 2108 #define DAGB0_RESERVE72__RESERVE_MASK 0xFFFFFFFFL 2109 //DAGB0_RESERVE73 2110 #define DAGB0_RESERVE73__RESERVE__SHIFT 0x0 2111 #define DAGB0_RESERVE73__RESERVE_MASK 0xFFFFFFFFL 2112 //DAGB0_RESERVE74 2113 #define DAGB0_RESERVE74__RESERVE__SHIFT 0x0 2114 #define DAGB0_RESERVE74__RESERVE_MASK 0xFFFFFFFFL 2115 //DAGB0_RESERVE75 2116 #define DAGB0_RESERVE75__RESERVE__SHIFT 0x0 2117 #define DAGB0_RESERVE75__RESERVE_MASK 0xFFFFFFFFL 2118 //DAGB0_RESERVE76 2119 #define DAGB0_RESERVE76__RESERVE__SHIFT 0x0 2120 #define DAGB0_RESERVE76__RESERVE_MASK 0xFFFFFFFFL 2121 //DAGB0_RESERVE77 2122 #define DAGB0_RESERVE77__RESERVE__SHIFT 0x0 2123 #define DAGB0_RESERVE77__RESERVE_MASK 0xFFFFFFFFL 2124 //DAGB0_RESERVE78 2125 #define DAGB0_RESERVE78__RESERVE__SHIFT 0x0 2126 #define DAGB0_RESERVE78__RESERVE_MASK 0xFFFFFFFFL 2127 //DAGB0_RESERVE79 2128 #define DAGB0_RESERVE79__RESERVE__SHIFT 0x0 2129 #define DAGB0_RESERVE79__RESERVE_MASK 0xFFFFFFFFL 2130 //DAGB0_RESERVE80 2131 #define DAGB0_RESERVE80__RESERVE__SHIFT 0x0 2132 #define DAGB0_RESERVE80__RESERVE_MASK 0xFFFFFFFFL 2133 //DAGB0_RESERVE81 2134 #define DAGB0_RESERVE81__RESERVE__SHIFT 0x0 2135 #define DAGB0_RESERVE81__RESERVE_MASK 0xFFFFFFFFL 2136 //DAGB0_RESERVE82 2137 #define DAGB0_RESERVE82__RESERVE__SHIFT 0x0 2138 #define DAGB0_RESERVE82__RESERVE_MASK 0xFFFFFFFFL 2139 //DAGB0_RESERVE83 2140 #define DAGB0_RESERVE83__RESERVE__SHIFT 0x0 2141 #define DAGB0_RESERVE83__RESERVE_MASK 0xFFFFFFFFL 2142 //DAGB0_RESERVE84 2143 #define DAGB0_RESERVE84__RESERVE__SHIFT 0x0 2144 #define DAGB0_RESERVE84__RESERVE_MASK 0xFFFFFFFFL 2145 //DAGB0_RESERVE85 2146 #define DAGB0_RESERVE85__RESERVE__SHIFT 0x0 2147 #define DAGB0_RESERVE85__RESERVE_MASK 0xFFFFFFFFL 2148 //DAGB0_RESERVE86 2149 #define DAGB0_RESERVE86__RESERVE__SHIFT 0x0 2150 #define DAGB0_RESERVE86__RESERVE_MASK 0xFFFFFFFFL 2151 //DAGB0_RESERVE87 2152 #define DAGB0_RESERVE87__RESERVE__SHIFT 0x0 2153 #define DAGB0_RESERVE87__RESERVE_MASK 0xFFFFFFFFL 2154 //DAGB0_RESERVE88 2155 #define DAGB0_RESERVE88__RESERVE__SHIFT 0x0 2156 #define DAGB0_RESERVE88__RESERVE_MASK 0xFFFFFFFFL 2157 //DAGB0_RESERVE89 2158 #define DAGB0_RESERVE89__RESERVE__SHIFT 0x0 2159 #define DAGB0_RESERVE89__RESERVE_MASK 0xFFFFFFFFL 2160 //DAGB0_RESERVE90 2161 #define DAGB0_RESERVE90__RESERVE__SHIFT 0x0 2162 #define DAGB0_RESERVE90__RESERVE_MASK 0xFFFFFFFFL 2163 //DAGB0_RESERVE91 2164 #define DAGB0_RESERVE91__RESERVE__SHIFT 0x0 2165 #define DAGB0_RESERVE91__RESERVE_MASK 0xFFFFFFFFL 2166 //DAGB0_RESERVE92 2167 #define DAGB0_RESERVE92__RESERVE__SHIFT 0x0 2168 #define DAGB0_RESERVE92__RESERVE_MASK 0xFFFFFFFFL 2169 //DAGB0_RESERVE93 2170 #define DAGB0_RESERVE93__RESERVE__SHIFT 0x0 2171 #define DAGB0_RESERVE93__RESERVE_MASK 0xFFFFFFFFL 2172 //DAGB0_RESERVE94 2173 #define DAGB0_RESERVE94__RESERVE__SHIFT 0x0 2174 #define DAGB0_RESERVE94__RESERVE_MASK 0xFFFFFFFFL 2175 //DAGB0_RESERVE95 2176 #define DAGB0_RESERVE95__RESERVE__SHIFT 0x0 2177 #define DAGB0_RESERVE95__RESERVE_MASK 0xFFFFFFFFL 2178 //DAGB0_RESERVE96 2179 #define DAGB0_RESERVE96__RESERVE__SHIFT 0x0 2180 #define DAGB0_RESERVE96__RESERVE_MASK 0xFFFFFFFFL 2181 //DAGB0_RESERVE97 2182 #define DAGB0_RESERVE97__RESERVE__SHIFT 0x0 2183 #define DAGB0_RESERVE97__RESERVE_MASK 0xFFFFFFFFL 2184 //DAGB0_RESERVE98 2185 #define DAGB0_RESERVE98__RESERVE__SHIFT 0x0 2186 #define DAGB0_RESERVE98__RESERVE_MASK 0xFFFFFFFFL 2187 //DAGB0_RESERVE99 2188 #define DAGB0_RESERVE99__RESERVE__SHIFT 0x0 2189 #define DAGB0_RESERVE99__RESERVE_MASK 0xFFFFFFFFL 2190 //DAGB0_RESERVE100 2191 #define DAGB0_RESERVE100__RESERVE__SHIFT 0x0 2192 #define DAGB0_RESERVE100__RESERVE_MASK 0xFFFFFFFFL 2193 //DAGB0_RESERVE101 2194 #define DAGB0_RESERVE101__RESERVE__SHIFT 0x0 2195 #define DAGB0_RESERVE101__RESERVE_MASK 0xFFFFFFFFL 2196 //DAGB0_RESERVE102 2197 #define DAGB0_RESERVE102__RESERVE__SHIFT 0x0 2198 #define DAGB0_RESERVE102__RESERVE_MASK 0xFFFFFFFFL 2199 //DAGB0_RESERVE103 2200 #define DAGB0_RESERVE103__RESERVE__SHIFT 0x0 2201 #define DAGB0_RESERVE103__RESERVE_MASK 0xFFFFFFFFL 2202 //DAGB0_RESERVE104 2203 #define DAGB0_RESERVE104__RESERVE__SHIFT 0x0 2204 #define DAGB0_RESERVE104__RESERVE_MASK 0xFFFFFFFFL 2205 //DAGB0_RESERVE105 2206 #define DAGB0_RESERVE105__RESERVE__SHIFT 0x0 2207 #define DAGB0_RESERVE105__RESERVE_MASK 0xFFFFFFFFL 2208 //DAGB0_RESERVE106 2209 #define DAGB0_RESERVE106__RESERVE__SHIFT 0x0 2210 #define DAGB0_RESERVE106__RESERVE_MASK 0xFFFFFFFFL 2211 //DAGB0_RESERVE107 2212 #define DAGB0_RESERVE107__RESERVE__SHIFT 0x0 2213 #define DAGB0_RESERVE107__RESERVE_MASK 0xFFFFFFFFL 2214 //DAGB0_RESERVE108 2215 #define DAGB0_RESERVE108__RESERVE__SHIFT 0x0 2216 #define DAGB0_RESERVE108__RESERVE_MASK 0xFFFFFFFFL 2217 //DAGB0_RESERVE109 2218 #define DAGB0_RESERVE109__RESERVE__SHIFT 0x0 2219 #define DAGB0_RESERVE109__RESERVE_MASK 0xFFFFFFFFL 2220 //DAGB0_RESERVE110 2221 #define DAGB0_RESERVE110__RESERVE__SHIFT 0x0 2222 #define DAGB0_RESERVE110__RESERVE_MASK 0xFFFFFFFFL 2223 //DAGB0_RESERVE111 2224 #define DAGB0_RESERVE111__RESERVE__SHIFT 0x0 2225 #define DAGB0_RESERVE111__RESERVE_MASK 0xFFFFFFFFL 2226 //DAGB0_RESERVE112 2227 #define DAGB0_RESERVE112__RESERVE__SHIFT 0x0 2228 #define DAGB0_RESERVE112__RESERVE_MASK 0xFFFFFFFFL 2229 //DAGB0_RESERVE113 2230 #define DAGB0_RESERVE113__RESERVE__SHIFT 0x0 2231 #define DAGB0_RESERVE113__RESERVE_MASK 0xFFFFFFFFL 2232 //DAGB0_RESERVE114 2233 #define DAGB0_RESERVE114__RESERVE__SHIFT 0x0 2234 #define DAGB0_RESERVE114__RESERVE_MASK 0xFFFFFFFFL 2235 //DAGB0_RESERVE115 2236 #define DAGB0_RESERVE115__RESERVE__SHIFT 0x0 2237 #define DAGB0_RESERVE115__RESERVE_MASK 0xFFFFFFFFL 2238 //DAGB0_RESERVE116 2239 #define DAGB0_RESERVE116__RESERVE__SHIFT 0x0 2240 #define DAGB0_RESERVE116__RESERVE_MASK 0xFFFFFFFFL 2241 //DAGB0_RESERVE117 2242 #define DAGB0_RESERVE117__RESERVE__SHIFT 0x0 2243 #define DAGB0_RESERVE117__RESERVE_MASK 0xFFFFFFFFL 2244 //DAGB0_RESERVE118 2245 #define DAGB0_RESERVE118__RESERVE__SHIFT 0x0 2246 #define DAGB0_RESERVE118__RESERVE_MASK 0xFFFFFFFFL 2247 //DAGB0_RESERVE119 2248 #define DAGB0_RESERVE119__RESERVE__SHIFT 0x0 2249 #define DAGB0_RESERVE119__RESERVE_MASK 0xFFFFFFFFL 2250 //DAGB0_RESERVE120 2251 #define DAGB0_RESERVE120__RESERVE__SHIFT 0x0 2252 #define DAGB0_RESERVE120__RESERVE_MASK 0xFFFFFFFFL 2253 //DAGB0_RESERVE121 2254 #define DAGB0_RESERVE121__RESERVE__SHIFT 0x0 2255 #define DAGB0_RESERVE121__RESERVE_MASK 0xFFFFFFFFL 2256 //DAGB0_RESERVE122 2257 #define DAGB0_RESERVE122__RESERVE__SHIFT 0x0 2258 #define DAGB0_RESERVE122__RESERVE_MASK 0xFFFFFFFFL 2259 //DAGB0_RESERVE123 2260 #define DAGB0_RESERVE123__RESERVE__SHIFT 0x0 2261 #define DAGB0_RESERVE123__RESERVE_MASK 0xFFFFFFFFL 2262 //DAGB0_RESERVE124 2263 #define DAGB0_RESERVE124__RESERVE__SHIFT 0x0 2264 #define DAGB0_RESERVE124__RESERVE_MASK 0xFFFFFFFFL 2265 //DAGB0_RESERVE125 2266 #define DAGB0_RESERVE125__RESERVE__SHIFT 0x0 2267 #define DAGB0_RESERVE125__RESERVE_MASK 0xFFFFFFFFL 2268 //DAGB0_RESERVE126 2269 #define DAGB0_RESERVE126__RESERVE__SHIFT 0x0 2270 #define DAGB0_RESERVE126__RESERVE_MASK 0xFFFFFFFFL 2271 //DAGB0_RESERVE127 2272 #define DAGB0_RESERVE127__RESERVE__SHIFT 0x0 2273 #define DAGB0_RESERVE127__RESERVE_MASK 0xFFFFFFFFL 2274 //DAGB0_RESERVE128 2275 #define DAGB0_RESERVE128__RESERVE__SHIFT 0x0 2276 #define DAGB0_RESERVE128__RESERVE_MASK 0xFFFFFFFFL 2277 //DAGB0_RESERVE129 2278 #define DAGB0_RESERVE129__RESERVE__SHIFT 0x0 2279 #define DAGB0_RESERVE129__RESERVE_MASK 0xFFFFFFFFL 2280 //DAGB0_RESERVE130 2281 #define DAGB0_RESERVE130__RESERVE__SHIFT 0x0 2282 #define DAGB0_RESERVE130__RESERVE_MASK 0xFFFFFFFFL 2283 //DAGB0_RESERVE131 2284 #define DAGB0_RESERVE131__RESERVE__SHIFT 0x0 2285 #define DAGB0_RESERVE131__RESERVE_MASK 0xFFFFFFFFL 2286 2287 2288 // addressBlock: mmhub_mmea_mmeadec 2289 //MMEA0_DRAM_RD_CLI2GRP_MAP0 2290 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 2291 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 2292 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 2293 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 2294 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 2295 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 2296 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 2297 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 2298 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 2299 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 2300 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 2301 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 2302 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 2303 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 2304 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 2305 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 2306 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 2307 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 2308 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 2309 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 2310 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 2311 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 2312 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 2313 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 2314 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 2315 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 2316 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 2317 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 2318 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 2319 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 2320 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 2321 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 2322 //MMEA0_DRAM_RD_CLI2GRP_MAP1 2323 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 2324 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 2325 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 2326 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 2327 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 2328 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 2329 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 2330 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 2331 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 2332 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 2333 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 2334 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 2335 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 2336 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 2337 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 2338 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 2339 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 2340 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 2341 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 2342 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 2343 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 2344 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 2345 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 2346 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 2347 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 2348 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 2349 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 2350 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 2351 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 2352 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 2353 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 2354 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 2355 //MMEA0_DRAM_WR_CLI2GRP_MAP0 2356 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 2357 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 2358 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 2359 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 2360 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 2361 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 2362 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 2363 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 2364 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 2365 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 2366 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 2367 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 2368 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 2369 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 2370 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 2371 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 2372 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 2373 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 2374 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 2375 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 2376 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 2377 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 2378 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 2379 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 2380 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 2381 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 2382 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 2383 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 2384 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 2385 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 2386 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 2387 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 2388 //MMEA0_DRAM_WR_CLI2GRP_MAP1 2389 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 2390 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 2391 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 2392 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 2393 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 2394 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 2395 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 2396 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 2397 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 2398 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 2399 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 2400 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 2401 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 2402 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 2403 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 2404 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 2405 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 2406 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 2407 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 2408 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 2409 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 2410 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 2411 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 2412 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 2413 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 2414 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 2415 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 2416 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 2417 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 2418 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 2419 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 2420 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 2421 //MMEA0_DRAM_RD_GRP2VC_MAP 2422 #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 2423 #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 2424 #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 2425 #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 2426 #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 2427 #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 2428 #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 2429 #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 2430 //MMEA0_DRAM_WR_GRP2VC_MAP 2431 #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 2432 #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 2433 #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 2434 #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 2435 #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 2436 #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 2437 #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 2438 #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 2439 //MMEA0_DRAM_RD_LAZY 2440 #define MMEA0_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 2441 #define MMEA0_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 2442 #define MMEA0_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 2443 #define MMEA0_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 2444 #define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 2445 #define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 2446 #define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b 2447 #define MMEA0_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L 2448 #define MMEA0_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L 2449 #define MMEA0_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L 2450 #define MMEA0_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L 2451 #define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 2452 #define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 2453 #define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L 2454 //MMEA0_DRAM_WR_LAZY 2455 #define MMEA0_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 2456 #define MMEA0_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 2457 #define MMEA0_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 2458 #define MMEA0_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 2459 #define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 2460 #define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 2461 #define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b 2462 #define MMEA0_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L 2463 #define MMEA0_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L 2464 #define MMEA0_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L 2465 #define MMEA0_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L 2466 #define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 2467 #define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 2468 #define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L 2469 //MMEA0_DRAM_RD_CAM_CNTL 2470 #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 2471 #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 2472 #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 2473 #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 2474 #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 2475 #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 2476 #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 2477 #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 2478 #define MMEA0_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c 2479 #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 2480 #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 2481 #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 2482 #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 2483 #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 2484 #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 2485 #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 2486 #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 2487 #define MMEA0_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L 2488 //MMEA0_DRAM_WR_CAM_CNTL 2489 #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 2490 #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 2491 #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 2492 #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 2493 #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 2494 #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 2495 #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 2496 #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 2497 #define MMEA0_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c 2498 #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 2499 #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 2500 #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 2501 #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 2502 #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 2503 #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 2504 #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 2505 #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 2506 #define MMEA0_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L 2507 //MMEA0_DRAM_PAGE_BURST 2508 #define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 2509 #define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 2510 #define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 2511 #define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 2512 #define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL 2513 #define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 2514 #define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 2515 #define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L 2516 //MMEA0_DRAM_RD_PRI_AGE 2517 #define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 2518 #define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 2519 #define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 2520 #define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 2521 #define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 2522 #define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 2523 #define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 2524 #define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 2525 #define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 2526 #define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 2527 #define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 2528 #define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 2529 #define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 2530 #define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 2531 #define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 2532 #define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 2533 //MMEA0_DRAM_WR_PRI_AGE 2534 #define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 2535 #define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 2536 #define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 2537 #define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 2538 #define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 2539 #define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 2540 #define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 2541 #define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 2542 #define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 2543 #define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 2544 #define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 2545 #define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 2546 #define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 2547 #define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 2548 #define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 2549 #define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 2550 //MMEA0_DRAM_RD_PRI_QUEUING 2551 #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 2552 #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 2553 #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 2554 #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 2555 #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 2556 #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 2557 #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 2558 #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 2559 //MMEA0_DRAM_WR_PRI_QUEUING 2560 #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 2561 #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 2562 #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 2563 #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 2564 #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 2565 #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 2566 #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 2567 #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 2568 //MMEA0_DRAM_RD_PRI_FIXED 2569 #define MMEA0_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 2570 #define MMEA0_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 2571 #define MMEA0_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 2572 #define MMEA0_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 2573 #define MMEA0_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 2574 #define MMEA0_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 2575 #define MMEA0_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 2576 #define MMEA0_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 2577 //MMEA0_DRAM_WR_PRI_FIXED 2578 #define MMEA0_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 2579 #define MMEA0_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 2580 #define MMEA0_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 2581 #define MMEA0_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 2582 #define MMEA0_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 2583 #define MMEA0_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 2584 #define MMEA0_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 2585 #define MMEA0_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 2586 //MMEA0_DRAM_RD_PRI_URGENCY 2587 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 2588 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 2589 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 2590 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 2591 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 2592 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 2593 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 2594 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 2595 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 2596 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 2597 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 2598 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 2599 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 2600 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 2601 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 2602 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 2603 //MMEA0_DRAM_WR_PRI_URGENCY 2604 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 2605 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 2606 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 2607 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 2608 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 2609 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 2610 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 2611 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 2612 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 2613 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 2614 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 2615 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 2616 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 2617 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 2618 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 2619 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 2620 //MMEA0_DRAM_RD_PRI_QUANT_PRI1 2621 #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 2622 #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 2623 #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 2624 #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 2625 #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 2626 #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 2627 #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 2628 #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 2629 //MMEA0_DRAM_RD_PRI_QUANT_PRI2 2630 #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 2631 #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 2632 #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 2633 #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 2634 #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 2635 #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 2636 #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 2637 #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 2638 //MMEA0_DRAM_RD_PRI_QUANT_PRI3 2639 #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 2640 #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 2641 #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 2642 #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 2643 #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 2644 #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 2645 #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 2646 #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 2647 //MMEA0_DRAM_WR_PRI_QUANT_PRI1 2648 #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 2649 #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 2650 #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 2651 #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 2652 #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 2653 #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 2654 #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 2655 #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 2656 //MMEA0_DRAM_WR_PRI_QUANT_PRI2 2657 #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 2658 #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 2659 #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 2660 #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 2661 #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 2662 #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 2663 #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 2664 #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 2665 //MMEA0_DRAM_WR_PRI_QUANT_PRI3 2666 #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 2667 #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 2668 #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 2669 #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 2670 #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 2671 #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 2672 #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 2673 #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 2674 //MMEA0_ADDRNORM_BASE_ADDR0 2675 #define MMEA0_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 2676 #define MMEA0_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 2677 #define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2 2678 #define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x6 2679 #define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 2680 #define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9 2681 #define MMEA0_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc 2682 #define MMEA0_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L 2683 #define MMEA0_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 2684 #define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000003CL 2685 #define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK 0x000000C0L 2686 #define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L 2687 #define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L 2688 #define MMEA0_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L 2689 //MMEA0_ADDRNORM_LIMIT_ADDR0 2690 #define MMEA0_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 2691 #define MMEA0_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc 2692 #define MMEA0_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL 2693 #define MMEA0_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L 2694 //MMEA0_ADDRNORM_BASE_ADDR1 2695 #define MMEA0_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 2696 #define MMEA0_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 2697 #define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2 2698 #define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x6 2699 #define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 2700 #define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9 2701 #define MMEA0_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc 2702 #define MMEA0_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L 2703 #define MMEA0_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 2704 #define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000003CL 2705 #define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK 0x000000C0L 2706 #define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L 2707 #define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L 2708 #define MMEA0_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L 2709 //MMEA0_ADDRNORM_LIMIT_ADDR1 2710 #define MMEA0_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 2711 #define MMEA0_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc 2712 #define MMEA0_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL 2713 #define MMEA0_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L 2714 //MMEA0_ADDRNORM_OFFSET_ADDR1 2715 #define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0 2716 #define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0x14 2717 #define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L 2718 #define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0xFFF00000L 2719 //MMEA0_ADDRNORMDRAM_HOLE_CNTL 2720 #define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 2721 #define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 2722 #define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L 2723 #define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L 2724 //MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG 2725 #define MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT 0x0 2726 #define MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT 0x6 2727 #define MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK 0x0000003FL 2728 #define MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK 0x00000FC0L 2729 //MMEA0_ADDRDEC_BANK_CFG 2730 #define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0 2731 #define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x5 2732 #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xa 2733 #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xd 2734 #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x10 2735 #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x11 2736 #define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000001FL 2737 #define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x000003E0L 2738 #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00001C00L 2739 #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x0000E000L 2740 #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00010000L 2741 #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00020000L 2742 //MMEA0_ADDRDEC_MISC_CFG 2743 #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0 2744 #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1 2745 #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2 2746 #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN3__SHIFT 0x3 2747 #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN4__SHIFT 0x4 2748 #define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8 2749 #define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9 2750 #define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc 2751 #define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x11 2752 #define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x16 2753 #define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x18 2754 #define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x1a 2755 #define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1d 2756 #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L 2757 #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L 2758 #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L 2759 #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN3_MASK 0x00000008L 2760 #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN4_MASK 0x00000010L 2761 #define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L 2762 #define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L 2763 #define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0001F000L 2764 #define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x003E0000L 2765 #define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00C00000L 2766 #define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x03000000L 2767 #define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x1C000000L 2768 #define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0xE0000000L 2769 //MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0 2770 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0 2771 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1 2772 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe 2773 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L 2774 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL 2775 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L 2776 //MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1 2777 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0 2778 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1 2779 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe 2780 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L 2781 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL 2782 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L 2783 //MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2 2784 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0 2785 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1 2786 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe 2787 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L 2788 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL 2789 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L 2790 //MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3 2791 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0 2792 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1 2793 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe 2794 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L 2795 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL 2796 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L 2797 //MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4 2798 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0 2799 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1 2800 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe 2801 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L 2802 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL 2803 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L 2804 //MMEA0_ADDRDECDRAM_ADDR_HASH_PC 2805 #define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0 2806 #define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT 0x1 2807 #define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe 2808 #define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L 2809 #define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL 2810 #define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L 2811 //MMEA0_ADDRDECDRAM_ADDR_HASH_PC2 2812 #define MMEA0_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0 2813 #define MMEA0_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000001FL 2814 //MMEA0_ADDRDECDRAM_ADDR_HASH_CS0 2815 #define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0 2816 #define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1 2817 #define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L 2818 #define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL 2819 //MMEA0_ADDRDECDRAM_ADDR_HASH_CS1 2820 #define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0 2821 #define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1 2822 #define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L 2823 #define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL 2824 //MMEA0_ADDRDECDRAM_HARVEST_ENABLE 2825 #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 2826 #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 2827 #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 2828 #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 2829 #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L 2830 #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L 2831 #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L 2832 #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L 2833 //MMEA0_ADDRDECDRAM_HARVNA_ADDR_START0 2834 #define MMEA0_ADDRDECDRAM_HARVNA_ADDR_START0__START__SHIFT 0x0 2835 #define MMEA0_ADDRDECDRAM_HARVNA_ADDR_START0__BANK_XOR__SHIFT 0x1c 2836 #define MMEA0_ADDRDECDRAM_HARVNA_ADDR_START0__START_MASK 0x000FFFFFL 2837 #define MMEA0_ADDRDECDRAM_HARVNA_ADDR_START0__BANK_XOR_MASK 0xF0000000L 2838 //MMEA0_ADDRDECDRAM_HARVNA_ADDR_END0 2839 #define MMEA0_ADDRDECDRAM_HARVNA_ADDR_END0__END__SHIFT 0x0 2840 #define MMEA0_ADDRDECDRAM_HARVNA_ADDR_END0__END_MASK 0x000FFFFFL 2841 //MMEA0_ADDRDECDRAM_HARVNA_ADDR_START1 2842 #define MMEA0_ADDRDECDRAM_HARVNA_ADDR_START1__START__SHIFT 0x0 2843 #define MMEA0_ADDRDECDRAM_HARVNA_ADDR_START1__BANK_XOR__SHIFT 0x1c 2844 #define MMEA0_ADDRDECDRAM_HARVNA_ADDR_START1__START_MASK 0x000FFFFFL 2845 #define MMEA0_ADDRDECDRAM_HARVNA_ADDR_START1__BANK_XOR_MASK 0xF0000000L 2846 //MMEA0_ADDRDECDRAM_HARVNA_ADDR_END1 2847 #define MMEA0_ADDRDECDRAM_HARVNA_ADDR_END1__END__SHIFT 0x0 2848 #define MMEA0_ADDRDECDRAM_HARVNA_ADDR_END1__END_MASK 0x000FFFFFL 2849 //MMEA0_ADDRDEC0_BASE_ADDR_CS0 2850 #define MMEA0_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 2851 #define MMEA0_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 2852 #define MMEA0_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L 2853 #define MMEA0_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 2854 //MMEA0_ADDRDEC0_BASE_ADDR_CS1 2855 #define MMEA0_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 2856 #define MMEA0_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 2857 #define MMEA0_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L 2858 #define MMEA0_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 2859 //MMEA0_ADDRDEC0_BASE_ADDR_CS2 2860 #define MMEA0_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 2861 #define MMEA0_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 2862 #define MMEA0_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L 2863 #define MMEA0_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 2864 //MMEA0_ADDRDEC0_BASE_ADDR_CS3 2865 #define MMEA0_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 2866 #define MMEA0_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 2867 #define MMEA0_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L 2868 #define MMEA0_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 2869 //MMEA0_ADDRDEC0_BASE_ADDR_SECCS0 2870 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 2871 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 2872 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L 2873 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 2874 //MMEA0_ADDRDEC0_BASE_ADDR_SECCS1 2875 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 2876 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 2877 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L 2878 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 2879 //MMEA0_ADDRDEC0_BASE_ADDR_SECCS2 2880 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 2881 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 2882 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L 2883 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 2884 //MMEA0_ADDRDEC0_BASE_ADDR_SECCS3 2885 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 2886 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 2887 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L 2888 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 2889 //MMEA0_ADDRDEC0_ADDR_MASK_CS01 2890 #define MMEA0_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 2891 #define MMEA0_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 2892 //MMEA0_ADDRDEC0_ADDR_MASK_CS23 2893 #define MMEA0_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 2894 #define MMEA0_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 2895 //MMEA0_ADDRDEC0_ADDR_MASK_SECCS01 2896 #define MMEA0_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 2897 #define MMEA0_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 2898 //MMEA0_ADDRDEC0_ADDR_MASK_SECCS23 2899 #define MMEA0_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 2900 #define MMEA0_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 2901 //MMEA0_ADDRDEC0_ADDR_CFG_CS01 2902 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2 2903 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 2904 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 2905 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 2906 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 2907 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 2908 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f 2909 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL 2910 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 2911 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 2912 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 2913 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 2914 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 2915 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L 2916 //MMEA0_ADDRDEC0_ADDR_CFG_CS23 2917 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2 2918 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 2919 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 2920 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 2921 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 2922 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 2923 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f 2924 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL 2925 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 2926 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 2927 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 2928 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 2929 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 2930 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L 2931 //MMEA0_ADDRDEC0_ADDR_SEL_CS01 2932 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0 2933 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4 2934 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8 2935 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc 2936 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10 2937 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 2938 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 2939 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 2940 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 2941 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 2942 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 2943 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L 2944 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 2945 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 2946 //MMEA0_ADDRDEC0_ADDR_SEL_CS23 2947 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0 2948 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4 2949 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8 2950 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc 2951 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10 2952 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 2953 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 2954 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 2955 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 2956 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 2957 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 2958 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L 2959 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 2960 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 2961 //MMEA0_ADDRDEC0_COL_SEL_LO_CS01 2962 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0 2963 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4 2964 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8 2965 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc 2966 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10 2967 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14 2968 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18 2969 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 2970 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 2971 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 2972 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 2973 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 2974 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 2975 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 2976 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 2977 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 2978 //MMEA0_ADDRDEC0_COL_SEL_LO_CS23 2979 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0 2980 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4 2981 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8 2982 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc 2983 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10 2984 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14 2985 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18 2986 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 2987 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 2988 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 2989 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 2990 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 2991 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 2992 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 2993 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 2994 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 2995 //MMEA0_ADDRDEC0_COL_SEL_HI_CS01 2996 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0 2997 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4 2998 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8 2999 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc 3000 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10 3001 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14 3002 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18 3003 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 3004 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 3005 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 3006 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 3007 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 3008 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 3009 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 3010 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 3011 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 3012 //MMEA0_ADDRDEC0_COL_SEL_HI_CS23 3013 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0 3014 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4 3015 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8 3016 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc 3017 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10 3018 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14 3019 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18 3020 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 3021 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 3022 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 3023 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 3024 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 3025 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 3026 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 3027 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 3028 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 3029 //MMEA0_ADDRDEC0_RM_SEL_CS01 3030 #define MMEA0_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0 3031 #define MMEA0_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4 3032 #define MMEA0_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8 3033 #define MMEA0_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc 3034 #define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 3035 #define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 3036 #define MMEA0_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL 3037 #define MMEA0_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L 3038 #define MMEA0_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L 3039 #define MMEA0_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L 3040 #define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 3041 #define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 3042 //MMEA0_ADDRDEC0_RM_SEL_CS23 3043 #define MMEA0_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0 3044 #define MMEA0_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4 3045 #define MMEA0_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8 3046 #define MMEA0_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc 3047 #define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 3048 #define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 3049 #define MMEA0_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL 3050 #define MMEA0_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L 3051 #define MMEA0_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L 3052 #define MMEA0_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L 3053 #define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 3054 #define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 3055 //MMEA0_ADDRDEC0_RM_SEL_SECCS01 3056 #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0 3057 #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4 3058 #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8 3059 #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc 3060 #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 3061 #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 3062 #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL 3063 #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L 3064 #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L 3065 #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L 3066 #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 3067 #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 3068 //MMEA0_ADDRDEC0_RM_SEL_SECCS23 3069 #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0 3070 #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4 3071 #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8 3072 #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc 3073 #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 3074 #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 3075 #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL 3076 #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L 3077 #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L 3078 #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L 3079 #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 3080 #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 3081 //MMEA0_ADDRDEC1_BASE_ADDR_CS0 3082 #define MMEA0_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 3083 #define MMEA0_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 3084 #define MMEA0_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L 3085 #define MMEA0_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 3086 //MMEA0_ADDRDEC1_BASE_ADDR_CS1 3087 #define MMEA0_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 3088 #define MMEA0_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 3089 #define MMEA0_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L 3090 #define MMEA0_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 3091 //MMEA0_ADDRDEC1_BASE_ADDR_CS2 3092 #define MMEA0_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 3093 #define MMEA0_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 3094 #define MMEA0_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L 3095 #define MMEA0_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 3096 //MMEA0_ADDRDEC1_BASE_ADDR_CS3 3097 #define MMEA0_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 3098 #define MMEA0_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 3099 #define MMEA0_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L 3100 #define MMEA0_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 3101 //MMEA0_ADDRDEC1_BASE_ADDR_SECCS0 3102 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 3103 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 3104 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L 3105 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 3106 //MMEA0_ADDRDEC1_BASE_ADDR_SECCS1 3107 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 3108 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 3109 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L 3110 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 3111 //MMEA0_ADDRDEC1_BASE_ADDR_SECCS2 3112 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 3113 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 3114 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L 3115 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 3116 //MMEA0_ADDRDEC1_BASE_ADDR_SECCS3 3117 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 3118 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 3119 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L 3120 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 3121 //MMEA0_ADDRDEC1_ADDR_MASK_CS01 3122 #define MMEA0_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 3123 #define MMEA0_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 3124 //MMEA0_ADDRDEC1_ADDR_MASK_CS23 3125 #define MMEA0_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 3126 #define MMEA0_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 3127 //MMEA0_ADDRDEC1_ADDR_MASK_SECCS01 3128 #define MMEA0_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 3129 #define MMEA0_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 3130 //MMEA0_ADDRDEC1_ADDR_MASK_SECCS23 3131 #define MMEA0_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 3132 #define MMEA0_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 3133 //MMEA0_ADDRDEC1_ADDR_CFG_CS01 3134 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2 3135 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 3136 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 3137 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 3138 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 3139 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 3140 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f 3141 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL 3142 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 3143 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 3144 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 3145 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 3146 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 3147 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L 3148 //MMEA0_ADDRDEC1_ADDR_CFG_CS23 3149 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2 3150 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 3151 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 3152 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 3153 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 3154 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 3155 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f 3156 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL 3157 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 3158 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 3159 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 3160 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 3161 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 3162 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L 3163 //MMEA0_ADDRDEC1_ADDR_SEL_CS01 3164 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0 3165 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4 3166 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8 3167 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc 3168 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10 3169 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 3170 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 3171 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 3172 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 3173 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 3174 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 3175 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L 3176 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 3177 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 3178 //MMEA0_ADDRDEC1_ADDR_SEL_CS23 3179 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0 3180 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4 3181 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8 3182 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc 3183 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10 3184 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 3185 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 3186 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 3187 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 3188 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 3189 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 3190 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L 3191 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 3192 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 3193 //MMEA0_ADDRDEC1_COL_SEL_LO_CS01 3194 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0 3195 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4 3196 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8 3197 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc 3198 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10 3199 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14 3200 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18 3201 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 3202 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 3203 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 3204 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 3205 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 3206 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 3207 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 3208 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 3209 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 3210 //MMEA0_ADDRDEC1_COL_SEL_LO_CS23 3211 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0 3212 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4 3213 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8 3214 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc 3215 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10 3216 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14 3217 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18 3218 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 3219 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 3220 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 3221 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 3222 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 3223 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 3224 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 3225 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 3226 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 3227 //MMEA0_ADDRDEC1_COL_SEL_HI_CS01 3228 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0 3229 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4 3230 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8 3231 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc 3232 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10 3233 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14 3234 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18 3235 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 3236 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 3237 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 3238 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 3239 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 3240 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 3241 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 3242 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 3243 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 3244 //MMEA0_ADDRDEC1_COL_SEL_HI_CS23 3245 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0 3246 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4 3247 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8 3248 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc 3249 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10 3250 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14 3251 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18 3252 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 3253 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 3254 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 3255 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 3256 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 3257 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 3258 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 3259 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 3260 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 3261 //MMEA0_ADDRDEC1_RM_SEL_CS01 3262 #define MMEA0_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0 3263 #define MMEA0_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4 3264 #define MMEA0_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8 3265 #define MMEA0_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc 3266 #define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 3267 #define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 3268 #define MMEA0_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL 3269 #define MMEA0_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L 3270 #define MMEA0_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L 3271 #define MMEA0_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L 3272 #define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 3273 #define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 3274 //MMEA0_ADDRDEC1_RM_SEL_CS23 3275 #define MMEA0_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0 3276 #define MMEA0_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4 3277 #define MMEA0_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8 3278 #define MMEA0_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc 3279 #define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 3280 #define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 3281 #define MMEA0_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL 3282 #define MMEA0_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L 3283 #define MMEA0_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L 3284 #define MMEA0_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L 3285 #define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 3286 #define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 3287 //MMEA0_ADDRDEC1_RM_SEL_SECCS01 3288 #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0 3289 #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4 3290 #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8 3291 #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc 3292 #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 3293 #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 3294 #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL 3295 #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L 3296 #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L 3297 #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L 3298 #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 3299 #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 3300 //MMEA0_ADDRDEC1_RM_SEL_SECCS23 3301 #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0 3302 #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4 3303 #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8 3304 #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc 3305 #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 3306 #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 3307 #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL 3308 #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L 3309 #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L 3310 #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L 3311 #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 3312 #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 3313 //MMEA0_IO_RD_CLI2GRP_MAP0 3314 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 3315 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 3316 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 3317 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 3318 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 3319 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 3320 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 3321 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 3322 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 3323 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 3324 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 3325 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 3326 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 3327 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 3328 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 3329 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 3330 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 3331 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 3332 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 3333 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 3334 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 3335 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 3336 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 3337 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 3338 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 3339 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 3340 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 3341 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 3342 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 3343 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 3344 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 3345 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 3346 //MMEA0_IO_RD_CLI2GRP_MAP1 3347 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 3348 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 3349 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 3350 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 3351 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 3352 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 3353 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 3354 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 3355 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 3356 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 3357 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 3358 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 3359 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 3360 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 3361 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 3362 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 3363 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 3364 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 3365 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 3366 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 3367 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 3368 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 3369 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 3370 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 3371 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 3372 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 3373 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 3374 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 3375 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 3376 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 3377 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 3378 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 3379 //MMEA0_IO_WR_CLI2GRP_MAP0 3380 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 3381 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 3382 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 3383 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 3384 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 3385 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 3386 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 3387 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 3388 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 3389 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 3390 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 3391 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 3392 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 3393 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 3394 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 3395 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 3396 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 3397 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 3398 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 3399 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 3400 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 3401 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 3402 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 3403 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 3404 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 3405 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 3406 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 3407 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 3408 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 3409 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 3410 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 3411 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 3412 //MMEA0_IO_WR_CLI2GRP_MAP1 3413 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 3414 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 3415 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 3416 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 3417 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 3418 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 3419 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 3420 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 3421 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 3422 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 3423 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 3424 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 3425 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 3426 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 3427 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 3428 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 3429 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 3430 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 3431 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 3432 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 3433 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 3434 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 3435 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 3436 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 3437 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 3438 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 3439 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 3440 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 3441 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 3442 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 3443 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 3444 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 3445 //MMEA0_IO_RD_COMBINE_FLUSH 3446 #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 3447 #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 3448 #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 3449 #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc 3450 #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL 3451 #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L 3452 #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L 3453 #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L 3454 //MMEA0_IO_WR_COMBINE_FLUSH 3455 #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 3456 #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 3457 #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 3458 #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc 3459 #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL 3460 #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L 3461 #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L 3462 #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L 3463 //MMEA0_IO_GROUP_BURST 3464 #define MMEA0_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 3465 #define MMEA0_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 3466 #define MMEA0_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 3467 #define MMEA0_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 3468 #define MMEA0_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL 3469 #define MMEA0_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 3470 #define MMEA0_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 3471 #define MMEA0_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L 3472 //MMEA0_IO_RD_PRI_AGE 3473 #define MMEA0_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 3474 #define MMEA0_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 3475 #define MMEA0_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 3476 #define MMEA0_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 3477 #define MMEA0_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 3478 #define MMEA0_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 3479 #define MMEA0_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 3480 #define MMEA0_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 3481 #define MMEA0_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 3482 #define MMEA0_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 3483 #define MMEA0_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 3484 #define MMEA0_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 3485 #define MMEA0_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 3486 #define MMEA0_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 3487 #define MMEA0_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 3488 #define MMEA0_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 3489 //MMEA0_IO_WR_PRI_AGE 3490 #define MMEA0_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 3491 #define MMEA0_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 3492 #define MMEA0_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 3493 #define MMEA0_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 3494 #define MMEA0_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 3495 #define MMEA0_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 3496 #define MMEA0_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 3497 #define MMEA0_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 3498 #define MMEA0_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 3499 #define MMEA0_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 3500 #define MMEA0_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 3501 #define MMEA0_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 3502 #define MMEA0_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 3503 #define MMEA0_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 3504 #define MMEA0_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 3505 #define MMEA0_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 3506 //MMEA0_IO_RD_PRI_QUEUING 3507 #define MMEA0_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 3508 #define MMEA0_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 3509 #define MMEA0_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 3510 #define MMEA0_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 3511 #define MMEA0_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 3512 #define MMEA0_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 3513 #define MMEA0_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 3514 #define MMEA0_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 3515 //MMEA0_IO_WR_PRI_QUEUING 3516 #define MMEA0_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 3517 #define MMEA0_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 3518 #define MMEA0_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 3519 #define MMEA0_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 3520 #define MMEA0_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 3521 #define MMEA0_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 3522 #define MMEA0_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 3523 #define MMEA0_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 3524 //MMEA0_IO_RD_PRI_FIXED 3525 #define MMEA0_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 3526 #define MMEA0_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 3527 #define MMEA0_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 3528 #define MMEA0_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 3529 #define MMEA0_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 3530 #define MMEA0_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 3531 #define MMEA0_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 3532 #define MMEA0_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 3533 //MMEA0_IO_WR_PRI_FIXED 3534 #define MMEA0_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 3535 #define MMEA0_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 3536 #define MMEA0_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 3537 #define MMEA0_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 3538 #define MMEA0_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 3539 #define MMEA0_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 3540 #define MMEA0_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 3541 #define MMEA0_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 3542 //MMEA0_IO_RD_PRI_URGENCY 3543 #define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 3544 #define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 3545 #define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 3546 #define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 3547 #define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 3548 #define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 3549 #define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 3550 #define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 3551 #define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 3552 #define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 3553 #define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 3554 #define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 3555 #define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 3556 #define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 3557 #define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 3558 #define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 3559 //MMEA0_IO_WR_PRI_URGENCY 3560 #define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 3561 #define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 3562 #define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 3563 #define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 3564 #define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 3565 #define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 3566 #define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 3567 #define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 3568 #define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 3569 #define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 3570 #define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 3571 #define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 3572 #define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 3573 #define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 3574 #define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 3575 #define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 3576 //MMEA0_IO_RD_PRI_URGENCY_MASKING 3577 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 3578 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 3579 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 3580 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 3581 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 3582 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 3583 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 3584 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 3585 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 3586 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 3587 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa 3588 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb 3589 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc 3590 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd 3591 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe 3592 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf 3593 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 3594 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 3595 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 3596 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 3597 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 3598 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 3599 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 3600 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 3601 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 3602 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 3603 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a 3604 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b 3605 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c 3606 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d 3607 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e 3608 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f 3609 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L 3610 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L 3611 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L 3612 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L 3613 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L 3614 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L 3615 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L 3616 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L 3617 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L 3618 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L 3619 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L 3620 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L 3621 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L 3622 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L 3623 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L 3624 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L 3625 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L 3626 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L 3627 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L 3628 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L 3629 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L 3630 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L 3631 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L 3632 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L 3633 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L 3634 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L 3635 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L 3636 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L 3637 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L 3638 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L 3639 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L 3640 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L 3641 //MMEA0_IO_WR_PRI_URGENCY_MASKING 3642 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 3643 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 3644 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 3645 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 3646 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 3647 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 3648 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 3649 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 3650 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 3651 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 3652 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa 3653 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb 3654 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc 3655 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd 3656 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe 3657 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf 3658 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 3659 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 3660 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 3661 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 3662 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 3663 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 3664 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 3665 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 3666 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 3667 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 3668 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a 3669 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b 3670 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c 3671 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d 3672 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e 3673 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f 3674 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L 3675 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L 3676 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L 3677 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L 3678 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L 3679 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L 3680 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L 3681 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L 3682 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L 3683 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L 3684 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L 3685 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L 3686 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L 3687 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L 3688 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L 3689 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L 3690 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L 3691 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L 3692 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L 3693 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L 3694 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L 3695 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L 3696 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L 3697 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L 3698 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L 3699 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L 3700 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L 3701 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L 3702 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L 3703 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L 3704 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L 3705 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L 3706 //MMEA0_IO_RD_PRI_QUANT_PRI1 3707 #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 3708 #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 3709 #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 3710 #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 3711 #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 3712 #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 3713 #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 3714 #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 3715 //MMEA0_IO_RD_PRI_QUANT_PRI2 3716 #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 3717 #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 3718 #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 3719 #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 3720 #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 3721 #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 3722 #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 3723 #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 3724 //MMEA0_IO_RD_PRI_QUANT_PRI3 3725 #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 3726 #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 3727 #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 3728 #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 3729 #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 3730 #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 3731 #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 3732 #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 3733 //MMEA0_IO_WR_PRI_QUANT_PRI1 3734 #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 3735 #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 3736 #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 3737 #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 3738 #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 3739 #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 3740 #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 3741 #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 3742 //MMEA0_IO_WR_PRI_QUANT_PRI2 3743 #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 3744 #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 3745 #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 3746 #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 3747 #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 3748 #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 3749 #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 3750 #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 3751 //MMEA0_IO_WR_PRI_QUANT_PRI3 3752 #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 3753 #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 3754 #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 3755 #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 3756 #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 3757 #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 3758 #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 3759 #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 3760 //MMEA0_SDP_ARB_DRAM 3761 #define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 3762 #define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 3763 #define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10 3764 #define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11 3765 #define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12 3766 #define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13 3767 #define MMEA0_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14 3768 #define MMEA0_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 3769 #define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL 3770 #define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L 3771 #define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L 3772 #define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L 3773 #define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L 3774 #define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L 3775 #define MMEA0_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L 3776 #define MMEA0_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L 3777 //MMEA0_SDP_ARB_FINAL 3778 #define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 3779 #define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 3780 #define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa 3781 #define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf 3782 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 3783 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 3784 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 3785 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 3786 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 3787 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 3788 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 3789 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 3790 #define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 3791 #define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a 3792 #define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL 3793 #define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L 3794 #define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L 3795 #define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L 3796 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L 3797 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L 3798 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L 3799 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L 3800 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L 3801 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L 3802 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L 3803 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L 3804 #define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L 3805 #define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L 3806 //MMEA0_SDP_DRAM_PRIORITY 3807 #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 3808 #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 3809 #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 3810 #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 3811 #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 3812 #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 3813 #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 3814 #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 3815 #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 3816 #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 3817 #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 3818 #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 3819 #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 3820 #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 3821 #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 3822 #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 3823 //MMEA0_SDP_IO_PRIORITY 3824 #define MMEA0_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 3825 #define MMEA0_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 3826 #define MMEA0_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 3827 #define MMEA0_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 3828 #define MMEA0_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 3829 #define MMEA0_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 3830 #define MMEA0_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 3831 #define MMEA0_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 3832 #define MMEA0_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 3833 #define MMEA0_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 3834 #define MMEA0_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 3835 #define MMEA0_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 3836 #define MMEA0_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 3837 #define MMEA0_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 3838 #define MMEA0_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 3839 #define MMEA0_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 3840 //MMEA0_SDP_CREDITS 3841 #define MMEA0_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 3842 #define MMEA0_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 3843 #define MMEA0_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 3844 #define MMEA0_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL 3845 #define MMEA0_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L 3846 #define MMEA0_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L 3847 //MMEA0_SDP_TAG_RESERVE0 3848 #define MMEA0_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 3849 #define MMEA0_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 3850 #define MMEA0_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 3851 #define MMEA0_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 3852 #define MMEA0_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL 3853 #define MMEA0_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L 3854 #define MMEA0_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L 3855 #define MMEA0_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L 3856 //MMEA0_SDP_TAG_RESERVE1 3857 #define MMEA0_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 3858 #define MMEA0_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 3859 #define MMEA0_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 3860 #define MMEA0_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 3861 #define MMEA0_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL 3862 #define MMEA0_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L 3863 #define MMEA0_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L 3864 #define MMEA0_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L 3865 //MMEA0_SDP_VCC_RESERVE0 3866 #define MMEA0_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 3867 #define MMEA0_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 3868 #define MMEA0_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc 3869 #define MMEA0_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 3870 #define MMEA0_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 3871 #define MMEA0_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL 3872 #define MMEA0_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L 3873 #define MMEA0_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L 3874 #define MMEA0_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L 3875 #define MMEA0_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L 3876 //MMEA0_SDP_VCC_RESERVE1 3877 #define MMEA0_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 3878 #define MMEA0_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 3879 #define MMEA0_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc 3880 #define MMEA0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f 3881 #define MMEA0_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL 3882 #define MMEA0_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L 3883 #define MMEA0_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L 3884 #define MMEA0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L 3885 //MMEA0_SDP_VCD_RESERVE0 3886 #define MMEA0_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 3887 #define MMEA0_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 3888 #define MMEA0_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc 3889 #define MMEA0_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 3890 #define MMEA0_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 3891 #define MMEA0_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL 3892 #define MMEA0_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L 3893 #define MMEA0_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L 3894 #define MMEA0_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L 3895 #define MMEA0_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L 3896 //MMEA0_SDP_VCD_RESERVE1 3897 #define MMEA0_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 3898 #define MMEA0_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 3899 #define MMEA0_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc 3900 #define MMEA0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f 3901 #define MMEA0_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL 3902 #define MMEA0_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L 3903 #define MMEA0_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L 3904 #define MMEA0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L 3905 //MMEA0_SDP_REQ_CNTL 3906 #define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 3907 #define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 3908 #define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 3909 #define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 3910 #define MMEA0_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x4 3911 #define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L 3912 #define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L 3913 #define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L 3914 #define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L 3915 #define MMEA0_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000010L 3916 //MMEA0_MISC 3917 #define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0 3918 #define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1 3919 #define MMEA0_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2 3920 #define MMEA0_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3 3921 #define MMEA0_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4 3922 #define MMEA0_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5 3923 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x6 3924 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x7 3925 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x8 3926 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x9 3927 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa 3928 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0xb 3929 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0xc 3930 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0xd 3931 #define MMEA0_MISC__EARLY_SDP_ORIGDATA__SHIFT 0xe 3932 #define MMEA0_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0xf 3933 #define MMEA0_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x11 3934 #define MMEA0_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x13 3935 #define MMEA0_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0x15 3936 #define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x1a 3937 #define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x1b 3938 #define MMEA0_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x1c 3939 #define MMEA0_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x1d 3940 #define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x1e 3941 #define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x1f 3942 #define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L 3943 #define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L 3944 #define MMEA0_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L 3945 #define MMEA0_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L 3946 #define MMEA0_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L 3947 #define MMEA0_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L 3948 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000040L 3949 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000080L 3950 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000100L 3951 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000200L 3952 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000400L 3953 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000800L 3954 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00001000L 3955 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00002000L 3956 #define MMEA0_MISC__EARLY_SDP_ORIGDATA_MASK 0x00004000L 3957 #define MMEA0_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00018000L 3958 #define MMEA0_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00060000L 3959 #define MMEA0_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00180000L 3960 #define MMEA0_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x03E00000L 3961 #define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x04000000L 3962 #define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x08000000L 3963 #define MMEA0_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x10000000L 3964 #define MMEA0_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x20000000L 3965 #define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x40000000L 3966 #define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x80000000L 3967 //MMEA0_LATENCY_SAMPLING 3968 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 3969 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 3970 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 3971 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 3972 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 3973 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 3974 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 3975 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 3976 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 3977 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 3978 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa 3979 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb 3980 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc 3981 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd 3982 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe 3983 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 3984 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L 3985 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L 3986 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L 3987 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L 3988 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L 3989 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L 3990 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L 3991 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L 3992 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L 3993 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L 3994 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L 3995 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L 3996 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L 3997 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L 3998 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L 3999 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L 4000 //MMEA0_PERFCOUNTER_LO 4001 #define MMEA0_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 4002 #define MMEA0_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 4003 //MMEA0_PERFCOUNTER_HI 4004 #define MMEA0_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 4005 #define MMEA0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 4006 #define MMEA0_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 4007 #define MMEA0_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 4008 //MMEA0_PERFCOUNTER0_CFG 4009 #define MMEA0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 4010 #define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 4011 #define MMEA0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 4012 #define MMEA0_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 4013 #define MMEA0_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 4014 #define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 4015 #define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 4016 #define MMEA0_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 4017 #define MMEA0_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 4018 #define MMEA0_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 4019 //MMEA0_PERFCOUNTER1_CFG 4020 #define MMEA0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 4021 #define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 4022 #define MMEA0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 4023 #define MMEA0_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 4024 #define MMEA0_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 4025 #define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 4026 #define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 4027 #define MMEA0_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 4028 #define MMEA0_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 4029 #define MMEA0_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 4030 //MMEA0_PERFCOUNTER_RSLT_CNTL 4031 #define MMEA0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 4032 #define MMEA0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 4033 #define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 4034 #define MMEA0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 4035 #define MMEA0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 4036 #define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 4037 #define MMEA0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 4038 #define MMEA0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 4039 #define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 4040 #define MMEA0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 4041 #define MMEA0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 4042 #define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 4043 //MMEA0_EDC_CNT 4044 #define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 4045 #define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 4046 #define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 4047 #define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 4048 #define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 4049 #define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa 4050 #define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc 4051 #define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe 4052 #define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 4053 #define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 4054 #define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14 4055 #define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16 4056 #define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18 4057 #define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a 4058 #define MMEA0_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c 4059 #define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 4060 #define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 4061 #define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 4062 #define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 4063 #define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 4064 #define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 4065 #define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L 4066 #define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L 4067 #define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L 4068 #define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L 4069 #define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L 4070 #define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L 4071 #define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L 4072 #define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L 4073 #define MMEA0_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L 4074 //MMEA0_EDC_CNT2 4075 #define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 4076 #define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 4077 #define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 4078 #define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 4079 #define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 4080 #define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa 4081 #define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc 4082 #define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe 4083 #define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 4084 #define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 4085 #define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 4086 #define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 4087 #define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 4088 #define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 4089 #define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L 4090 #define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L 4091 //MMEA0_DSM_CNTL 4092 #define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 4093 #define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 4094 #define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 4095 #define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 4096 #define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 4097 #define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 4098 #define MMEA0_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 4099 #define MMEA0_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb 4100 #define MMEA0_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc 4101 #define MMEA0_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe 4102 #define MMEA0_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf 4103 #define MMEA0_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 4104 #define MMEA0_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 4105 #define MMEA0_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 4106 #define MMEA0_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15 4107 #define MMEA0_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 4108 #define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L 4109 #define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L 4110 #define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L 4111 #define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L 4112 #define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L 4113 #define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L 4114 #define MMEA0_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L 4115 #define MMEA0_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L 4116 #define MMEA0_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L 4117 #define MMEA0_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L 4118 #define MMEA0_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L 4119 #define MMEA0_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L 4120 #define MMEA0_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L 4121 #define MMEA0_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L 4122 #define MMEA0_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L 4123 #define MMEA0_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L 4124 //MMEA0_DSM_CNTLA 4125 #define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 4126 #define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 4127 #define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 4128 #define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 4129 #define MMEA0_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 4130 #define MMEA0_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 4131 #define MMEA0_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 4132 #define MMEA0_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb 4133 #define MMEA0_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc 4134 #define MMEA0_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe 4135 #define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf 4136 #define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 4137 #define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 4138 #define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 4139 #define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L 4140 #define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L 4141 #define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L 4142 #define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L 4143 #define MMEA0_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L 4144 #define MMEA0_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L 4145 #define MMEA0_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L 4146 #define MMEA0_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L 4147 #define MMEA0_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L 4148 #define MMEA0_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L 4149 #define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L 4150 #define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L 4151 #define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L 4152 #define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L 4153 //MMEA0_DSM_CNTL2 4154 #define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 4155 #define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2 4156 #define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 4157 #define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5 4158 #define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 4159 #define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8 4160 #define MMEA0_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 4161 #define MMEA0_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb 4162 #define MMEA0_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc 4163 #define MMEA0_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe 4164 #define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf 4165 #define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11 4166 #define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 4167 #define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14 4168 #define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15 4169 #define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17 4170 #define MMEA0_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a 4171 #define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L 4172 #define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L 4173 #define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L 4174 #define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L 4175 #define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L 4176 #define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L 4177 #define MMEA0_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L 4178 #define MMEA0_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L 4179 #define MMEA0_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L 4180 #define MMEA0_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L 4181 #define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L 4182 #define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L 4183 #define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L 4184 #define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L 4185 #define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L 4186 #define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L 4187 #define MMEA0_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L 4188 //MMEA0_DSM_CNTL2A 4189 #define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 4190 #define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2 4191 #define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 4192 #define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5 4193 #define MMEA0_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 4194 #define MMEA0_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8 4195 #define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 4196 #define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb 4197 #define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc 4198 #define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe 4199 #define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf 4200 #define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11 4201 #define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 4202 #define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14 4203 #define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L 4204 #define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L 4205 #define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L 4206 #define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L 4207 #define MMEA0_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L 4208 #define MMEA0_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L 4209 #define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L 4210 #define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L 4211 #define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L 4212 #define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L 4213 #define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L 4214 #define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L 4215 #define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L 4216 #define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L 4217 //MMEA0_CGTT_CLK_CTRL 4218 #define MMEA0_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 4219 #define MMEA0_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 4220 #define MMEA0_CGTT_CLK_CTRL__SPARE0__SHIFT 0xc 4221 #define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT 0x14 4222 #define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT 0x15 4223 #define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT 0x16 4224 #define MMEA0_CGTT_CLK_CTRL__SPARE1__SHIFT 0x17 4225 #define MMEA0_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 4226 #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c 4227 #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d 4228 #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e 4229 #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f 4230 #define MMEA0_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 4231 #define MMEA0_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 4232 #define MMEA0_CGTT_CLK_CTRL__SPARE0_MASK 0x000FF000L 4233 #define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK 0x00100000L 4234 #define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK 0x00200000L 4235 #define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK 0x00400000L 4236 #define MMEA0_CGTT_CLK_CTRL__SPARE1_MASK 0x07800000L 4237 #define MMEA0_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 4238 #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L 4239 #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L 4240 #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L 4241 #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L 4242 //MMEA0_EDC_MODE 4243 #define MMEA0_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 4244 #define MMEA0_EDC_MODE__GATE_FUE__SHIFT 0x11 4245 #define MMEA0_EDC_MODE__DED_MODE__SHIFT 0x14 4246 #define MMEA0_EDC_MODE__PROP_FED__SHIFT 0x1d 4247 #define MMEA0_EDC_MODE__BYPASS__SHIFT 0x1f 4248 #define MMEA0_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L 4249 #define MMEA0_EDC_MODE__GATE_FUE_MASK 0x00020000L 4250 #define MMEA0_EDC_MODE__DED_MODE_MASK 0x00300000L 4251 #define MMEA0_EDC_MODE__PROP_FED_MASK 0x20000000L 4252 #define MMEA0_EDC_MODE__BYPASS_MASK 0x80000000L 4253 //MMEA0_ERR_STATUS 4254 #define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 4255 #define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 4256 #define MMEA0_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 4257 #define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa 4258 #define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb 4259 #define MMEA0_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc 4260 #define MMEA0_ERR_STATUS__FUE_FLAG__SHIFT 0xd 4261 #define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL 4262 #define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L 4263 #define MMEA0_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L 4264 #define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L 4265 #define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L 4266 #define MMEA0_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L 4267 #define MMEA0_ERR_STATUS__FUE_FLAG_MASK 0x00002000L 4268 //MMEA0_MISC2 4269 #define MMEA0_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0 4270 #define MMEA0_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1 4271 #define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2 4272 #define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7 4273 #define MMEA0_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0xc 4274 #define MMEA0_MISC2__RRET_SWAP_MODE__SHIFT 0xd 4275 #define MMEA0_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L 4276 #define MMEA0_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L 4277 #define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL 4278 #define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L 4279 #define MMEA0_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00001000L 4280 #define MMEA0_MISC2__RRET_SWAP_MODE_MASK 0x00002000L 4281 //MMEA0_ADDRDEC_SELECT 4282 #define MMEA0_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT 0x0 4283 #define MMEA0_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT 0x5 4284 #define MMEA0_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT 0xa 4285 #define MMEA0_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT 0xf 4286 #define MMEA0_ADDRDEC_SELECT__DRAM_GECC_ENABLE__SHIFT 0x14 4287 #define MMEA0_ADDRDEC_SELECT__GMI_GECC_ENABLE__SHIFT 0x15 4288 #define MMEA0_ADDRDEC_SELECT__DRAM_SKIP_MSB__SHIFT 0x16 4289 #define MMEA0_ADDRDEC_SELECT__GMI_SKIP_MSB__SHIFT 0x17 4290 #define MMEA0_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK 0x0000001FL 4291 #define MMEA0_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK 0x000003E0L 4292 #define MMEA0_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK 0x00007C00L 4293 #define MMEA0_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK 0x000F8000L 4294 #define MMEA0_ADDRDEC_SELECT__DRAM_GECC_ENABLE_MASK 0x00100000L 4295 #define MMEA0_ADDRDEC_SELECT__GMI_GECC_ENABLE_MASK 0x00200000L 4296 #define MMEA0_ADDRDEC_SELECT__DRAM_SKIP_MSB_MASK 0x00400000L 4297 #define MMEA0_ADDRDEC_SELECT__GMI_SKIP_MSB_MASK 0x00800000L 4298 4299 4300 // addressBlock: mmhub_pctldec 4301 //PCTL_MISC 4302 #define PCTL_MISC__ALLOW_DEEP_SLEEP_MODE__SHIFT 0x0 4303 #define PCTL_MISC__STCTRL_RSMU_IDLE_THRESHOLD__SHIFT 0x3 4304 #define PCTL_MISC__STCTRL_DAGB_IDLE_THRESHOLD__SHIFT 0x6 4305 #define PCTL_MISC__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT 0xb 4306 #define PCTL_MISC__OVR_EA0_SDP_PARTACK__SHIFT 0xc 4307 #define PCTL_MISC__OVR_EA1_SDP_PARTACK__SHIFT 0xd 4308 #define PCTL_MISC__OVR_EA0_SDP_FULLACK__SHIFT 0xe 4309 #define PCTL_MISC__OVR_EA1_SDP_FULLACK__SHIFT 0xf 4310 #define PCTL_MISC__PGFSM_CMD_STATUS__SHIFT 0x10 4311 #define PCTL_MISC__ALLOW_DEEP_SLEEP_MODE_MASK 0x00000007L 4312 #define PCTL_MISC__STCTRL_RSMU_IDLE_THRESHOLD_MASK 0x00000038L 4313 #define PCTL_MISC__STCTRL_DAGB_IDLE_THRESHOLD_MASK 0x000007C0L 4314 #define PCTL_MISC__STCTRL_IGNORE_PROTECTION_FAULT_MASK 0x00000800L 4315 #define PCTL_MISC__OVR_EA0_SDP_PARTACK_MASK 0x00001000L 4316 #define PCTL_MISC__OVR_EA1_SDP_PARTACK_MASK 0x00002000L 4317 #define PCTL_MISC__OVR_EA0_SDP_FULLACK_MASK 0x00004000L 4318 #define PCTL_MISC__OVR_EA1_SDP_FULLACK_MASK 0x00008000L 4319 #define PCTL_MISC__PGFSM_CMD_STATUS_MASK 0x00030000L 4320 //PCTL_MMHUB_DEEPSLEEP 4321 #define PCTL_MMHUB_DEEPSLEEP__DS0__SHIFT 0x0 4322 #define PCTL_MMHUB_DEEPSLEEP__DS1__SHIFT 0x1 4323 #define PCTL_MMHUB_DEEPSLEEP__DS2__SHIFT 0x2 4324 #define PCTL_MMHUB_DEEPSLEEP__DS3__SHIFT 0x3 4325 #define PCTL_MMHUB_DEEPSLEEP__DS4__SHIFT 0x4 4326 #define PCTL_MMHUB_DEEPSLEEP__DS5__SHIFT 0x5 4327 #define PCTL_MMHUB_DEEPSLEEP__DS6__SHIFT 0x6 4328 #define PCTL_MMHUB_DEEPSLEEP__DS7__SHIFT 0x7 4329 #define PCTL_MMHUB_DEEPSLEEP__DS8__SHIFT 0x8 4330 #define PCTL_MMHUB_DEEPSLEEP__DS9__SHIFT 0x9 4331 #define PCTL_MMHUB_DEEPSLEEP__DS10__SHIFT 0xa 4332 #define PCTL_MMHUB_DEEPSLEEP__DS11__SHIFT 0xb 4333 #define PCTL_MMHUB_DEEPSLEEP__DS12__SHIFT 0xc 4334 #define PCTL_MMHUB_DEEPSLEEP__DS13__SHIFT 0xd 4335 #define PCTL_MMHUB_DEEPSLEEP__DS14__SHIFT 0xe 4336 #define PCTL_MMHUB_DEEPSLEEP__DS15__SHIFT 0xf 4337 #define PCTL_MMHUB_DEEPSLEEP__DS16__SHIFT 0x10 4338 #define PCTL_MMHUB_DEEPSLEEP__SETCLEAR__SHIFT 0x1f 4339 #define PCTL_MMHUB_DEEPSLEEP__DS0_MASK 0x00000001L 4340 #define PCTL_MMHUB_DEEPSLEEP__DS1_MASK 0x00000002L 4341 #define PCTL_MMHUB_DEEPSLEEP__DS2_MASK 0x00000004L 4342 #define PCTL_MMHUB_DEEPSLEEP__DS3_MASK 0x00000008L 4343 #define PCTL_MMHUB_DEEPSLEEP__DS4_MASK 0x00000010L 4344 #define PCTL_MMHUB_DEEPSLEEP__DS5_MASK 0x00000020L 4345 #define PCTL_MMHUB_DEEPSLEEP__DS6_MASK 0x00000040L 4346 #define PCTL_MMHUB_DEEPSLEEP__DS7_MASK 0x00000080L 4347 #define PCTL_MMHUB_DEEPSLEEP__DS8_MASK 0x00000100L 4348 #define PCTL_MMHUB_DEEPSLEEP__DS9_MASK 0x00000200L 4349 #define PCTL_MMHUB_DEEPSLEEP__DS10_MASK 0x00000400L 4350 #define PCTL_MMHUB_DEEPSLEEP__DS11_MASK 0x00000800L 4351 #define PCTL_MMHUB_DEEPSLEEP__DS12_MASK 0x00001000L 4352 #define PCTL_MMHUB_DEEPSLEEP__DS13_MASK 0x00002000L 4353 #define PCTL_MMHUB_DEEPSLEEP__DS14_MASK 0x00004000L 4354 #define PCTL_MMHUB_DEEPSLEEP__DS15_MASK 0x00008000L 4355 #define PCTL_MMHUB_DEEPSLEEP__DS16_MASK 0x00010000L 4356 #define PCTL_MMHUB_DEEPSLEEP__SETCLEAR_MASK 0x80000000L 4357 //PCTL_MMHUB_DEEPSLEEP_OVERRIDE 4358 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0__SHIFT 0x0 4359 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1__SHIFT 0x1 4360 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2__SHIFT 0x2 4361 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3__SHIFT 0x3 4362 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4__SHIFT 0x4 4363 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5__SHIFT 0x5 4364 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6__SHIFT 0x6 4365 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7__SHIFT 0x7 4366 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8__SHIFT 0x8 4367 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9__SHIFT 0x9 4368 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10__SHIFT 0xa 4369 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11__SHIFT 0xb 4370 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12__SHIFT 0xc 4371 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13__SHIFT 0xd 4372 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14__SHIFT 0xe 4373 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15__SHIFT 0xf 4374 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16__SHIFT 0x10 4375 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0_MASK 0x00000001L 4376 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1_MASK 0x00000002L 4377 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2_MASK 0x00000004L 4378 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3_MASK 0x00000008L 4379 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4_MASK 0x00000010L 4380 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5_MASK 0x00000020L 4381 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6_MASK 0x00000040L 4382 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7_MASK 0x00000080L 4383 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8_MASK 0x00000100L 4384 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9_MASK 0x00000200L 4385 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10_MASK 0x00000400L 4386 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11_MASK 0x00000800L 4387 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12_MASK 0x00001000L 4388 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13_MASK 0x00002000L 4389 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14_MASK 0x00004000L 4390 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15_MASK 0x00008000L 4391 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16_MASK 0x00010000L 4392 //PCTL_PG_IGNORE_DEEPSLEEP 4393 #define PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS__SHIFT 0x0 4394 #define PCTL_PG_IGNORE_DEEPSLEEP__DS0__SHIFT 0x1 4395 #define PCTL_PG_IGNORE_DEEPSLEEP__DS1__SHIFT 0x2 4396 #define PCTL_PG_IGNORE_DEEPSLEEP__DS2__SHIFT 0x3 4397 #define PCTL_PG_IGNORE_DEEPSLEEP__DS3__SHIFT 0x4 4398 #define PCTL_PG_IGNORE_DEEPSLEEP__DS4__SHIFT 0x5 4399 #define PCTL_PG_IGNORE_DEEPSLEEP__DS5__SHIFT 0x6 4400 #define PCTL_PG_IGNORE_DEEPSLEEP__DS6__SHIFT 0x7 4401 #define PCTL_PG_IGNORE_DEEPSLEEP__DS7__SHIFT 0x8 4402 #define PCTL_PG_IGNORE_DEEPSLEEP__DS8__SHIFT 0x9 4403 #define PCTL_PG_IGNORE_DEEPSLEEP__DS9__SHIFT 0xa 4404 #define PCTL_PG_IGNORE_DEEPSLEEP__DS10__SHIFT 0xb 4405 #define PCTL_PG_IGNORE_DEEPSLEEP__DS11__SHIFT 0xc 4406 #define PCTL_PG_IGNORE_DEEPSLEEP__DS12__SHIFT 0xd 4407 #define PCTL_PG_IGNORE_DEEPSLEEP__DS13__SHIFT 0xe 4408 #define PCTL_PG_IGNORE_DEEPSLEEP__DS14__SHIFT 0xf 4409 #define PCTL_PG_IGNORE_DEEPSLEEP__DS15__SHIFT 0x10 4410 #define PCTL_PG_IGNORE_DEEPSLEEP__DS16__SHIFT 0x11 4411 #define PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS_MASK 0x00000001L 4412 #define PCTL_PG_IGNORE_DEEPSLEEP__DS0_MASK 0x00000002L 4413 #define PCTL_PG_IGNORE_DEEPSLEEP__DS1_MASK 0x00000004L 4414 #define PCTL_PG_IGNORE_DEEPSLEEP__DS2_MASK 0x00000008L 4415 #define PCTL_PG_IGNORE_DEEPSLEEP__DS3_MASK 0x00000010L 4416 #define PCTL_PG_IGNORE_DEEPSLEEP__DS4_MASK 0x00000020L 4417 #define PCTL_PG_IGNORE_DEEPSLEEP__DS5_MASK 0x00000040L 4418 #define PCTL_PG_IGNORE_DEEPSLEEP__DS6_MASK 0x00000080L 4419 #define PCTL_PG_IGNORE_DEEPSLEEP__DS7_MASK 0x00000100L 4420 #define PCTL_PG_IGNORE_DEEPSLEEP__DS8_MASK 0x00000200L 4421 #define PCTL_PG_IGNORE_DEEPSLEEP__DS9_MASK 0x00000400L 4422 #define PCTL_PG_IGNORE_DEEPSLEEP__DS10_MASK 0x00000800L 4423 #define PCTL_PG_IGNORE_DEEPSLEEP__DS11_MASK 0x00001000L 4424 #define PCTL_PG_IGNORE_DEEPSLEEP__DS12_MASK 0x00002000L 4425 #define PCTL_PG_IGNORE_DEEPSLEEP__DS13_MASK 0x00004000L 4426 #define PCTL_PG_IGNORE_DEEPSLEEP__DS14_MASK 0x00008000L 4427 #define PCTL_PG_IGNORE_DEEPSLEEP__DS15_MASK 0x00010000L 4428 #define PCTL_PG_IGNORE_DEEPSLEEP__DS16_MASK 0x00020000L 4429 //PCTL_PG_DAGB 4430 #define PCTL_PG_DAGB__DS0__SHIFT 0x0 4431 #define PCTL_PG_DAGB__DS1__SHIFT 0x1 4432 #define PCTL_PG_DAGB__DS2__SHIFT 0x2 4433 #define PCTL_PG_DAGB__DS3__SHIFT 0x3 4434 #define PCTL_PG_DAGB__DS4__SHIFT 0x4 4435 #define PCTL_PG_DAGB__DS5__SHIFT 0x5 4436 #define PCTL_PG_DAGB__DS6__SHIFT 0x6 4437 #define PCTL_PG_DAGB__DS7__SHIFT 0x7 4438 #define PCTL_PG_DAGB__DS8__SHIFT 0x8 4439 #define PCTL_PG_DAGB__DS9__SHIFT 0x9 4440 #define PCTL_PG_DAGB__DS10__SHIFT 0xa 4441 #define PCTL_PG_DAGB__DS11__SHIFT 0xb 4442 #define PCTL_PG_DAGB__DS12__SHIFT 0xc 4443 #define PCTL_PG_DAGB__DS13__SHIFT 0xd 4444 #define PCTL_PG_DAGB__DS14__SHIFT 0xe 4445 #define PCTL_PG_DAGB__DS15__SHIFT 0xf 4446 #define PCTL_PG_DAGB__DS16__SHIFT 0x10 4447 #define PCTL_PG_DAGB__DS0_MASK 0x00000001L 4448 #define PCTL_PG_DAGB__DS1_MASK 0x00000002L 4449 #define PCTL_PG_DAGB__DS2_MASK 0x00000004L 4450 #define PCTL_PG_DAGB__DS3_MASK 0x00000008L 4451 #define PCTL_PG_DAGB__DS4_MASK 0x00000010L 4452 #define PCTL_PG_DAGB__DS5_MASK 0x00000020L 4453 #define PCTL_PG_DAGB__DS6_MASK 0x00000040L 4454 #define PCTL_PG_DAGB__DS7_MASK 0x00000080L 4455 #define PCTL_PG_DAGB__DS8_MASK 0x00000100L 4456 #define PCTL_PG_DAGB__DS9_MASK 0x00000200L 4457 #define PCTL_PG_DAGB__DS10_MASK 0x00000400L 4458 #define PCTL_PG_DAGB__DS11_MASK 0x00000800L 4459 #define PCTL_PG_DAGB__DS12_MASK 0x00001000L 4460 #define PCTL_PG_DAGB__DS13_MASK 0x00002000L 4461 #define PCTL_PG_DAGB__DS14_MASK 0x00004000L 4462 #define PCTL_PG_DAGB__DS15_MASK 0x00008000L 4463 #define PCTL_PG_DAGB__DS16_MASK 0x00010000L 4464 //PCTL0_RENG_RAM_INDEX 4465 #define PCTL0_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 4466 #define PCTL0_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000007FFL 4467 //PCTL0_RENG_RAM_DATA 4468 #define PCTL0_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 4469 #define PCTL0_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL 4470 //PCTL0_RENG_EXECUTE 4471 #define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0 4472 #define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 4473 #define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 4474 #define PCTL0_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xd 4475 #define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L 4476 #define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L 4477 #define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00001FFCL 4478 #define PCTL0_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x00FFE000L 4479 //PCTL1_RENG_RAM_INDEX 4480 #define PCTL1_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 4481 #define PCTL1_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL 4482 //PCTL1_RENG_RAM_DATA 4483 #define PCTL1_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 4484 #define PCTL1_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL 4485 //PCTL1_RENG_EXECUTE 4486 #define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0 4487 #define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 4488 #define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 4489 #define PCTL1_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xc 4490 #define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L 4491 #define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L 4492 #define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00000FFCL 4493 #define PCTL1_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x003FF000L 4494 //PCTL2_RENG_RAM_INDEX 4495 #define PCTL2_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 4496 #define PCTL2_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL 4497 //PCTL2_RENG_RAM_DATA 4498 #define PCTL2_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 4499 #define PCTL2_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL 4500 //PCTL2_RENG_EXECUTE 4501 #define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0 4502 #define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 4503 #define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 4504 #define PCTL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xc 4505 #define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L 4506 #define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L 4507 #define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00000FFCL 4508 #define PCTL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x003FF000L 4509 //PCTL0_STCTRL_REGISTER_SAVE_RANGE0 4510 #define PCTL0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4511 #define PCTL0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4512 #define PCTL0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4513 #define PCTL0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4514 //PCTL0_STCTRL_REGISTER_SAVE_RANGE1 4515 #define PCTL0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4516 #define PCTL0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4517 #define PCTL0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4518 #define PCTL0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4519 //PCTL0_STCTRL_REGISTER_SAVE_RANGE2 4520 #define PCTL0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4521 #define PCTL0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4522 #define PCTL0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4523 #define PCTL0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4524 //PCTL0_STCTRL_REGISTER_SAVE_RANGE3 4525 #define PCTL0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4526 #define PCTL0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4527 #define PCTL0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4528 #define PCTL0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4529 //PCTL0_STCTRL_REGISTER_SAVE_RANGE4 4530 #define PCTL0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4531 #define PCTL0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4532 #define PCTL0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4533 #define PCTL0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4534 //PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET 4535 #define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 4536 #define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 4537 #define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL 4538 #define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L 4539 //PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1 4540 #define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 4541 #define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 4542 #define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL 4543 #define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L 4544 //PCTL1_STCTRL_REGISTER_SAVE_RANGE0 4545 #define PCTL1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4546 #define PCTL1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4547 #define PCTL1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4548 #define PCTL1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4549 //PCTL1_STCTRL_REGISTER_SAVE_RANGE1 4550 #define PCTL1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4551 #define PCTL1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4552 #define PCTL1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4553 #define PCTL1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4554 //PCTL1_STCTRL_REGISTER_SAVE_RANGE2 4555 #define PCTL1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4556 #define PCTL1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4557 #define PCTL1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4558 #define PCTL1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4559 //PCTL1_STCTRL_REGISTER_SAVE_RANGE3 4560 #define PCTL1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4561 #define PCTL1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4562 #define PCTL1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4563 #define PCTL1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4564 //PCTL1_STCTRL_REGISTER_SAVE_RANGE4 4565 #define PCTL1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4566 #define PCTL1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4567 #define PCTL1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4568 #define PCTL1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4569 //PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET 4570 #define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 4571 #define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 4572 #define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL 4573 #define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L 4574 //PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1 4575 #define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 4576 #define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 4577 #define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL 4578 #define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L 4579 //PCTL2_STCTRL_REGISTER_SAVE_RANGE0 4580 #define PCTL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4581 #define PCTL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4582 #define PCTL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4583 #define PCTL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4584 //PCTL2_STCTRL_REGISTER_SAVE_RANGE1 4585 #define PCTL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4586 #define PCTL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4587 #define PCTL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4588 #define PCTL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4589 //PCTL2_STCTRL_REGISTER_SAVE_RANGE2 4590 #define PCTL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4591 #define PCTL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4592 #define PCTL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4593 #define PCTL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4594 //PCTL2_STCTRL_REGISTER_SAVE_RANGE3 4595 #define PCTL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4596 #define PCTL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4597 #define PCTL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4598 #define PCTL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4599 //PCTL2_STCTRL_REGISTER_SAVE_RANGE4 4600 #define PCTL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4601 #define PCTL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4602 #define PCTL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4603 #define PCTL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4604 //PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET 4605 #define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 4606 #define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 4607 #define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL 4608 #define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L 4609 //PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1 4610 #define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 4611 #define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 4612 #define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL 4613 #define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L 4614 //PCTL0_MISC 4615 #define PCTL0_MISC__CRITICAL_REGS_LOCK__SHIFT 0xb 4616 #define PCTL0_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xc 4617 #define PCTL0_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xf 4618 #define PCTL0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0x10 4619 #define PCTL0_MISC__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x11 4620 #define PCTL0_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x12 4621 #define PCTL0_MISC__RD_TIMER_ENABLE__SHIFT 0x13 4622 #define PCTL0_MISC__CRITICAL_REGS_LOCK_MASK 0x00000800L 4623 #define PCTL0_MISC__TILE_IDLE_THRESHOLD_MASK 0x00007000L 4624 #define PCTL0_MISC__RENG_MEM_LS_ENABLE_MASK 0x00008000L 4625 #define PCTL0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00010000L 4626 #define PCTL0_MISC__RENG_EXECUTE_ON_PWR_UP_MASK 0x00020000L 4627 #define PCTL0_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00040000L 4628 #define PCTL0_MISC__RD_TIMER_ENABLE_MASK 0x00080000L 4629 //PCTL1_MISC 4630 #define PCTL1_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa 4631 #define PCTL1_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb 4632 #define PCTL1_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe 4633 #define PCTL1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf 4634 #define PCTL1_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 4635 #define PCTL1_MISC__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x11 4636 #define PCTL1_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x12 4637 #define PCTL1_MISC__RD_TIMER_ENABLE__SHIFT 0x13 4638 #define PCTL1_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L 4639 #define PCTL1_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L 4640 #define PCTL1_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L 4641 #define PCTL1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L 4642 #define PCTL1_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L 4643 #define PCTL1_MISC__RENG_EXECUTE_ON_PWR_UP_MASK 0x00020000L 4644 #define PCTL1_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00040000L 4645 #define PCTL1_MISC__RD_TIMER_ENABLE_MASK 0x00080000L 4646 //PCTL2_MISC 4647 #define PCTL2_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa 4648 #define PCTL2_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb 4649 #define PCTL2_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe 4650 #define PCTL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf 4651 #define PCTL2_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 4652 #define PCTL2_MISC__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x11 4653 #define PCTL2_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x12 4654 #define PCTL2_MISC__RD_TIMER_ENABLE__SHIFT 0x13 4655 #define PCTL2_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L 4656 #define PCTL2_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L 4657 #define PCTL2_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L 4658 #define PCTL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L 4659 #define PCTL2_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L 4660 #define PCTL2_MISC__RENG_EXECUTE_ON_PWR_UP_MASK 0x00020000L 4661 #define PCTL2_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00040000L 4662 #define PCTL2_MISC__RD_TIMER_ENABLE_MASK 0x00080000L 4663 //PCTL_PERFCOUNTER_LO 4664 #define PCTL_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 4665 #define PCTL_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 4666 //PCTL_PERFCOUNTER_HI 4667 #define PCTL_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 4668 #define PCTL_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 4669 #define PCTL_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 4670 #define PCTL_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 4671 //PCTL_PERFCOUNTER0_CFG 4672 #define PCTL_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 4673 #define PCTL_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 4674 #define PCTL_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 4675 #define PCTL_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 4676 #define PCTL_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 4677 #define PCTL_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 4678 #define PCTL_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 4679 #define PCTL_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 4680 #define PCTL_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 4681 #define PCTL_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 4682 //PCTL_PERFCOUNTER1_CFG 4683 #define PCTL_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 4684 #define PCTL_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 4685 #define PCTL_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 4686 #define PCTL_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 4687 #define PCTL_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 4688 #define PCTL_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 4689 #define PCTL_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 4690 #define PCTL_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 4691 #define PCTL_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 4692 #define PCTL_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 4693 //PCTL_PERFCOUNTER_RSLT_CNTL 4694 #define PCTL_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 4695 #define PCTL_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 4696 #define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 4697 #define PCTL_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 4698 #define PCTL_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 4699 #define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 4700 #define PCTL_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 4701 #define PCTL_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 4702 #define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 4703 #define PCTL_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 4704 #define PCTL_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 4705 #define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 4706 4707 4708 // addressBlock: mmhub_l1tlb_mmvml1pfdec 4709 //MMMC_VM_MX_L1_TLB0_STATUS 4710 #define MMMC_VM_MX_L1_TLB0_STATUS__BUSY__SHIFT 0x0 4711 #define MMMC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 4712 #define MMMC_VM_MX_L1_TLB0_STATUS__BUSY_MASK 0x00000001L 4713 #define MMMC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 4714 //MMMC_VM_MX_L1_TLB1_STATUS 4715 #define MMMC_VM_MX_L1_TLB1_STATUS__BUSY__SHIFT 0x0 4716 #define MMMC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 4717 #define MMMC_VM_MX_L1_TLB1_STATUS__BUSY_MASK 0x00000001L 4718 #define MMMC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 4719 //MMMC_VM_MX_L1_TLB2_STATUS 4720 #define MMMC_VM_MX_L1_TLB2_STATUS__BUSY__SHIFT 0x0 4721 #define MMMC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 4722 #define MMMC_VM_MX_L1_TLB2_STATUS__BUSY_MASK 0x00000001L 4723 #define MMMC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 4724 //MMMC_VM_MX_L1_TLB3_STATUS 4725 #define MMMC_VM_MX_L1_TLB3_STATUS__BUSY__SHIFT 0x0 4726 #define MMMC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 4727 #define MMMC_VM_MX_L1_TLB3_STATUS__BUSY_MASK 0x00000001L 4728 #define MMMC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 4729 //MMMC_VM_MX_L1_TLB4_STATUS 4730 #define MMMC_VM_MX_L1_TLB4_STATUS__BUSY__SHIFT 0x0 4731 #define MMMC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 4732 #define MMMC_VM_MX_L1_TLB4_STATUS__BUSY_MASK 0x00000001L 4733 #define MMMC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 4734 //MMMC_VM_MX_L1_TLB5_STATUS 4735 #define MMMC_VM_MX_L1_TLB5_STATUS__BUSY__SHIFT 0x0 4736 #define MMMC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 4737 #define MMMC_VM_MX_L1_TLB5_STATUS__BUSY_MASK 0x00000001L 4738 #define MMMC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 4739 //MMMC_VM_MX_L1_TLB6_STATUS 4740 #define MMMC_VM_MX_L1_TLB6_STATUS__BUSY__SHIFT 0x0 4741 #define MMMC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 4742 #define MMMC_VM_MX_L1_TLB6_STATUS__BUSY_MASK 0x00000001L 4743 #define MMMC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 4744 //MMMC_VM_MX_L1_TLB7_STATUS 4745 #define MMMC_VM_MX_L1_TLB7_STATUS__BUSY__SHIFT 0x0 4746 #define MMMC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 4747 #define MMMC_VM_MX_L1_TLB7_STATUS__BUSY_MASK 0x00000001L 4748 #define MMMC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 4749 4750 4751 // addressBlock: mmhub_l1tlb_mmvml1pldec 4752 //MMMC_VM_MX_L1_PERFCOUNTER0_CFG 4753 #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 4754 #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 4755 #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 4756 #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 4757 #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 4758 #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 4759 #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 4760 #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 4761 #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 4762 #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 4763 //MMMC_VM_MX_L1_PERFCOUNTER1_CFG 4764 #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 4765 #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 4766 #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 4767 #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 4768 #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 4769 #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 4770 #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 4771 #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 4772 #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 4773 #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 4774 //MMMC_VM_MX_L1_PERFCOUNTER2_CFG 4775 #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 4776 #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 4777 #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 4778 #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 4779 #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 4780 #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 4781 #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 4782 #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 4783 #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 4784 #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 4785 //MMMC_VM_MX_L1_PERFCOUNTER3_CFG 4786 #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 4787 #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 4788 #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 4789 #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c 4790 #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 4791 #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL 4792 #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L 4793 #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L 4794 #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L 4795 #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L 4796 //MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL 4797 #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 4798 #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 4799 #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 4800 #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 4801 #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 4802 #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 4803 #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 4804 #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 4805 #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 4806 #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 4807 #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 4808 #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 4809 4810 4811 // addressBlock: mmhub_l1tlb_mmvml1prdec 4812 //MMMC_VM_MX_L1_PERFCOUNTER_LO 4813 #define MMMC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 4814 #define MMMC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 4815 //MMMC_VM_MX_L1_PERFCOUNTER_HI 4816 #define MMMC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 4817 #define MMMC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 4818 #define MMMC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 4819 #define MMMC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 4820 4821 4822 // addressBlock: mmhub_mmutcl2_mmatcl2dec 4823 //MM_ATC_L2_CNTL 4824 #define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0 4825 #define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x3 4826 #define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x6 4827 #define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x7 4828 #define MM_ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT 0x8 4829 #define MM_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb 4830 #define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x00000003L 4831 #define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x00000018L 4832 #define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00000040L 4833 #define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00000080L 4834 #define MM_ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK 0x00000700L 4835 #define MM_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L 4836 //MM_ATC_L2_CNTL2 4837 #define MM_ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0 4838 #define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x6 4839 #define MM_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x8 4840 #define MM_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0x9 4841 #define MM_ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xc 4842 #define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0xf 4843 #define MM_ATC_L2_CNTL2__BANK_SELECT_MASK 0x0000003FL 4844 #define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L 4845 #define MM_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000100L 4846 #define MM_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0x00000E00L 4847 #define MM_ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x00007000L 4848 #define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x001F8000L 4849 //MM_ATC_L2_CACHE_DATA0 4850 #define MM_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT 0x0 4851 #define MM_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT 0x1 4852 #define MM_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT 0x2 4853 #define MM_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT 0x18 4854 #define MM_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK 0x00000001L 4855 #define MM_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK 0x00000002L 4856 #define MM_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK 0x00FFFFFCL 4857 #define MM_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK 0x0F000000L 4858 //MM_ATC_L2_CACHE_DATA1 4859 #define MM_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT 0x0 4860 #define MM_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK 0xFFFFFFFFL 4861 //MM_ATC_L2_CACHE_DATA2 4862 #define MM_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT 0x0 4863 #define MM_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK 0xFFFFFFFFL 4864 //MM_ATC_L2_CNTL3 4865 #define MM_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT 0x0 4866 #define MM_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT 0x3 4867 #define MM_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS__SHIFT 0x9 4868 #define MM_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK 0x00000007L 4869 #define MM_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK 0x000001F8L 4870 #define MM_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS_MASK 0x00000E00L 4871 //MM_ATC_L2_STATUS 4872 #define MM_ATC_L2_STATUS__BUSY__SHIFT 0x0 4873 #define MM_ATC_L2_STATUS__PARITY_ERROR_INFO__SHIFT 0x1 4874 #define MM_ATC_L2_STATUS__BUSY_MASK 0x00000001L 4875 #define MM_ATC_L2_STATUS__PARITY_ERROR_INFO_MASK 0x3FFFFFFEL 4876 //MM_ATC_L2_STATUS2 4877 #define MM_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO__SHIFT 0x0 4878 #define MM_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO__SHIFT 0x8 4879 #define MM_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO_MASK 0x000000FFL 4880 #define MM_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO_MASK 0x0000FF00L 4881 //MM_ATC_L2_MISC_CG 4882 #define MM_ATC_L2_MISC_CG__OFFDLY__SHIFT 0x6 4883 #define MM_ATC_L2_MISC_CG__ENABLE__SHIFT 0x12 4884 #define MM_ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13 4885 #define MM_ATC_L2_MISC_CG__OFFDLY_MASK 0x00000FC0L 4886 #define MM_ATC_L2_MISC_CG__ENABLE_MASK 0x00040000L 4887 #define MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK 0x00080000L 4888 //MM_ATC_L2_MEM_POWER_LS 4889 #define MM_ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 4890 #define MM_ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 4891 #define MM_ATC_L2_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL 4892 #define MM_ATC_L2_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L 4893 //MM_ATC_L2_CGTT_CLK_CTRL 4894 #define MM_ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 4895 #define MM_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 4896 #define MM_ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf 4897 #define MM_ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 4898 #define MM_ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 4899 #define MM_ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 4900 #define MM_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 4901 #define MM_ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L 4902 #define MM_ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L 4903 #define MM_ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L 4904 //MM_ATC_L2_SDPPORT_CTRL 4905 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKEN__SHIFT 0x0 4906 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKENRCV__SHIFT 0x1 4907 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKEN__SHIFT 0x2 4908 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKENRCV__SHIFT 0x3 4909 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKEN__SHIFT 0x4 4910 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKENRCV__SHIFT 0x5 4911 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKEN__SHIFT 0x6 4912 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKENRCV__SHIFT 0x7 4913 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKEN__SHIFT 0x8 4914 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKENRCV__SHIFT 0x9 4915 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKEN_MASK 0x00000001L 4916 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKENRCV_MASK 0x00000002L 4917 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKEN_MASK 0x00000004L 4918 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKENRCV_MASK 0x00000008L 4919 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKEN_MASK 0x00000010L 4920 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKENRCV_MASK 0x00000020L 4921 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKEN_MASK 0x00000040L 4922 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKENRCV_MASK 0x00000080L 4923 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKEN_MASK 0x00000100L 4924 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKENRCV_MASK 0x00000200L 4925 4926 4927 // addressBlock: mmhub_mmutcl2_mmvml2pfdec 4928 //MMVM_L2_CNTL 4929 #define MMVM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0 4930 #define MMVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1 4931 #define MMVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2 4932 #define MMVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4 4933 #define MMVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8 4934 #define MMVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9 4935 #define MMVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa 4936 #define MMVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb 4937 #define MMVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc 4938 #define MMVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf 4939 #define MMVM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12 4940 #define MMVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13 4941 #define MMVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15 4942 #define MMVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT 0x1a 4943 #define MMVM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L 4944 #define MMVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L 4945 #define MMVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL 4946 #define MMVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L 4947 #define MMVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L 4948 #define MMVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L 4949 #define MMVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L 4950 #define MMVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L 4951 #define MMVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L 4952 #define MMVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L 4953 #define MMVM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L 4954 #define MMVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L 4955 #define MMVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L 4956 #define MMVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK 0x0C000000L 4957 //MMVM_L2_CNTL2 4958 #define MMVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0 4959 #define MMVM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1 4960 #define MMVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15 4961 #define MMVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16 4962 #define MMVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT 0x17 4963 #define MMVM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a 4964 #define MMVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c 4965 #define MMVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L 4966 #define MMVM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L 4967 #define MMVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L 4968 #define MMVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L 4969 #define MMVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK 0x03800000L 4970 #define MMVM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L 4971 #define MMVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L 4972 //MMVM_L2_CNTL3 4973 #define MMVM_L2_CNTL3__BANK_SELECT__SHIFT 0x0 4974 #define MMVM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6 4975 #define MMVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8 4976 #define MMVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf 4977 #define MMVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14 4978 #define MMVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15 4979 #define MMVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18 4980 #define MMVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c 4981 #define MMVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d 4982 #define MMVM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e 4983 #define MMVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f 4984 #define MMVM_L2_CNTL3__BANK_SELECT_MASK 0x0000003FL 4985 #define MMVM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L 4986 #define MMVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L 4987 #define MMVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L 4988 #define MMVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L 4989 #define MMVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L 4990 #define MMVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L 4991 #define MMVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L 4992 #define MMVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L 4993 #define MMVM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L 4994 #define MMVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L 4995 //MMVM_L2_STATUS 4996 #define MMVM_L2_STATUS__L2_BUSY__SHIFT 0x0 4997 #define MMVM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1 4998 #define MMVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT 0x11 4999 #define MMVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT 0x12 5000 #define MMVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT 0x13 5001 #define MMVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT 0x14 5002 #define MMVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT 0x15 5003 #define MMVM_L2_STATUS__L2_BUSY_MASK 0x00000001L 5004 #define MMVM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x0001FFFEL 5005 #define MMVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK 0x00020000L 5006 #define MMVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK 0x00040000L 5007 #define MMVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK 0x00080000L 5008 #define MMVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK 0x00100000L 5009 #define MMVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK 0x00200000L 5010 //MMVM_DUMMY_PAGE_FAULT_CNTL 5011 #define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0 5012 #define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1 5013 #define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT 0x2 5014 #define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x00000001L 5015 #define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x00000002L 5016 #define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK 0x000000FCL 5017 //MMVM_DUMMY_PAGE_FAULT_ADDR_LO32 5018 #define MMVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT 0x0 5019 #define MMVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL 5020 //MMVM_DUMMY_PAGE_FAULT_ADDR_HI32 5021 #define MMVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT 0x0 5022 #define MMVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK 0x0000000FL 5023 //MMVM_INVALIDATE_CNTL 5024 #define MMVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING__SHIFT 0x0 5025 #define MMVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING__SHIFT 0x8 5026 #define MMVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING_MASK 0x000000FFL 5027 #define MMVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING_MASK 0x0000FF00L 5028 //MMVM_L2_PROTECTION_FAULT_CNTL 5029 #define MMVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0 5030 #define MMVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x1 5031 #define MMVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x2 5032 #define MMVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x3 5033 #define MMVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 5034 #define MMVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x5 5035 #define MMVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x6 5036 #define MMVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 5037 #define MMVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x8 5038 #define MMVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x9 5039 #define MMVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5040 #define MMVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb 5041 #define MMVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5042 #define MMVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0xd 5043 #define MMVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x1d 5044 #define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT 0x1e 5045 #define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT 0x1f 5046 #define MMVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L 5047 #define MMVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000002L 5048 #define MMVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000004L 5049 #define MMVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000008L 5050 #define MMVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L 5051 #define MMVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000020L 5052 #define MMVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000040L 5053 #define MMVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L 5054 #define MMVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000100L 5055 #define MMVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000200L 5056 #define MMVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5057 #define MMVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L 5058 #define MMVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5059 #define MMVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x1FFFE000L 5060 #define MMVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x20000000L 5061 #define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK 0x40000000L 5062 #define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK 0x80000000L 5063 //MMVM_L2_PROTECTION_FAULT_CNTL2 5064 #define MMVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x0 5065 #define MMVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x10 5066 #define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT 0x11 5067 #define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT 0x12 5068 #define MMVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT 0x13 5069 #define MMVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x0000FFFFL 5070 #define MMVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x00010000L 5071 #define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK 0x00020000L 5072 #define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK 0x00040000L 5073 #define MMVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK 0x00080000L 5074 //MMVM_L2_PROTECTION_FAULT_MM_CNTL3 5075 #define MMVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 5076 #define MMVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL 5077 //MMVM_L2_PROTECTION_FAULT_MM_CNTL4 5078 #define MMVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 5079 #define MMVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL 5080 //MMVM_L2_PROTECTION_FAULT_STATUS 5081 #define MMVM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT 0x0 5082 #define MMVM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT 0x1 5083 #define MMVM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT 0x4 5084 #define MMVM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT 0x8 5085 #define MMVM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT 0x9 5086 #define MMVM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT 0x12 5087 #define MMVM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x13 5088 #define MMVM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x14 5089 #define MMVM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT 0x18 5090 #define MMVM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT 0x19 5091 #define MMVM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK 0x00000001L 5092 #define MMVM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK 0x0000000EL 5093 #define MMVM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK 0x000000F0L 5094 #define MMVM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK 0x00000100L 5095 #define MMVM_L2_PROTECTION_FAULT_STATUS__CID_MASK 0x0003FE00L 5096 #define MMVM_L2_PROTECTION_FAULT_STATUS__RW_MASK 0x00040000L 5097 #define MMVM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x00080000L 5098 #define MMVM_L2_PROTECTION_FAULT_STATUS__VMID_MASK 0x00F00000L 5099 #define MMVM_L2_PROTECTION_FAULT_STATUS__VF_MASK 0x01000000L 5100 #define MMVM_L2_PROTECTION_FAULT_STATUS__VFID_MASK 0x3E000000L 5101 //MMVM_L2_PROTECTION_FAULT_ADDR_LO32 5102 #define MMVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0 5103 #define MMVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL 5104 //MMVM_L2_PROTECTION_FAULT_ADDR_HI32 5105 #define MMVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT 0x0 5106 #define MMVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK 0x0000000FL 5107 //MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 5108 #define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT 0x0 5109 #define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL 5110 //MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 5111 #define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT 0x0 5112 #define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK 0x0000000FL 5113 //MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 5114 #define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 5115 #define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 5116 //MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 5117 #define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 5118 #define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 5119 //MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 5120 #define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 5121 #define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 5122 //MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 5123 #define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 5124 #define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 5125 //MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 5126 #define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT 0x0 5127 #define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK 0xFFFFFFFFL 5128 //MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 5129 #define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT 0x0 5130 #define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK 0x0000000FL 5131 //MMVM_L2_CNTL4 5132 #define MMVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0 5133 #define MMVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT 0x6 5134 #define MMVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT 0x7 5135 #define MMVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x8 5136 #define MMVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x12 5137 #define MMVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT 0x1c 5138 #define MMVM_L2_CNTL4__GC_CH_FGCG_OFF__SHIFT 0x1d 5139 #define MMVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL 5140 #define MMVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK 0x00000040L 5141 #define MMVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK 0x00000080L 5142 #define MMVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0003FF00L 5143 #define MMVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0FFC0000L 5144 #define MMVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK 0x10000000L 5145 #define MMVM_L2_CNTL4__GC_CH_FGCG_OFF_MASK 0x20000000L 5146 //MMVM_L2_MM_GROUP_RT_CLASSES 5147 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT 0x0 5148 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT 0x1 5149 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT 0x2 5150 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT 0x3 5151 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT 0x4 5152 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT 0x5 5153 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT 0x6 5154 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT 0x7 5155 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT 0x8 5156 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT 0x9 5157 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT 0xa 5158 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT 0xb 5159 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT 0xc 5160 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT 0xd 5161 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT 0xe 5162 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT 0xf 5163 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT 0x10 5164 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT 0x11 5165 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT 0x12 5166 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT 0x13 5167 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT 0x14 5168 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT 0x15 5169 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT 0x16 5170 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT 0x17 5171 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT 0x18 5172 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT 0x19 5173 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT 0x1a 5174 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT 0x1b 5175 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT 0x1c 5176 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT 0x1d 5177 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT 0x1e 5178 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT 0x1f 5179 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK 0x00000001L 5180 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK 0x00000002L 5181 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK 0x00000004L 5182 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK 0x00000008L 5183 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK 0x00000010L 5184 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK 0x00000020L 5185 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK 0x00000040L 5186 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK 0x00000080L 5187 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK 0x00000100L 5188 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK 0x00000200L 5189 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK 0x00000400L 5190 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK 0x00000800L 5191 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK 0x00001000L 5192 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK 0x00002000L 5193 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK 0x00004000L 5194 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK 0x00008000L 5195 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK 0x00010000L 5196 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK 0x00020000L 5197 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK 0x00040000L 5198 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK 0x00080000L 5199 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK 0x00100000L 5200 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK 0x00200000L 5201 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK 0x00400000L 5202 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK 0x00800000L 5203 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK 0x01000000L 5204 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK 0x02000000L 5205 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK 0x04000000L 5206 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK 0x08000000L 5207 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK 0x10000000L 5208 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK 0x20000000L 5209 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK 0x40000000L 5210 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK 0x80000000L 5211 //MMVM_L2_BANK_SELECT_RESERVED_CID 5212 #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0 5213 #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa 5214 #define MMVM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14 5215 #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 5216 #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 5217 #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT 0x1a 5218 #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL 5219 #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L 5220 #define MMVM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x00100000L 5221 #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L 5222 #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L 5223 #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE_MASK 0x7C000000L 5224 //MMVM_L2_BANK_SELECT_RESERVED_CID2 5225 #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT 0x0 5226 #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa 5227 #define MMVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT 0x14 5228 #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 5229 #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 5230 #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT 0x1a 5231 #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL 5232 #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L 5233 #define MMVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK 0x00100000L 5234 #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L 5235 #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L 5236 #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE_MASK 0x7C000000L 5237 //MMVM_L2_CACHE_PARITY_CNTL 5238 #define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT 0x0 5239 #define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT 0x1 5240 #define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT 0x2 5241 #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT 0x3 5242 #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT 0x4 5243 #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT 0x5 5244 #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT 0x6 5245 #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT 0x9 5246 #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT 0xc 5247 #define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK 0x00000001L 5248 #define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK 0x00000002L 5249 #define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK 0x00000004L 5250 #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK 0x00000008L 5251 #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK 0x00000010L 5252 #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK 0x00000020L 5253 #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK 0x000001C0L 5254 #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK 0x00000E00L 5255 #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK 0x0000F000L 5256 //MMVM_L2_IH_LOG_CNTL 5257 #define MMVM_L2_IH_LOG_CNTL__ENABLE_LOGGING__SHIFT 0x0 5258 #define MMVM_L2_IH_LOG_CNTL__USE_L_BIT__SHIFT 0x1 5259 #define MMVM_L2_IH_LOG_CNTL__REGISTER_ADDRESS__SHIFT 0x2 5260 #define MMVM_L2_IH_LOG_CNTL__LOG_ALL_TRANSLATIONS__SHIFT 0x14 5261 #define MMVM_L2_IH_LOG_CNTL__ENABLE_LOGGING_MASK 0x00000001L 5262 #define MMVM_L2_IH_LOG_CNTL__USE_L_BIT_MASK 0x00000002L 5263 #define MMVM_L2_IH_LOG_CNTL__REGISTER_ADDRESS_MASK 0x000FFFFCL 5264 #define MMVM_L2_IH_LOG_CNTL__LOG_ALL_TRANSLATIONS_MASK 0x00100000L 5265 //MMVM_L2_IH_LOG_BUSY 5266 #define MMVM_L2_IH_LOG_BUSY__PER_VMID_TRANSLATION_BUSY__SHIFT 0x0 5267 #define MMVM_L2_IH_LOG_BUSY__PER_VMID_INVALIDATION_BUSY__SHIFT 0x10 5268 #define MMVM_L2_IH_LOG_BUSY__PER_VMID_TRANSLATION_BUSY_MASK 0x0000FFFFL 5269 #define MMVM_L2_IH_LOG_BUSY__PER_VMID_INVALIDATION_BUSY_MASK 0xFFFF0000L 5270 //MMVM_L2_CGTT_CLK_CTRL 5271 #define MMVM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 5272 #define MMVM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 5273 #define MMVM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf 5274 #define MMVM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 5275 #define MMVM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 5276 #define MMVM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 5277 #define MMVM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 5278 #define MMVM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L 5279 #define MMVM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L 5280 #define MMVM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L 5281 //MMVM_L2_CNTL5 5282 #define MMVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 5283 #define MMVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID__SHIFT 0x5 5284 #define MMVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 5285 #define MMVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID_MASK 0x00003FE0L 5286 //MMVM_L2_GCR_CNTL 5287 #define MMVM_L2_GCR_CNTL__GCR_ENABLE__SHIFT 0x0 5288 #define MMVM_L2_GCR_CNTL__GCR_CLIENT_ID__SHIFT 0x1 5289 #define MMVM_L2_GCR_CNTL__GCR_ENABLE_MASK 0x00000001L 5290 #define MMVM_L2_GCR_CNTL__GCR_CLIENT_ID_MASK 0x000003FEL 5291 //MMVML2_WALKER_MACRO_THROTTLE_TIME 5292 #define MMVML2_WALKER_MACRO_THROTTLE_TIME__TIME__SHIFT 0x0 5293 #define MMVML2_WALKER_MACRO_THROTTLE_TIME__TIME_MASK 0x00FFFFFFL 5294 //MMVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT 5295 #define MMVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT__LIMIT__SHIFT 0x1 5296 #define MMVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT__LIMIT_MASK 0x0000FFFEL 5297 //MMVML2_WALKER_MICRO_THROTTLE_TIME 5298 #define MMVML2_WALKER_MICRO_THROTTLE_TIME__TIME__SHIFT 0x0 5299 #define MMVML2_WALKER_MICRO_THROTTLE_TIME__TIME_MASK 0x00FFFFFFL 5300 //MMVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT 5301 #define MMVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT__LIMIT__SHIFT 0x1 5302 #define MMVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT__LIMIT_MASK 0x0000FFFEL 5303 5304 5305 // addressBlock: mmhub_mmutcl2_mmvml2vcdec 5306 //MMVM_CONTEXT0_CNTL 5307 #define MMVM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5308 #define MMVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5309 #define MMVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5310 #define MMVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5311 #define MMVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5312 #define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5313 #define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5314 #define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5315 #define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5316 #define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5317 #define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5318 #define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5319 #define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5320 #define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5321 #define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5322 #define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5323 #define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5324 #define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5325 #define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5326 #define MMVM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5327 #define MMVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5328 #define MMVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5329 #define MMVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5330 #define MMVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5331 #define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5332 #define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5333 #define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5334 #define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5335 #define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5336 #define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5337 #define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5338 #define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5339 #define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5340 #define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5341 #define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5342 #define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5343 #define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5344 #define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5345 //MMVM_CONTEXT1_CNTL 5346 #define MMVM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5347 #define MMVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5348 #define MMVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5349 #define MMVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5350 #define MMVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5351 #define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5352 #define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5353 #define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5354 #define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5355 #define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5356 #define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5357 #define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5358 #define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5359 #define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5360 #define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5361 #define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5362 #define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5363 #define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5364 #define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5365 #define MMVM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5366 #define MMVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5367 #define MMVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5368 #define MMVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5369 #define MMVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5370 #define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5371 #define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5372 #define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5373 #define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5374 #define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5375 #define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5376 #define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5377 #define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5378 #define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5379 #define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5380 #define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5381 #define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5382 #define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5383 #define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5384 //MMVM_CONTEXT2_CNTL 5385 #define MMVM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5386 #define MMVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5387 #define MMVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5388 #define MMVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5389 #define MMVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5390 #define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5391 #define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5392 #define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5393 #define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5394 #define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5395 #define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5396 #define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5397 #define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5398 #define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5399 #define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5400 #define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5401 #define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5402 #define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5403 #define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5404 #define MMVM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5405 #define MMVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5406 #define MMVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5407 #define MMVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5408 #define MMVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5409 #define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5410 #define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5411 #define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5412 #define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5413 #define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5414 #define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5415 #define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5416 #define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5417 #define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5418 #define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5419 #define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5420 #define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5421 #define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5422 #define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5423 //MMVM_CONTEXT3_CNTL 5424 #define MMVM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5425 #define MMVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5426 #define MMVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5427 #define MMVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5428 #define MMVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5429 #define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5430 #define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5431 #define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5432 #define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5433 #define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5434 #define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5435 #define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5436 #define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5437 #define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5438 #define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5439 #define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5440 #define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5441 #define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5442 #define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5443 #define MMVM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5444 #define MMVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5445 #define MMVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5446 #define MMVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5447 #define MMVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5448 #define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5449 #define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5450 #define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5451 #define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5452 #define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5453 #define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5454 #define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5455 #define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5456 #define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5457 #define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5458 #define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5459 #define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5460 #define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5461 #define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5462 //MMVM_CONTEXT4_CNTL 5463 #define MMVM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5464 #define MMVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5465 #define MMVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5466 #define MMVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5467 #define MMVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5468 #define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5469 #define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5470 #define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5471 #define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5472 #define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5473 #define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5474 #define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5475 #define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5476 #define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5477 #define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5478 #define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5479 #define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5480 #define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5481 #define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5482 #define MMVM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5483 #define MMVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5484 #define MMVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5485 #define MMVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5486 #define MMVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5487 #define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5488 #define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5489 #define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5490 #define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5491 #define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5492 #define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5493 #define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5494 #define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5495 #define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5496 #define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5497 #define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5498 #define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5499 #define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5500 #define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5501 //MMVM_CONTEXT5_CNTL 5502 #define MMVM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5503 #define MMVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5504 #define MMVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5505 #define MMVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5506 #define MMVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5507 #define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5508 #define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5509 #define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5510 #define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5511 #define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5512 #define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5513 #define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5514 #define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5515 #define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5516 #define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5517 #define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5518 #define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5519 #define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5520 #define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5521 #define MMVM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5522 #define MMVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5523 #define MMVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5524 #define MMVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5525 #define MMVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5526 #define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5527 #define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5528 #define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5529 #define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5530 #define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5531 #define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5532 #define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5533 #define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5534 #define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5535 #define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5536 #define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5537 #define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5538 #define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5539 #define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5540 //MMVM_CONTEXT6_CNTL 5541 #define MMVM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5542 #define MMVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5543 #define MMVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5544 #define MMVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5545 #define MMVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5546 #define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5547 #define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5548 #define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5549 #define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5550 #define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5551 #define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5552 #define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5553 #define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5554 #define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5555 #define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5556 #define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5557 #define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5558 #define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5559 #define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5560 #define MMVM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5561 #define MMVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5562 #define MMVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5563 #define MMVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5564 #define MMVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5565 #define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5566 #define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5567 #define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5568 #define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5569 #define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5570 #define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5571 #define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5572 #define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5573 #define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5574 #define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5575 #define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5576 #define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5577 #define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5578 #define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5579 //MMVM_CONTEXT7_CNTL 5580 #define MMVM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5581 #define MMVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5582 #define MMVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5583 #define MMVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5584 #define MMVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5585 #define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5586 #define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5587 #define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5588 #define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5589 #define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5590 #define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5591 #define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5592 #define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5593 #define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5594 #define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5595 #define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5596 #define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5597 #define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5598 #define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5599 #define MMVM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5600 #define MMVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5601 #define MMVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5602 #define MMVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5603 #define MMVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5604 #define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5605 #define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5606 #define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5607 #define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5608 #define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5609 #define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5610 #define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5611 #define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5612 #define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5613 #define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5614 #define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5615 #define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5616 #define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5617 #define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5618 //MMVM_CONTEXT8_CNTL 5619 #define MMVM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5620 #define MMVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5621 #define MMVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5622 #define MMVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5623 #define MMVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5624 #define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5625 #define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5626 #define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5627 #define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5628 #define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5629 #define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5630 #define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5631 #define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5632 #define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5633 #define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5634 #define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5635 #define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5636 #define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5637 #define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5638 #define MMVM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5639 #define MMVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5640 #define MMVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5641 #define MMVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5642 #define MMVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5643 #define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5644 #define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5645 #define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5646 #define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5647 #define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5648 #define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5649 #define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5650 #define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5651 #define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5652 #define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5653 #define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5654 #define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5655 #define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5656 #define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5657 //MMVM_CONTEXT9_CNTL 5658 #define MMVM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5659 #define MMVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5660 #define MMVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5661 #define MMVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5662 #define MMVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5663 #define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5664 #define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5665 #define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5666 #define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5667 #define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5668 #define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5669 #define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5670 #define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5671 #define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5672 #define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5673 #define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5674 #define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5675 #define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5676 #define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5677 #define MMVM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5678 #define MMVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5679 #define MMVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5680 #define MMVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5681 #define MMVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5682 #define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5683 #define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5684 #define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5685 #define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5686 #define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5687 #define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5688 #define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5689 #define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5690 #define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5691 #define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5692 #define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5693 #define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5694 #define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5695 #define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5696 //MMVM_CONTEXT10_CNTL 5697 #define MMVM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5698 #define MMVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5699 #define MMVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5700 #define MMVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5701 #define MMVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5702 #define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5703 #define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5704 #define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5705 #define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5706 #define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5707 #define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5708 #define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5709 #define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5710 #define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5711 #define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5712 #define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5713 #define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5714 #define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5715 #define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5716 #define MMVM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5717 #define MMVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5718 #define MMVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5719 #define MMVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5720 #define MMVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5721 #define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5722 #define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5723 #define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5724 #define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5725 #define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5726 #define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5727 #define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5728 #define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5729 #define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5730 #define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5731 #define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5732 #define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5733 #define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5734 #define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5735 //MMVM_CONTEXT11_CNTL 5736 #define MMVM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5737 #define MMVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5738 #define MMVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5739 #define MMVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5740 #define MMVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5741 #define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5742 #define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5743 #define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5744 #define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5745 #define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5746 #define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5747 #define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5748 #define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5749 #define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5750 #define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5751 #define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5752 #define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5753 #define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5754 #define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5755 #define MMVM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5756 #define MMVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5757 #define MMVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5758 #define MMVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5759 #define MMVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5760 #define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5761 #define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5762 #define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5763 #define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5764 #define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5765 #define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5766 #define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5767 #define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5768 #define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5769 #define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5770 #define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5771 #define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5772 #define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5773 #define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5774 //MMVM_CONTEXT12_CNTL 5775 #define MMVM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5776 #define MMVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5777 #define MMVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5778 #define MMVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5779 #define MMVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5780 #define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5781 #define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5782 #define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5783 #define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5784 #define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5785 #define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5786 #define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5787 #define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5788 #define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5789 #define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5790 #define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5791 #define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5792 #define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5793 #define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5794 #define MMVM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5795 #define MMVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5796 #define MMVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5797 #define MMVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5798 #define MMVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5799 #define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5800 #define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5801 #define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5802 #define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5803 #define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5804 #define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5805 #define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5806 #define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5807 #define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5808 #define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5809 #define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5810 #define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5811 #define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5812 #define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5813 //MMVM_CONTEXT13_CNTL 5814 #define MMVM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5815 #define MMVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5816 #define MMVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5817 #define MMVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5818 #define MMVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5819 #define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5820 #define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5821 #define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5822 #define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5823 #define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5824 #define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5825 #define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5826 #define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5827 #define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5828 #define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5829 #define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5830 #define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5831 #define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5832 #define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5833 #define MMVM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5834 #define MMVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5835 #define MMVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5836 #define MMVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5837 #define MMVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5838 #define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5839 #define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5840 #define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5841 #define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5842 #define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5843 #define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5844 #define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5845 #define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5846 #define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5847 #define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5848 #define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5849 #define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5850 #define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5851 #define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5852 //MMVM_CONTEXT14_CNTL 5853 #define MMVM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5854 #define MMVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5855 #define MMVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5856 #define MMVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5857 #define MMVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5858 #define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5859 #define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5860 #define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5861 #define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5862 #define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5863 #define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5864 #define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5865 #define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5866 #define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5867 #define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5868 #define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5869 #define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5870 #define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5871 #define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5872 #define MMVM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5873 #define MMVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5874 #define MMVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5875 #define MMVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5876 #define MMVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5877 #define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5878 #define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5879 #define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5880 #define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5881 #define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5882 #define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5883 #define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5884 #define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5885 #define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5886 #define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5887 #define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5888 #define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5889 #define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5890 #define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5891 //MMVM_CONTEXT15_CNTL 5892 #define MMVM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5893 #define MMVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5894 #define MMVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5895 #define MMVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5896 #define MMVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5897 #define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5898 #define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5899 #define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5900 #define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5901 #define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5902 #define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5903 #define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5904 #define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5905 #define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5906 #define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5907 #define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5908 #define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5909 #define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5910 #define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5911 #define MMVM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5912 #define MMVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5913 #define MMVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5914 #define MMVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5915 #define MMVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5916 #define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5917 #define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5918 #define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5919 #define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5920 #define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5921 #define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5922 #define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5923 #define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5924 #define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5925 #define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5926 #define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5927 #define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5928 #define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5929 #define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5930 //MMVM_CONTEXTS_DISABLE 5931 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0 5932 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1 5933 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2 5934 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3 5935 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4 5936 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5 5937 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6 5938 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7 5939 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8 5940 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9 5941 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa 5942 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb 5943 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc 5944 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd 5945 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe 5946 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf 5947 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L 5948 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L 5949 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L 5950 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L 5951 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L 5952 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L 5953 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L 5954 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L 5955 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L 5956 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L 5957 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L 5958 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L 5959 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L 5960 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L 5961 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L 5962 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L 5963 //MMVM_INVALIDATE_ENG0_SEM 5964 #define MMVM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT 0x0 5965 #define MMVM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK 0x00000001L 5966 //MMVM_INVALIDATE_ENG1_SEM 5967 #define MMVM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT 0x0 5968 #define MMVM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK 0x00000001L 5969 //MMVM_INVALIDATE_ENG2_SEM 5970 #define MMVM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT 0x0 5971 #define MMVM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK 0x00000001L 5972 //MMVM_INVALIDATE_ENG3_SEM 5973 #define MMVM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT 0x0 5974 #define MMVM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK 0x00000001L 5975 //MMVM_INVALIDATE_ENG4_SEM 5976 #define MMVM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT 0x0 5977 #define MMVM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK 0x00000001L 5978 //MMVM_INVALIDATE_ENG5_SEM 5979 #define MMVM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT 0x0 5980 #define MMVM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK 0x00000001L 5981 //MMVM_INVALIDATE_ENG6_SEM 5982 #define MMVM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT 0x0 5983 #define MMVM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK 0x00000001L 5984 //MMVM_INVALIDATE_ENG7_SEM 5985 #define MMVM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT 0x0 5986 #define MMVM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK 0x00000001L 5987 //MMVM_INVALIDATE_ENG8_SEM 5988 #define MMVM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT 0x0 5989 #define MMVM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK 0x00000001L 5990 //MMVM_INVALIDATE_ENG9_SEM 5991 #define MMVM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT 0x0 5992 #define MMVM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK 0x00000001L 5993 //MMVM_INVALIDATE_ENG10_SEM 5994 #define MMVM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT 0x0 5995 #define MMVM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK 0x00000001L 5996 //MMVM_INVALIDATE_ENG11_SEM 5997 #define MMVM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT 0x0 5998 #define MMVM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK 0x00000001L 5999 //MMVM_INVALIDATE_ENG12_SEM 6000 #define MMVM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT 0x0 6001 #define MMVM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK 0x00000001L 6002 //MMVM_INVALIDATE_ENG13_SEM 6003 #define MMVM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT 0x0 6004 #define MMVM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK 0x00000001L 6005 //MMVM_INVALIDATE_ENG14_SEM 6006 #define MMVM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT 0x0 6007 #define MMVM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK 0x00000001L 6008 //MMVM_INVALIDATE_ENG15_SEM 6009 #define MMVM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT 0x0 6010 #define MMVM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK 0x00000001L 6011 //MMVM_INVALIDATE_ENG16_SEM 6012 #define MMVM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT 0x0 6013 #define MMVM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK 0x00000001L 6014 //MMVM_INVALIDATE_ENG17_SEM 6015 #define MMVM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT 0x0 6016 #define MMVM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK 0x00000001L 6017 //MMVM_INVALIDATE_ENG0_REQ 6018 #define MMVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6019 #define MMVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT 0x10 6020 #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6021 #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6022 #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6023 #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6024 #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6025 #define MMVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6026 #define MMVM_INVALIDATE_ENG0_REQ__LOG_REQUEST__SHIFT 0x19 6027 #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6028 #define MMVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6029 #define MMVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK 0x00070000L 6030 #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6031 #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6032 #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6033 #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6034 #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6035 #define MMVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6036 #define MMVM_INVALIDATE_ENG0_REQ__LOG_REQUEST_MASK 0x02000000L 6037 #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6038 //MMVM_INVALIDATE_ENG1_REQ 6039 #define MMVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6040 #define MMVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT 0x10 6041 #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6042 #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6043 #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6044 #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6045 #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6046 #define MMVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6047 #define MMVM_INVALIDATE_ENG1_REQ__LOG_REQUEST__SHIFT 0x19 6048 #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6049 #define MMVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6050 #define MMVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK 0x00070000L 6051 #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6052 #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6053 #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6054 #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6055 #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6056 #define MMVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6057 #define MMVM_INVALIDATE_ENG1_REQ__LOG_REQUEST_MASK 0x02000000L 6058 #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6059 //MMVM_INVALIDATE_ENG2_REQ 6060 #define MMVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6061 #define MMVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT 0x10 6062 #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6063 #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6064 #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6065 #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6066 #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6067 #define MMVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6068 #define MMVM_INVALIDATE_ENG2_REQ__LOG_REQUEST__SHIFT 0x19 6069 #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6070 #define MMVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6071 #define MMVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK 0x00070000L 6072 #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6073 #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6074 #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6075 #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6076 #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6077 #define MMVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6078 #define MMVM_INVALIDATE_ENG2_REQ__LOG_REQUEST_MASK 0x02000000L 6079 #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6080 //MMVM_INVALIDATE_ENG3_REQ 6081 #define MMVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6082 #define MMVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT 0x10 6083 #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6084 #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6085 #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6086 #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6087 #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6088 #define MMVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6089 #define MMVM_INVALIDATE_ENG3_REQ__LOG_REQUEST__SHIFT 0x19 6090 #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6091 #define MMVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6092 #define MMVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK 0x00070000L 6093 #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6094 #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6095 #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6096 #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6097 #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6098 #define MMVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6099 #define MMVM_INVALIDATE_ENG3_REQ__LOG_REQUEST_MASK 0x02000000L 6100 #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6101 //MMVM_INVALIDATE_ENG4_REQ 6102 #define MMVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6103 #define MMVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT 0x10 6104 #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6105 #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6106 #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6107 #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6108 #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6109 #define MMVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6110 #define MMVM_INVALIDATE_ENG4_REQ__LOG_REQUEST__SHIFT 0x19 6111 #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6112 #define MMVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6113 #define MMVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK 0x00070000L 6114 #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6115 #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6116 #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6117 #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6118 #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6119 #define MMVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6120 #define MMVM_INVALIDATE_ENG4_REQ__LOG_REQUEST_MASK 0x02000000L 6121 #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6122 //MMVM_INVALIDATE_ENG5_REQ 6123 #define MMVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6124 #define MMVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT 0x10 6125 #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6126 #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6127 #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6128 #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6129 #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6130 #define MMVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6131 #define MMVM_INVALIDATE_ENG5_REQ__LOG_REQUEST__SHIFT 0x19 6132 #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6133 #define MMVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6134 #define MMVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK 0x00070000L 6135 #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6136 #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6137 #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6138 #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6139 #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6140 #define MMVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6141 #define MMVM_INVALIDATE_ENG5_REQ__LOG_REQUEST_MASK 0x02000000L 6142 #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6143 //MMVM_INVALIDATE_ENG6_REQ 6144 #define MMVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6145 #define MMVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT 0x10 6146 #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6147 #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6148 #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6149 #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6150 #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6151 #define MMVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6152 #define MMVM_INVALIDATE_ENG6_REQ__LOG_REQUEST__SHIFT 0x19 6153 #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6154 #define MMVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6155 #define MMVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK 0x00070000L 6156 #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6157 #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6158 #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6159 #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6160 #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6161 #define MMVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6162 #define MMVM_INVALIDATE_ENG6_REQ__LOG_REQUEST_MASK 0x02000000L 6163 #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6164 //MMVM_INVALIDATE_ENG7_REQ 6165 #define MMVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6166 #define MMVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT 0x10 6167 #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6168 #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6169 #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6170 #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6171 #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6172 #define MMVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6173 #define MMVM_INVALIDATE_ENG7_REQ__LOG_REQUEST__SHIFT 0x19 6174 #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6175 #define MMVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6176 #define MMVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK 0x00070000L 6177 #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6178 #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6179 #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6180 #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6181 #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6182 #define MMVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6183 #define MMVM_INVALIDATE_ENG7_REQ__LOG_REQUEST_MASK 0x02000000L 6184 #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6185 //MMVM_INVALIDATE_ENG8_REQ 6186 #define MMVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6187 #define MMVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT 0x10 6188 #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6189 #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6190 #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6191 #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6192 #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6193 #define MMVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6194 #define MMVM_INVALIDATE_ENG8_REQ__LOG_REQUEST__SHIFT 0x19 6195 #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6196 #define MMVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6197 #define MMVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK 0x00070000L 6198 #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6199 #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6200 #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6201 #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6202 #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6203 #define MMVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6204 #define MMVM_INVALIDATE_ENG8_REQ__LOG_REQUEST_MASK 0x02000000L 6205 #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6206 //MMVM_INVALIDATE_ENG9_REQ 6207 #define MMVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6208 #define MMVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT 0x10 6209 #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6210 #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6211 #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6212 #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6213 #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6214 #define MMVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6215 #define MMVM_INVALIDATE_ENG9_REQ__LOG_REQUEST__SHIFT 0x19 6216 #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6217 #define MMVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6218 #define MMVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK 0x00070000L 6219 #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6220 #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6221 #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6222 #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6223 #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6224 #define MMVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6225 #define MMVM_INVALIDATE_ENG9_REQ__LOG_REQUEST_MASK 0x02000000L 6226 #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6227 //MMVM_INVALIDATE_ENG10_REQ 6228 #define MMVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6229 #define MMVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT 0x10 6230 #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6231 #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6232 #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6233 #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6234 #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6235 #define MMVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6236 #define MMVM_INVALIDATE_ENG10_REQ__LOG_REQUEST__SHIFT 0x19 6237 #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6238 #define MMVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6239 #define MMVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK 0x00070000L 6240 #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6241 #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6242 #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6243 #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6244 #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6245 #define MMVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6246 #define MMVM_INVALIDATE_ENG10_REQ__LOG_REQUEST_MASK 0x02000000L 6247 #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6248 //MMVM_INVALIDATE_ENG11_REQ 6249 #define MMVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6250 #define MMVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT 0x10 6251 #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6252 #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6253 #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6254 #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6255 #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6256 #define MMVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6257 #define MMVM_INVALIDATE_ENG11_REQ__LOG_REQUEST__SHIFT 0x19 6258 #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6259 #define MMVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6260 #define MMVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK 0x00070000L 6261 #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6262 #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6263 #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6264 #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6265 #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6266 #define MMVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6267 #define MMVM_INVALIDATE_ENG11_REQ__LOG_REQUEST_MASK 0x02000000L 6268 #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6269 //MMVM_INVALIDATE_ENG12_REQ 6270 #define MMVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6271 #define MMVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT 0x10 6272 #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6273 #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6274 #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6275 #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6276 #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6277 #define MMVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6278 #define MMVM_INVALIDATE_ENG12_REQ__LOG_REQUEST__SHIFT 0x19 6279 #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6280 #define MMVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6281 #define MMVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK 0x00070000L 6282 #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6283 #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6284 #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6285 #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6286 #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6287 #define MMVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6288 #define MMVM_INVALIDATE_ENG12_REQ__LOG_REQUEST_MASK 0x02000000L 6289 #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6290 //MMVM_INVALIDATE_ENG13_REQ 6291 #define MMVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6292 #define MMVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT 0x10 6293 #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6294 #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6295 #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6296 #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6297 #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6298 #define MMVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6299 #define MMVM_INVALIDATE_ENG13_REQ__LOG_REQUEST__SHIFT 0x19 6300 #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6301 #define MMVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6302 #define MMVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK 0x00070000L 6303 #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6304 #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6305 #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6306 #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6307 #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6308 #define MMVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6309 #define MMVM_INVALIDATE_ENG13_REQ__LOG_REQUEST_MASK 0x02000000L 6310 #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6311 //MMVM_INVALIDATE_ENG14_REQ 6312 #define MMVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6313 #define MMVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT 0x10 6314 #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6315 #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6316 #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6317 #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6318 #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6319 #define MMVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6320 #define MMVM_INVALIDATE_ENG14_REQ__LOG_REQUEST__SHIFT 0x19 6321 #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6322 #define MMVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6323 #define MMVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK 0x00070000L 6324 #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6325 #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6326 #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6327 #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6328 #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6329 #define MMVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6330 #define MMVM_INVALIDATE_ENG14_REQ__LOG_REQUEST_MASK 0x02000000L 6331 #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6332 //MMVM_INVALIDATE_ENG15_REQ 6333 #define MMVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6334 #define MMVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT 0x10 6335 #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6336 #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6337 #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6338 #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6339 #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6340 #define MMVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6341 #define MMVM_INVALIDATE_ENG15_REQ__LOG_REQUEST__SHIFT 0x19 6342 #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6343 #define MMVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6344 #define MMVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK 0x00070000L 6345 #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6346 #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6347 #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6348 #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6349 #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6350 #define MMVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6351 #define MMVM_INVALIDATE_ENG15_REQ__LOG_REQUEST_MASK 0x02000000L 6352 #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6353 //MMVM_INVALIDATE_ENG16_REQ 6354 #define MMVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6355 #define MMVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT 0x10 6356 #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6357 #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6358 #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6359 #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6360 #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6361 #define MMVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6362 #define MMVM_INVALIDATE_ENG16_REQ__LOG_REQUEST__SHIFT 0x19 6363 #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6364 #define MMVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6365 #define MMVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK 0x00070000L 6366 #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6367 #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6368 #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6369 #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6370 #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6371 #define MMVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6372 #define MMVM_INVALIDATE_ENG16_REQ__LOG_REQUEST_MASK 0x02000000L 6373 #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6374 //MMVM_INVALIDATE_ENG17_REQ 6375 #define MMVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6376 #define MMVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT 0x10 6377 #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6378 #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6379 #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6380 #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6381 #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6382 #define MMVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6383 #define MMVM_INVALIDATE_ENG17_REQ__LOG_REQUEST__SHIFT 0x19 6384 #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6385 #define MMVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6386 #define MMVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK 0x00070000L 6387 #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6388 #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6389 #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6390 #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6391 #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6392 #define MMVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6393 #define MMVM_INVALIDATE_ENG17_REQ__LOG_REQUEST_MASK 0x02000000L 6394 #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6395 //MMVM_INVALIDATE_ENG0_ACK 6396 #define MMVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6397 #define MMVM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT 0x10 6398 #define MMVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6399 #define MMVM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK 0x00010000L 6400 //MMVM_INVALIDATE_ENG1_ACK 6401 #define MMVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6402 #define MMVM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT 0x10 6403 #define MMVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6404 #define MMVM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK 0x00010000L 6405 //MMVM_INVALIDATE_ENG2_ACK 6406 #define MMVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6407 #define MMVM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT 0x10 6408 #define MMVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6409 #define MMVM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK 0x00010000L 6410 //MMVM_INVALIDATE_ENG3_ACK 6411 #define MMVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6412 #define MMVM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT 0x10 6413 #define MMVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6414 #define MMVM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK 0x00010000L 6415 //MMVM_INVALIDATE_ENG4_ACK 6416 #define MMVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6417 #define MMVM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT 0x10 6418 #define MMVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6419 #define MMVM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK 0x00010000L 6420 //MMVM_INVALIDATE_ENG5_ACK 6421 #define MMVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6422 #define MMVM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT 0x10 6423 #define MMVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6424 #define MMVM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK 0x00010000L 6425 //MMVM_INVALIDATE_ENG6_ACK 6426 #define MMVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6427 #define MMVM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT 0x10 6428 #define MMVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6429 #define MMVM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK 0x00010000L 6430 //MMVM_INVALIDATE_ENG7_ACK 6431 #define MMVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6432 #define MMVM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT 0x10 6433 #define MMVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6434 #define MMVM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK 0x00010000L 6435 //MMVM_INVALIDATE_ENG8_ACK 6436 #define MMVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6437 #define MMVM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT 0x10 6438 #define MMVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6439 #define MMVM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK 0x00010000L 6440 //MMVM_INVALIDATE_ENG9_ACK 6441 #define MMVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6442 #define MMVM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT 0x10 6443 #define MMVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6444 #define MMVM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK 0x00010000L 6445 //MMVM_INVALIDATE_ENG10_ACK 6446 #define MMVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6447 #define MMVM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT 0x10 6448 #define MMVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6449 #define MMVM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK 0x00010000L 6450 //MMVM_INVALIDATE_ENG11_ACK 6451 #define MMVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6452 #define MMVM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT 0x10 6453 #define MMVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6454 #define MMVM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK 0x00010000L 6455 //MMVM_INVALIDATE_ENG12_ACK 6456 #define MMVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6457 #define MMVM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT 0x10 6458 #define MMVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6459 #define MMVM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK 0x00010000L 6460 //MMVM_INVALIDATE_ENG13_ACK 6461 #define MMVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6462 #define MMVM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT 0x10 6463 #define MMVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6464 #define MMVM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK 0x00010000L 6465 //MMVM_INVALIDATE_ENG14_ACK 6466 #define MMVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6467 #define MMVM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT 0x10 6468 #define MMVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6469 #define MMVM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK 0x00010000L 6470 //MMVM_INVALIDATE_ENG15_ACK 6471 #define MMVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6472 #define MMVM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT 0x10 6473 #define MMVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6474 #define MMVM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK 0x00010000L 6475 //MMVM_INVALIDATE_ENG16_ACK 6476 #define MMVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6477 #define MMVM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT 0x10 6478 #define MMVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6479 #define MMVM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK 0x00010000L 6480 //MMVM_INVALIDATE_ENG17_ACK 6481 #define MMVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6482 #define MMVM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT 0x10 6483 #define MMVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6484 #define MMVM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK 0x00010000L 6485 //MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 6486 #define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6487 #define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6488 #define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6489 #define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6490 //MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 6491 #define MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6492 #define MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6493 //MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 6494 #define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6495 #define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6496 #define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6497 #define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6498 //MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 6499 #define MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6500 #define MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6501 //MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 6502 #define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6503 #define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6504 #define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6505 #define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6506 //MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 6507 #define MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6508 #define MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6509 //MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 6510 #define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6511 #define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6512 #define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6513 #define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6514 //MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 6515 #define MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6516 #define MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6517 //MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 6518 #define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6519 #define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6520 #define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6521 #define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6522 //MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 6523 #define MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6524 #define MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6525 //MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 6526 #define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6527 #define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6528 #define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6529 #define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6530 //MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 6531 #define MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6532 #define MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6533 //MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 6534 #define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6535 #define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6536 #define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6537 #define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6538 //MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 6539 #define MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6540 #define MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6541 //MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 6542 #define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6543 #define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6544 #define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6545 #define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6546 //MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 6547 #define MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6548 #define MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6549 //MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 6550 #define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6551 #define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6552 #define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6553 #define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6554 //MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 6555 #define MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6556 #define MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6557 //MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 6558 #define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6559 #define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6560 #define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6561 #define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6562 //MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 6563 #define MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6564 #define MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6565 //MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 6566 #define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6567 #define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6568 #define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6569 #define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6570 //MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 6571 #define MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6572 #define MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6573 //MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 6574 #define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6575 #define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6576 #define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6577 #define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6578 //MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 6579 #define MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6580 #define MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6581 //MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 6582 #define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6583 #define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6584 #define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6585 #define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6586 //MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 6587 #define MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6588 #define MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6589 //MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 6590 #define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6591 #define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6592 #define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6593 #define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6594 //MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 6595 #define MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6596 #define MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6597 //MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 6598 #define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6599 #define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6600 #define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6601 #define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6602 //MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 6603 #define MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6604 #define MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6605 //MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 6606 #define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6607 #define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6608 #define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6609 #define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6610 //MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 6611 #define MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6612 #define MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6613 //MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 6614 #define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6615 #define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6616 #define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6617 #define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6618 //MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 6619 #define MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6620 #define MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6621 //MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 6622 #define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6623 #define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6624 #define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6625 #define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6626 //MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 6627 #define MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6628 #define MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6629 //MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 6630 #define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6631 #define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6632 //MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 6633 #define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6634 #define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6635 //MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 6636 #define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6637 #define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6638 //MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 6639 #define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6640 #define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6641 //MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 6642 #define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6643 #define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6644 //MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 6645 #define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6646 #define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6647 //MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 6648 #define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6649 #define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6650 //MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 6651 #define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6652 #define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6653 //MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 6654 #define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6655 #define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6656 //MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 6657 #define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6658 #define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6659 //MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 6660 #define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6661 #define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6662 //MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 6663 #define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6664 #define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6665 //MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 6666 #define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6667 #define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6668 //MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 6669 #define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6670 #define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6671 //MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 6672 #define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6673 #define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6674 //MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 6675 #define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6676 #define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6677 //MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 6678 #define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6679 #define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6680 //MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 6681 #define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6682 #define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6683 //MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 6684 #define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6685 #define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6686 //MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 6687 #define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6688 #define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6689 //MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 6690 #define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6691 #define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6692 //MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 6693 #define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6694 #define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6695 //MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 6696 #define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6697 #define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6698 //MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 6699 #define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6700 #define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6701 //MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 6702 #define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6703 #define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6704 //MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 6705 #define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6706 #define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6707 //MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 6708 #define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6709 #define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6710 //MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 6711 #define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6712 #define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6713 //MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 6714 #define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6715 #define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6716 //MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 6717 #define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6718 #define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6719 //MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 6720 #define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6721 #define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6722 //MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 6723 #define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6724 #define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6725 //MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 6726 #define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6727 #define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6728 //MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 6729 #define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6730 #define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6731 //MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 6732 #define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6733 #define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6734 //MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 6735 #define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6736 #define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6737 //MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 6738 #define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6739 #define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6740 //MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 6741 #define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6742 #define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6743 //MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 6744 #define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6745 #define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6746 //MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 6747 #define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6748 #define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6749 //MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 6750 #define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6751 #define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6752 //MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 6753 #define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6754 #define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6755 //MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 6756 #define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6757 #define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6758 //MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 6759 #define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6760 #define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6761 //MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 6762 #define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6763 #define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6764 //MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 6765 #define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6766 #define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6767 //MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 6768 #define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6769 #define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6770 //MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 6771 #define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6772 #define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6773 //MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 6774 #define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6775 #define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6776 //MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 6777 #define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6778 #define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6779 //MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 6780 #define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6781 #define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6782 //MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 6783 #define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6784 #define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6785 //MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 6786 #define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6787 #define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6788 //MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 6789 #define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6790 #define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6791 //MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 6792 #define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6793 #define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6794 //MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 6795 #define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6796 #define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6797 //MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 6798 #define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6799 #define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6800 //MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 6801 #define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6802 #define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6803 //MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 6804 #define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6805 #define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6806 //MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 6807 #define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6808 #define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6809 //MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 6810 #define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6811 #define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6812 //MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 6813 #define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6814 #define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6815 //MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 6816 #define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6817 #define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6818 //MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 6819 #define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6820 #define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6821 //MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 6822 #define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6823 #define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6824 //MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 6825 #define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6826 #define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6827 //MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 6828 #define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6829 #define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6830 //MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 6831 #define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6832 #define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6833 //MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 6834 #define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6835 #define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6836 //MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 6837 #define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6838 #define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6839 //MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 6840 #define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6841 #define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6842 //MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 6843 #define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6844 #define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6845 //MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 6846 #define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6847 #define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6848 //MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 6849 #define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6850 #define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6851 //MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 6852 #define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6853 #define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6854 //MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 6855 #define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6856 #define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6857 //MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 6858 #define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6859 #define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6860 //MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 6861 #define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6862 #define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6863 //MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 6864 #define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6865 #define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6866 //MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 6867 #define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6868 #define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6869 //MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 6870 #define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6871 #define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6872 //MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 6873 #define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6874 #define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6875 //MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 6876 #define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6877 #define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6878 //MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 6879 #define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6880 #define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6881 //MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 6882 #define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6883 #define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6884 //MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 6885 #define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6886 #define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6887 //MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 6888 #define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6889 #define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6890 //MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 6891 #define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6892 #define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6893 //MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 6894 #define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6895 #define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6896 //MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 6897 #define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6898 #define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6899 //MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 6900 #define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6901 #define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6902 //MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 6903 #define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6904 #define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6905 //MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 6906 #define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6907 #define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6908 //MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 6909 #define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6910 #define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6911 //MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 6912 #define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6913 #define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6914 //MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 6915 #define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6916 #define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6917 6918 6919 // addressBlock: mmhub_mmutcl2_mmvml2pldec 6920 //MMMC_VM_L2_PERFCOUNTER0_CFG 6921 #define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 6922 #define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 6923 #define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 6924 #define MMMC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 6925 #define MMMC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 6926 #define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 6927 #define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 6928 #define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 6929 #define MMMC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 6930 #define MMMC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 6931 //MMMC_VM_L2_PERFCOUNTER1_CFG 6932 #define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 6933 #define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 6934 #define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 6935 #define MMMC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 6936 #define MMMC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 6937 #define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 6938 #define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 6939 #define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 6940 #define MMMC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 6941 #define MMMC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 6942 //MMMC_VM_L2_PERFCOUNTER2_CFG 6943 #define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 6944 #define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 6945 #define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 6946 #define MMMC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 6947 #define MMMC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 6948 #define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 6949 #define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 6950 #define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 6951 #define MMMC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 6952 #define MMMC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 6953 //MMMC_VM_L2_PERFCOUNTER3_CFG 6954 #define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 6955 #define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 6956 #define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 6957 #define MMMC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c 6958 #define MMMC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 6959 #define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL 6960 #define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L 6961 #define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L 6962 #define MMMC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L 6963 #define MMMC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L 6964 //MMMC_VM_L2_PERFCOUNTER4_CFG 6965 #define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT 0x0 6966 #define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT 0x8 6967 #define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT 0x18 6968 #define MMMC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT 0x1c 6969 #define MMMC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT 0x1d 6970 #define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK 0x000000FFL 6971 #define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK 0x0000FF00L 6972 #define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK 0x0F000000L 6973 #define MMMC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK 0x10000000L 6974 #define MMMC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK 0x20000000L 6975 //MMMC_VM_L2_PERFCOUNTER5_CFG 6976 #define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT 0x0 6977 #define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT 0x8 6978 #define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT 0x18 6979 #define MMMC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT 0x1c 6980 #define MMMC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT 0x1d 6981 #define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK 0x000000FFL 6982 #define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK 0x0000FF00L 6983 #define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK 0x0F000000L 6984 #define MMMC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK 0x10000000L 6985 #define MMMC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK 0x20000000L 6986 //MMMC_VM_L2_PERFCOUNTER6_CFG 6987 #define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT 0x0 6988 #define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT 0x8 6989 #define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT 0x18 6990 #define MMMC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT 0x1c 6991 #define MMMC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT 0x1d 6992 #define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK 0x000000FFL 6993 #define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK 0x0000FF00L 6994 #define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK 0x0F000000L 6995 #define MMMC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK 0x10000000L 6996 #define MMMC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK 0x20000000L 6997 //MMMC_VM_L2_PERFCOUNTER7_CFG 6998 #define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT 0x0 6999 #define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT 0x8 7000 #define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT 0x18 7001 #define MMMC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT 0x1c 7002 #define MMMC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT 0x1d 7003 #define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK 0x000000FFL 7004 #define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK 0x0000FF00L 7005 #define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK 0x0F000000L 7006 #define MMMC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK 0x10000000L 7007 #define MMMC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK 0x20000000L 7008 //MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL 7009 #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 7010 #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 7011 #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 7012 #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 7013 #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 7014 #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 7015 #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 7016 #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 7017 #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 7018 #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 7019 #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 7020 #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 7021 7022 7023 // addressBlock: mmhub_mmutcl2_mmvml2prdec 7024 //MMMC_VM_L2_PERFCOUNTER_LO 7025 #define MMMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 7026 #define MMMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 7027 //MMMC_VM_L2_PERFCOUNTER_HI 7028 #define MMMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 7029 #define MMMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 7030 #define MMMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 7031 #define MMMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 7032 7033 7034 // addressBlock: mmhub_mmutcl2_mmvmsharedhvdec 7035 //MMMC_VM_FB_SIZE_OFFSET_VF0 7036 #define MMMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT 0x0 7037 #define MMMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT 0x10 7038 #define MMMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK 0x0000FFFFL 7039 #define MMMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK 0xFFFF0000L 7040 //MMMC_VM_FB_SIZE_OFFSET_VF1 7041 #define MMMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT 0x0 7042 #define MMMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT 0x10 7043 #define MMMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK 0x0000FFFFL 7044 #define MMMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK 0xFFFF0000L 7045 //MMMC_VM_FB_SIZE_OFFSET_VF2 7046 #define MMMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT 0x0 7047 #define MMMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT 0x10 7048 #define MMMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK 0x0000FFFFL 7049 #define MMMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK 0xFFFF0000L 7050 //MMMC_VM_FB_SIZE_OFFSET_VF3 7051 #define MMMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT 0x0 7052 #define MMMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT 0x10 7053 #define MMMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK 0x0000FFFFL 7054 #define MMMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK 0xFFFF0000L 7055 //MMMC_VM_FB_SIZE_OFFSET_VF4 7056 #define MMMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT 0x0 7057 #define MMMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT 0x10 7058 #define MMMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK 0x0000FFFFL 7059 #define MMMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK 0xFFFF0000L 7060 //MMMC_VM_FB_SIZE_OFFSET_VF5 7061 #define MMMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT 0x0 7062 #define MMMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT 0x10 7063 #define MMMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK 0x0000FFFFL 7064 #define MMMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK 0xFFFF0000L 7065 //MMMC_VM_FB_SIZE_OFFSET_VF6 7066 #define MMMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT 0x0 7067 #define MMMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT 0x10 7068 #define MMMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK 0x0000FFFFL 7069 #define MMMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK 0xFFFF0000L 7070 //MMMC_VM_FB_SIZE_OFFSET_VF7 7071 #define MMMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT 0x0 7072 #define MMMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT 0x10 7073 #define MMMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK 0x0000FFFFL 7074 #define MMMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK 0xFFFF0000L 7075 //MMMC_VM_FB_SIZE_OFFSET_VF8 7076 #define MMMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT 0x0 7077 #define MMMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT 0x10 7078 #define MMMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK 0x0000FFFFL 7079 #define MMMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK 0xFFFF0000L 7080 //MMMC_VM_FB_SIZE_OFFSET_VF9 7081 #define MMMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT 0x0 7082 #define MMMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT 0x10 7083 #define MMMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK 0x0000FFFFL 7084 #define MMMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK 0xFFFF0000L 7085 //MMMC_VM_FB_SIZE_OFFSET_VF10 7086 #define MMMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT 0x0 7087 #define MMMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT 0x10 7088 #define MMMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK 0x0000FFFFL 7089 #define MMMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK 0xFFFF0000L 7090 //MMMC_VM_FB_SIZE_OFFSET_VF11 7091 #define MMMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT 0x0 7092 #define MMMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT 0x10 7093 #define MMMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK 0x0000FFFFL 7094 #define MMMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK 0xFFFF0000L 7095 //MMMC_VM_FB_SIZE_OFFSET_VF12 7096 #define MMMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT 0x0 7097 #define MMMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT 0x10 7098 #define MMMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK 0x0000FFFFL 7099 #define MMMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK 0xFFFF0000L 7100 //MMMC_VM_FB_SIZE_OFFSET_VF13 7101 #define MMMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT 0x0 7102 #define MMMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT 0x10 7103 #define MMMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK 0x0000FFFFL 7104 #define MMMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK 0xFFFF0000L 7105 //MMMC_VM_FB_SIZE_OFFSET_VF14 7106 #define MMMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT 0x0 7107 #define MMMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT 0x10 7108 #define MMMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK 0x0000FFFFL 7109 #define MMMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK 0xFFFF0000L 7110 //MMMC_VM_FB_SIZE_OFFSET_VF15 7111 #define MMMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT 0x0 7112 #define MMMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT 0x10 7113 #define MMMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK 0x0000FFFFL 7114 #define MMMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK 0xFFFF0000L 7115 //MMMC_VM_FB_SIZE_OFFSET_VF16 7116 #define MMMC_VM_FB_SIZE_OFFSET_VF16__VF_FB_SIZE__SHIFT 0x0 7117 #define MMMC_VM_FB_SIZE_OFFSET_VF16__VF_FB_OFFSET__SHIFT 0x10 7118 #define MMMC_VM_FB_SIZE_OFFSET_VF16__VF_FB_SIZE_MASK 0x0000FFFFL 7119 #define MMMC_VM_FB_SIZE_OFFSET_VF16__VF_FB_OFFSET_MASK 0xFFFF0000L 7120 //MMMC_VM_FB_SIZE_OFFSET_VF17 7121 #define MMMC_VM_FB_SIZE_OFFSET_VF17__VF_FB_SIZE__SHIFT 0x0 7122 #define MMMC_VM_FB_SIZE_OFFSET_VF17__VF_FB_OFFSET__SHIFT 0x10 7123 #define MMMC_VM_FB_SIZE_OFFSET_VF17__VF_FB_SIZE_MASK 0x0000FFFFL 7124 #define MMMC_VM_FB_SIZE_OFFSET_VF17__VF_FB_OFFSET_MASK 0xFFFF0000L 7125 //MMMC_VM_FB_SIZE_OFFSET_VF18 7126 #define MMMC_VM_FB_SIZE_OFFSET_VF18__VF_FB_SIZE__SHIFT 0x0 7127 #define MMMC_VM_FB_SIZE_OFFSET_VF18__VF_FB_OFFSET__SHIFT 0x10 7128 #define MMMC_VM_FB_SIZE_OFFSET_VF18__VF_FB_SIZE_MASK 0x0000FFFFL 7129 #define MMMC_VM_FB_SIZE_OFFSET_VF18__VF_FB_OFFSET_MASK 0xFFFF0000L 7130 //MMMC_VM_FB_SIZE_OFFSET_VF19 7131 #define MMMC_VM_FB_SIZE_OFFSET_VF19__VF_FB_SIZE__SHIFT 0x0 7132 #define MMMC_VM_FB_SIZE_OFFSET_VF19__VF_FB_OFFSET__SHIFT 0x10 7133 #define MMMC_VM_FB_SIZE_OFFSET_VF19__VF_FB_SIZE_MASK 0x0000FFFFL 7134 #define MMMC_VM_FB_SIZE_OFFSET_VF19__VF_FB_OFFSET_MASK 0xFFFF0000L 7135 //MMMC_VM_FB_SIZE_OFFSET_VF20 7136 #define MMMC_VM_FB_SIZE_OFFSET_VF20__VF_FB_SIZE__SHIFT 0x0 7137 #define MMMC_VM_FB_SIZE_OFFSET_VF20__VF_FB_OFFSET__SHIFT 0x10 7138 #define MMMC_VM_FB_SIZE_OFFSET_VF20__VF_FB_SIZE_MASK 0x0000FFFFL 7139 #define MMMC_VM_FB_SIZE_OFFSET_VF20__VF_FB_OFFSET_MASK 0xFFFF0000L 7140 //MMMC_VM_FB_SIZE_OFFSET_VF21 7141 #define MMMC_VM_FB_SIZE_OFFSET_VF21__VF_FB_SIZE__SHIFT 0x0 7142 #define MMMC_VM_FB_SIZE_OFFSET_VF21__VF_FB_OFFSET__SHIFT 0x10 7143 #define MMMC_VM_FB_SIZE_OFFSET_VF21__VF_FB_SIZE_MASK 0x0000FFFFL 7144 #define MMMC_VM_FB_SIZE_OFFSET_VF21__VF_FB_OFFSET_MASK 0xFFFF0000L 7145 //MMMC_VM_FB_SIZE_OFFSET_VF22 7146 #define MMMC_VM_FB_SIZE_OFFSET_VF22__VF_FB_SIZE__SHIFT 0x0 7147 #define MMMC_VM_FB_SIZE_OFFSET_VF22__VF_FB_OFFSET__SHIFT 0x10 7148 #define MMMC_VM_FB_SIZE_OFFSET_VF22__VF_FB_SIZE_MASK 0x0000FFFFL 7149 #define MMMC_VM_FB_SIZE_OFFSET_VF22__VF_FB_OFFSET_MASK 0xFFFF0000L 7150 //MMMC_VM_FB_SIZE_OFFSET_VF23 7151 #define MMMC_VM_FB_SIZE_OFFSET_VF23__VF_FB_SIZE__SHIFT 0x0 7152 #define MMMC_VM_FB_SIZE_OFFSET_VF23__VF_FB_OFFSET__SHIFT 0x10 7153 #define MMMC_VM_FB_SIZE_OFFSET_VF23__VF_FB_SIZE_MASK 0x0000FFFFL 7154 #define MMMC_VM_FB_SIZE_OFFSET_VF23__VF_FB_OFFSET_MASK 0xFFFF0000L 7155 //MMMC_VM_FB_SIZE_OFFSET_VF24 7156 #define MMMC_VM_FB_SIZE_OFFSET_VF24__VF_FB_SIZE__SHIFT 0x0 7157 #define MMMC_VM_FB_SIZE_OFFSET_VF24__VF_FB_OFFSET__SHIFT 0x10 7158 #define MMMC_VM_FB_SIZE_OFFSET_VF24__VF_FB_SIZE_MASK 0x0000FFFFL 7159 #define MMMC_VM_FB_SIZE_OFFSET_VF24__VF_FB_OFFSET_MASK 0xFFFF0000L 7160 //MMMC_VM_FB_SIZE_OFFSET_VF25 7161 #define MMMC_VM_FB_SIZE_OFFSET_VF25__VF_FB_SIZE__SHIFT 0x0 7162 #define MMMC_VM_FB_SIZE_OFFSET_VF25__VF_FB_OFFSET__SHIFT 0x10 7163 #define MMMC_VM_FB_SIZE_OFFSET_VF25__VF_FB_SIZE_MASK 0x0000FFFFL 7164 #define MMMC_VM_FB_SIZE_OFFSET_VF25__VF_FB_OFFSET_MASK 0xFFFF0000L 7165 //MMMC_VM_FB_SIZE_OFFSET_VF26 7166 #define MMMC_VM_FB_SIZE_OFFSET_VF26__VF_FB_SIZE__SHIFT 0x0 7167 #define MMMC_VM_FB_SIZE_OFFSET_VF26__VF_FB_OFFSET__SHIFT 0x10 7168 #define MMMC_VM_FB_SIZE_OFFSET_VF26__VF_FB_SIZE_MASK 0x0000FFFFL 7169 #define MMMC_VM_FB_SIZE_OFFSET_VF26__VF_FB_OFFSET_MASK 0xFFFF0000L 7170 //MMMC_VM_FB_SIZE_OFFSET_VF27 7171 #define MMMC_VM_FB_SIZE_OFFSET_VF27__VF_FB_SIZE__SHIFT 0x0 7172 #define MMMC_VM_FB_SIZE_OFFSET_VF27__VF_FB_OFFSET__SHIFT 0x10 7173 #define MMMC_VM_FB_SIZE_OFFSET_VF27__VF_FB_SIZE_MASK 0x0000FFFFL 7174 #define MMMC_VM_FB_SIZE_OFFSET_VF27__VF_FB_OFFSET_MASK 0xFFFF0000L 7175 //MMMC_VM_FB_SIZE_OFFSET_VF28 7176 #define MMMC_VM_FB_SIZE_OFFSET_VF28__VF_FB_SIZE__SHIFT 0x0 7177 #define MMMC_VM_FB_SIZE_OFFSET_VF28__VF_FB_OFFSET__SHIFT 0x10 7178 #define MMMC_VM_FB_SIZE_OFFSET_VF28__VF_FB_SIZE_MASK 0x0000FFFFL 7179 #define MMMC_VM_FB_SIZE_OFFSET_VF28__VF_FB_OFFSET_MASK 0xFFFF0000L 7180 //MMMC_VM_FB_SIZE_OFFSET_VF29 7181 #define MMMC_VM_FB_SIZE_OFFSET_VF29__VF_FB_SIZE__SHIFT 0x0 7182 #define MMMC_VM_FB_SIZE_OFFSET_VF29__VF_FB_OFFSET__SHIFT 0x10 7183 #define MMMC_VM_FB_SIZE_OFFSET_VF29__VF_FB_SIZE_MASK 0x0000FFFFL 7184 #define MMMC_VM_FB_SIZE_OFFSET_VF29__VF_FB_OFFSET_MASK 0xFFFF0000L 7185 //MMMC_VM_FB_SIZE_OFFSET_VF30 7186 #define MMMC_VM_FB_SIZE_OFFSET_VF30__VF_FB_SIZE__SHIFT 0x0 7187 #define MMMC_VM_FB_SIZE_OFFSET_VF30__VF_FB_OFFSET__SHIFT 0x10 7188 #define MMMC_VM_FB_SIZE_OFFSET_VF30__VF_FB_SIZE_MASK 0x0000FFFFL 7189 #define MMMC_VM_FB_SIZE_OFFSET_VF30__VF_FB_OFFSET_MASK 0xFFFF0000L 7190 //MMMC_VM_FB_SIZE_OFFSET_VF31 7191 #define MMMC_VM_FB_SIZE_OFFSET_VF31__VF_FB_SIZE__SHIFT 0x0 7192 #define MMMC_VM_FB_SIZE_OFFSET_VF31__VF_FB_OFFSET__SHIFT 0x10 7193 #define MMMC_VM_FB_SIZE_OFFSET_VF31__VF_FB_SIZE_MASK 0x0000FFFFL 7194 #define MMMC_VM_FB_SIZE_OFFSET_VF31__VF_FB_OFFSET_MASK 0xFFFF0000L 7195 //MMVM_IOMMU_MMIO_CNTRL_1 7196 #define MMVM_IOMMU_MMIO_CNTRL_1__MARC_EN__SHIFT 0x8 7197 #define MMVM_IOMMU_MMIO_CNTRL_1__MARC_EN_MASK 0x00000100L 7198 //MMMC_VM_MARC_BASE_LO_0 7199 #define MMMC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT 0xc 7200 #define MMMC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK 0xFFFFF000L 7201 //MMMC_VM_MARC_BASE_LO_1 7202 #define MMMC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT 0xc 7203 #define MMMC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK 0xFFFFF000L 7204 //MMMC_VM_MARC_BASE_LO_2 7205 #define MMMC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT 0xc 7206 #define MMMC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK 0xFFFFF000L 7207 //MMMC_VM_MARC_BASE_LO_3 7208 #define MMMC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT 0xc 7209 #define MMMC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK 0xFFFFF000L 7210 //MMMC_VM_MARC_BASE_HI_0 7211 #define MMMC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT 0x0 7212 #define MMMC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK 0x000FFFFFL 7213 //MMMC_VM_MARC_BASE_HI_1 7214 #define MMMC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT 0x0 7215 #define MMMC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK 0x000FFFFFL 7216 //MMMC_VM_MARC_BASE_HI_2 7217 #define MMMC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT 0x0 7218 #define MMMC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK 0x000FFFFFL 7219 //MMMC_VM_MARC_BASE_HI_3 7220 #define MMMC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT 0x0 7221 #define MMMC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK 0x000FFFFFL 7222 //MMMC_VM_MARC_RELOC_LO_0 7223 #define MMMC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT 0x0 7224 #define MMMC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT 0x1 7225 #define MMMC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT 0xc 7226 #define MMMC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK 0x00000001L 7227 #define MMMC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK 0x00000002L 7228 #define MMMC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK 0xFFFFF000L 7229 //MMMC_VM_MARC_RELOC_LO_1 7230 #define MMMC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT 0x0 7231 #define MMMC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT 0x1 7232 #define MMMC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT 0xc 7233 #define MMMC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK 0x00000001L 7234 #define MMMC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK 0x00000002L 7235 #define MMMC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK 0xFFFFF000L 7236 //MMMC_VM_MARC_RELOC_LO_2 7237 #define MMMC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT 0x0 7238 #define MMMC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT 0x1 7239 #define MMMC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT 0xc 7240 #define MMMC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK 0x00000001L 7241 #define MMMC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK 0x00000002L 7242 #define MMMC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK 0xFFFFF000L 7243 //MMMC_VM_MARC_RELOC_LO_3 7244 #define MMMC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT 0x0 7245 #define MMMC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT 0x1 7246 #define MMMC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT 0xc 7247 #define MMMC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK 0x00000001L 7248 #define MMMC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK 0x00000002L 7249 #define MMMC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK 0xFFFFF000L 7250 //MMMC_VM_MARC_RELOC_HI_0 7251 #define MMMC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT 0x0 7252 #define MMMC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK 0x000FFFFFL 7253 //MMMC_VM_MARC_RELOC_HI_1 7254 #define MMMC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT 0x0 7255 #define MMMC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK 0x000FFFFFL 7256 //MMMC_VM_MARC_RELOC_HI_2 7257 #define MMMC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT 0x0 7258 #define MMMC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK 0x000FFFFFL 7259 //MMMC_VM_MARC_RELOC_HI_3 7260 #define MMMC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT 0x0 7261 #define MMMC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK 0x000FFFFFL 7262 //MMMC_VM_MARC_LEN_LO_0 7263 #define MMMC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT 0xc 7264 #define MMMC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK 0xFFFFF000L 7265 //MMMC_VM_MARC_LEN_LO_1 7266 #define MMMC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT 0xc 7267 #define MMMC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK 0xFFFFF000L 7268 //MMMC_VM_MARC_LEN_LO_2 7269 #define MMMC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT 0xc 7270 #define MMMC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK 0xFFFFF000L 7271 //MMMC_VM_MARC_LEN_LO_3 7272 #define MMMC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT 0xc 7273 #define MMMC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK 0xFFFFF000L 7274 //MMMC_VM_MARC_LEN_HI_0 7275 #define MMMC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT 0x0 7276 #define MMMC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK 0x000FFFFFL 7277 //MMMC_VM_MARC_LEN_HI_1 7278 #define MMMC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT 0x0 7279 #define MMMC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK 0x000FFFFFL 7280 //MMMC_VM_MARC_LEN_HI_2 7281 #define MMMC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT 0x0 7282 #define MMMC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK 0x000FFFFFL 7283 //MMMC_VM_MARC_LEN_HI_3 7284 #define MMMC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT 0x0 7285 #define MMMC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK 0x000FFFFFL 7286 //MMVM_IOMMU_CONTROL_REGISTER 7287 #define MMVM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT 0x0 7288 #define MMVM_IOMMU_CONTROL_REGISTER__IOMMUEN_MASK 0x00000001L 7289 //MMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER 7290 #define MMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN__SHIFT 0xd 7291 #define MMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN_MASK 0x00002000L 7292 //MMVM_PCIE_ATS_CNTL 7293 #define MMVM_PCIE_ATS_CNTL__STU__SHIFT 0x10 7294 #define MMVM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0x1f 7295 #define MMVM_PCIE_ATS_CNTL__STU_MASK 0x001F0000L 7296 #define MMVM_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x80000000L 7297 //MMVM_PCIE_ATS_CNTL_VF_0 7298 #define MMVM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT 0x1f 7299 #define MMVM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK 0x80000000L 7300 //MMVM_PCIE_ATS_CNTL_VF_1 7301 #define MMVM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT 0x1f 7302 #define MMVM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK 0x80000000L 7303 //MMVM_PCIE_ATS_CNTL_VF_2 7304 #define MMVM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT 0x1f 7305 #define MMVM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK 0x80000000L 7306 //MMVM_PCIE_ATS_CNTL_VF_3 7307 #define MMVM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT 0x1f 7308 #define MMVM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK 0x80000000L 7309 //MMVM_PCIE_ATS_CNTL_VF_4 7310 #define MMVM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT 0x1f 7311 #define MMVM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK 0x80000000L 7312 //MMVM_PCIE_ATS_CNTL_VF_5 7313 #define MMVM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT 0x1f 7314 #define MMVM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK 0x80000000L 7315 //MMVM_PCIE_ATS_CNTL_VF_6 7316 #define MMVM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT 0x1f 7317 #define MMVM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK 0x80000000L 7318 //MMVM_PCIE_ATS_CNTL_VF_7 7319 #define MMVM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT 0x1f 7320 #define MMVM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK 0x80000000L 7321 //MMVM_PCIE_ATS_CNTL_VF_8 7322 #define MMVM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT 0x1f 7323 #define MMVM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK 0x80000000L 7324 //MMVM_PCIE_ATS_CNTL_VF_9 7325 #define MMVM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT 0x1f 7326 #define MMVM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK 0x80000000L 7327 //MMVM_PCIE_ATS_CNTL_VF_10 7328 #define MMVM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT 0x1f 7329 #define MMVM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK 0x80000000L 7330 //MMVM_PCIE_ATS_CNTL_VF_11 7331 #define MMVM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT 0x1f 7332 #define MMVM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK 0x80000000L 7333 //MMVM_PCIE_ATS_CNTL_VF_12 7334 #define MMVM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT 0x1f 7335 #define MMVM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK 0x80000000L 7336 //MMVM_PCIE_ATS_CNTL_VF_13 7337 #define MMVM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT 0x1f 7338 #define MMVM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK 0x80000000L 7339 //MMVM_PCIE_ATS_CNTL_VF_14 7340 #define MMVM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT 0x1f 7341 #define MMVM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK 0x80000000L 7342 //MMVM_PCIE_ATS_CNTL_VF_15 7343 #define MMVM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT 0x1f 7344 #define MMVM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK 0x80000000L 7345 //MMVM_PCIE_ATS_CNTL_VF_16 7346 #define MMVM_PCIE_ATS_CNTL_VF_16__ATC_ENABLE__SHIFT 0x1f 7347 #define MMVM_PCIE_ATS_CNTL_VF_16__ATC_ENABLE_MASK 0x80000000L 7348 //MMVM_PCIE_ATS_CNTL_VF_17 7349 #define MMVM_PCIE_ATS_CNTL_VF_17__ATC_ENABLE__SHIFT 0x1f 7350 #define MMVM_PCIE_ATS_CNTL_VF_17__ATC_ENABLE_MASK 0x80000000L 7351 //MMVM_PCIE_ATS_CNTL_VF_18 7352 #define MMVM_PCIE_ATS_CNTL_VF_18__ATC_ENABLE__SHIFT 0x1f 7353 #define MMVM_PCIE_ATS_CNTL_VF_18__ATC_ENABLE_MASK 0x80000000L 7354 //MMVM_PCIE_ATS_CNTL_VF_19 7355 #define MMVM_PCIE_ATS_CNTL_VF_19__ATC_ENABLE__SHIFT 0x1f 7356 #define MMVM_PCIE_ATS_CNTL_VF_19__ATC_ENABLE_MASK 0x80000000L 7357 //MMVM_PCIE_ATS_CNTL_VF_20 7358 #define MMVM_PCIE_ATS_CNTL_VF_20__ATC_ENABLE__SHIFT 0x1f 7359 #define MMVM_PCIE_ATS_CNTL_VF_20__ATC_ENABLE_MASK 0x80000000L 7360 //MMVM_PCIE_ATS_CNTL_VF_21 7361 #define MMVM_PCIE_ATS_CNTL_VF_21__ATC_ENABLE__SHIFT 0x1f 7362 #define MMVM_PCIE_ATS_CNTL_VF_21__ATC_ENABLE_MASK 0x80000000L 7363 //MMVM_PCIE_ATS_CNTL_VF_22 7364 #define MMVM_PCIE_ATS_CNTL_VF_22__ATC_ENABLE__SHIFT 0x1f 7365 #define MMVM_PCIE_ATS_CNTL_VF_22__ATC_ENABLE_MASK 0x80000000L 7366 //MMVM_PCIE_ATS_CNTL_VF_23 7367 #define MMVM_PCIE_ATS_CNTL_VF_23__ATC_ENABLE__SHIFT 0x1f 7368 #define MMVM_PCIE_ATS_CNTL_VF_23__ATC_ENABLE_MASK 0x80000000L 7369 //MMVM_PCIE_ATS_CNTL_VF_24 7370 #define MMVM_PCIE_ATS_CNTL_VF_24__ATC_ENABLE__SHIFT 0x1f 7371 #define MMVM_PCIE_ATS_CNTL_VF_24__ATC_ENABLE_MASK 0x80000000L 7372 //MMVM_PCIE_ATS_CNTL_VF_25 7373 #define MMVM_PCIE_ATS_CNTL_VF_25__ATC_ENABLE__SHIFT 0x1f 7374 #define MMVM_PCIE_ATS_CNTL_VF_25__ATC_ENABLE_MASK 0x80000000L 7375 //MMVM_PCIE_ATS_CNTL_VF_26 7376 #define MMVM_PCIE_ATS_CNTL_VF_26__ATC_ENABLE__SHIFT 0x1f 7377 #define MMVM_PCIE_ATS_CNTL_VF_26__ATC_ENABLE_MASK 0x80000000L 7378 //MMVM_PCIE_ATS_CNTL_VF_27 7379 #define MMVM_PCIE_ATS_CNTL_VF_27__ATC_ENABLE__SHIFT 0x1f 7380 #define MMVM_PCIE_ATS_CNTL_VF_27__ATC_ENABLE_MASK 0x80000000L 7381 //MMVM_PCIE_ATS_CNTL_VF_28 7382 #define MMVM_PCIE_ATS_CNTL_VF_28__ATC_ENABLE__SHIFT 0x1f 7383 #define MMVM_PCIE_ATS_CNTL_VF_28__ATC_ENABLE_MASK 0x80000000L 7384 //MMVM_PCIE_ATS_CNTL_VF_29 7385 #define MMVM_PCIE_ATS_CNTL_VF_29__ATC_ENABLE__SHIFT 0x1f 7386 #define MMVM_PCIE_ATS_CNTL_VF_29__ATC_ENABLE_MASK 0x80000000L 7387 //MMVM_PCIE_ATS_CNTL_VF_30 7388 #define MMVM_PCIE_ATS_CNTL_VF_30__ATC_ENABLE__SHIFT 0x1f 7389 #define MMVM_PCIE_ATS_CNTL_VF_30__ATC_ENABLE_MASK 0x80000000L 7390 //MMVM_PCIE_ATS_CNTL_VF_31 7391 #define MMVM_PCIE_ATS_CNTL_VF_31__ATC_ENABLE__SHIFT 0x1f 7392 #define MMVM_PCIE_ATS_CNTL_VF_31__ATC_ENABLE_MASK 0x80000000L 7393 //MMUTCL2_CGTT_CLK_CTRL 7394 #define MMUTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 7395 #define MMUTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 7396 #define MMUTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA__SHIFT 0xc 7397 #define MMUTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf 7398 #define MMUTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 7399 #define MMUTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 7400 #define MMUTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 7401 #define MMUTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 7402 #define MMUTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA_MASK 0x00007000L 7403 #define MMUTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L 7404 #define MMUTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L 7405 #define MMUTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L 7406 //MMMC_SHARED_ACTIVE_FCN_ID 7407 #define MMMC_SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x0 7408 #define MMMC_SHARED_ACTIVE_FCN_ID__VF__SHIFT 0x1f 7409 #define MMMC_SHARED_ACTIVE_FCN_ID__VFID_MASK 0x0000001FL 7410 #define MMMC_SHARED_ACTIVE_FCN_ID__VF_MASK 0x80000000L 7411 7412 7413 // addressBlock: mmhub_mmutcl2_mmvmsharedpfdec 7414 //MMMC_VM_NB_MMIOBASE 7415 #define MMMC_VM_NB_MMIOBASE__MMIOBASE__SHIFT 0x0 7416 #define MMMC_VM_NB_MMIOBASE__MMIOBASE_MASK 0xFFFFFFFFL 7417 //MMMC_VM_NB_MMIOLIMIT 7418 #define MMMC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT 0x0 7419 #define MMMC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK 0xFFFFFFFFL 7420 //MMMC_VM_NB_PCI_CTRL 7421 #define MMMC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT 0x17 7422 #define MMMC_VM_NB_PCI_CTRL__MMIOENABLE_MASK 0x00800000L 7423 //MMMC_VM_NB_PCI_ARB 7424 #define MMMC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT 0x3 7425 #define MMMC_VM_NB_PCI_ARB__VGA_HOLE_MASK 0x00000008L 7426 //MMMC_VM_NB_TOP_OF_DRAM_SLOT1 7427 #define MMMC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT 0x17 7428 #define MMMC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK 0xFF800000L 7429 //MMMC_VM_NB_LOWER_TOP_OF_DRAM2 7430 #define MMMC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT 0x0 7431 #define MMMC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT 0x17 7432 #define MMMC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK 0x00000001L 7433 #define MMMC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK 0xFF800000L 7434 //MMMC_VM_NB_UPPER_TOP_OF_DRAM2 7435 #define MMMC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT 0x0 7436 #define MMMC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK 0x00000FFFL 7437 //MMMC_VM_FB_OFFSET 7438 #define MMMC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0 7439 #define MMMC_VM_FB_OFFSET__FB_OFFSET_MASK 0x00FFFFFFL 7440 //MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 7441 #define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT 0x0 7442 #define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK 0xFFFFFFFFL 7443 //MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 7444 #define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT 0x0 7445 #define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK 0x0000000FL 7446 //MMMC_VM_STEERING 7447 #define MMMC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0 7448 #define MMMC_VM_STEERING__DEFAULT_STEERING_MASK 0x00000003L 7449 //MMMC_SHARED_VIRT_RESET_REQ 7450 #define MMMC_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0 7451 #define MMMC_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f 7452 #define MMMC_SHARED_VIRT_RESET_REQ__VF_MASK 0x7FFFFFFFL 7453 #define MMMC_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L 7454 //MMMC_MEM_POWER_LS 7455 #define MMMC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 7456 #define MMMC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 7457 #define MMMC_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL 7458 #define MMMC_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L 7459 //MMMC_VM_CACHEABLE_DRAM_ADDRESS_START 7460 #define MMMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT 0x0 7461 #define MMMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL 7462 //MMMC_VM_CACHEABLE_DRAM_ADDRESS_END 7463 #define MMMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT 0x0 7464 #define MMMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL 7465 //MMMC_VM_APT_CNTL 7466 #define MMMC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT 0x0 7467 #define MMMC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT 0x1 7468 #define MMMC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK 0x00000001L 7469 #define MMMC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK 0x00000002L 7470 //MMMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 7471 #define MMMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT 0x0 7472 #define MMMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK 0x00000001L 7473 //MMMC_VM_LOCAL_HBM_ADDRESS_START 7474 #define MMMC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS__SHIFT 0x0 7475 #define MMMC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL 7476 //MMMC_VM_LOCAL_HBM_ADDRESS_END 7477 #define MMMC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS__SHIFT 0x0 7478 #define MMMC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL 7479 //MMMC_SHARED_VIRT_RESET_REQ2 7480 #define MMMC_SHARED_VIRT_RESET_REQ2__VF__SHIFT 0x0 7481 #define MMMC_SHARED_VIRT_RESET_REQ2__VF_MASK 0x00000001L 7482 7483 7484 // addressBlock: mmhub_mmutcl2_mmvmsharedvcdec 7485 //MMMC_VM_FB_LOCATION_BASE 7486 #define MMMC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0 7487 #define MMMC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x00FFFFFFL 7488 //MMMC_VM_FB_LOCATION_TOP 7489 #define MMMC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT 0x0 7490 #define MMMC_VM_FB_LOCATION_TOP__FB_TOP_MASK 0x00FFFFFFL 7491 //MMMC_VM_AGP_TOP 7492 #define MMMC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0 7493 #define MMMC_VM_AGP_TOP__AGP_TOP_MASK 0x00FFFFFFL 7494 //MMMC_VM_AGP_BOT 7495 #define MMMC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0 7496 #define MMMC_VM_AGP_BOT__AGP_BOT_MASK 0x00FFFFFFL 7497 //MMMC_VM_AGP_BASE 7498 #define MMMC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0 7499 #define MMMC_VM_AGP_BASE__AGP_BASE_MASK 0x00FFFFFFL 7500 //MMMC_VM_SYSTEM_APERTURE_LOW_ADDR 7501 #define MMMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT 0x0 7502 #define MMMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL 7503 //MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR 7504 #define MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT 0x0 7505 #define MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL 7506 //MMMC_VM_MX_L1_TLB_CNTL 7507 #define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 7508 #define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 7509 #define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 7510 #define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 7511 #define MMMC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7 7512 #define MMMC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT 0xb 7513 #define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L 7514 #define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L 7515 #define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L 7516 #define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L 7517 #define MMMC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x00000780L 7518 #define MMMC_VM_MX_L1_TLB_CNTL__MTYPE_MASK 0x00003800L 7519 7520 7521 // addressBlock: mmhub_mmutcl2_mmatcl2pfcntrdec 7522 //MM_ATC_L2_PERFCOUNTER_LO 7523 #define MM_ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 7524 #define MM_ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 7525 //MM_ATC_L2_PERFCOUNTER_HI 7526 #define MM_ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 7527 #define MM_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 7528 #define MM_ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 7529 #define MM_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 7530 7531 7532 // addressBlock: mmhub_mmutcl2_mmatcl2pfcntldec 7533 //MM_ATC_L2_PERFCOUNTER0_CFG 7534 #define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 7535 #define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 7536 #define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 7537 #define MM_ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 7538 #define MM_ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 7539 #define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 7540 #define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 7541 #define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 7542 #define MM_ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 7543 #define MM_ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 7544 //MM_ATC_L2_PERFCOUNTER1_CFG 7545 #define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 7546 #define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 7547 #define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 7548 #define MM_ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 7549 #define MM_ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 7550 #define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 7551 #define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 7552 #define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 7553 #define MM_ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 7554 #define MM_ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 7555 //MM_ATC_L2_PERFCOUNTER_RSLT_CNTL 7556 #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 7557 #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 7558 #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 7559 #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 7560 #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 7561 #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 7562 #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 7563 #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 7564 #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 7565 #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 7566 #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 7567 #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 7568 7569 #endif 7570
Indexes created Wed Sep 24 02:09:48 GMT 2025