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    Searched defs:MO2 (Results 1 - 8 of 8) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/
ARMInstPrinter.cpp 102 const MCOperand &MO2 = MI->getOperand(2);
115 printRegName(O, MO2.getReg());
125 const MCOperand &MO2 = MI->getOperand(2);
127 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()));
136 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) {
142 << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm())) << markup(">");
385 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
397 printRegName(O, MO2.getReg());
405 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
410 printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm())
    [all...]
ARMMCCodeEmitter.cpp 931 const MCOperand &MO2 = MI.getOperand(OpIdx + 1);
933 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO2.getReg());
1253 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
1256 unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm());
1257 bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add;
1258 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm());
1347 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
1362 unsigned Imm = MO2.getImm();
1510 const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
1511 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm())
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/MCTargetDesc/
MSP430MCCodeEmitter.cpp 127 const MCOperand &MO2 = MI.getOperand(Op + 1);
128 if (MO2.isImm()) {
130 return ((unsigned)MO2.getImm() << 4) | Reg;
133 assert(MO2.isExpr() && "Expr operand expected");
146 Fixups.push_back(MCFixup::create(Offset, MO2.getExpr(),
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonAsmPrinter.cpp 452 MCOperand &MO2 = MappedInst.getOperand(2);
453 MCExpr const *Expr = MO2.getExpr();
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86RegisterInfo.cpp 902 MachineOperand &MO2 = MI->getOperand(2);
903 ShapeT Shape(&MO1, &MO2, MRI);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/AsmParser/
HexagonAsmParser.cpp 1235 MCOperand &MO2) {
1240 TmpInst.addOperand(MO2);
1597 MCOperand &MO2 = Inst.getOperand(2);
1599 if (MO2.getExpr()->evaluateAsAbsolute(Value)) {
1604 Inst = makeCombineInst(Hexagon::A2_combineii, Rdd, MO1, MO2);
1618 MCOperand &MO2 = Inst.getOperand(2);
1619 Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, MO1, MO2);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIInstrInfo.cpp 410 auto MO2 = *MI2.memoperands_begin();
411 if (MO1->getAddrSpace() != MO2->getAddrSpace())
415 auto Base2 = MO2->getValue();
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
LegalizerHelper.cpp 1118 MachineOperand &MO2 = MI.getOperand(0);
1121 MIRBuilder.buildSExt(MO2, DstExt);
1122 MO2.setReg(DstExt);

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