1 /* $NetBSD: pca9685reg.h,v 1.1 2019/07/24 05:25:32 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Jason R. Thorpe 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #ifndef pca9685reg_h_included 30 #define pca9685reg_h_included 31 32 /* 33 * Hardware definitions for the NXP PCA9685 16-channel, 12-bit PWM FM+ 34 * I2C-bus LED controller. 35 */ 36 37 #define PCA9685_NCHANNELS 16 38 39 /* 40 * PCA9685 i2c addresses. 41 */ 42 /* Default all-call address. */ 43 #define PCA9685_I2CADDR_ALLCALL_DEFAULT 0x70 44 45 /* Default sub-addresses. */ 46 #define PCA9685_I2CADDR_SUBADR1_DEFAULT 0x71 47 #define PCA9685_I2CADDR_SUBADR2_DEFAULT 0x72 48 #define PCA9685_I2CADDR_SUBADR3_DEFAULT 0x74 49 50 /* 51 * The PCA9685 has 6 address select pins, which must be 52 * pulled up or down to select the device's address. The 53 * selected slave address is: 54 * 55 * 1 A5 A4 A3 A2 A1 A0 56 * 57 * There are some addresses, however, that cannot be selected 58 * even if they fall into the selectable range: 59 * 60 * - Default all-call address (0x70) 61 * - 10-bit slave address prefix (0x78) 62 * - Reserved for future purposes address (0x7c) 63 * 64 * Use of sub-addresses to control groups of devices also limits 65 * the available individual slave addresses. 66 */ 67 #define PCA9685_I2CADDR_MIN 0x40 68 #define PCA9685_I2CADDR_MAX 0x7f 69 70 #define PCA9685_I2CADDR_BLACKLIST { 0x78, 0x7c } 71 72 /* 73 * PCA9685 has an internal 25MHz oscillator. The maximum external 74 * reference clock frequency is 50MHz. 75 */ 76 #define PCA9685_INTERNAL_FREQ 25000000 77 #define PCA9685_EXTERNAL_FREQ_MAX 50000000 78 79 /* 80 * Data sheet sez: 81 * 82 * Maximum PWM frequency is 1526Hz -- prescale == 0x03. 83 * Minimum PWM frequency is 24Hz -- prescale == 0xff. 84 */ 85 #define PCA9685_FREQ_MIN 24 86 #define PCA9685_FREQ_MAX 1526 87 88 #define PCA9685_PRESCALE_MIN 0x03 89 #define PCA9685_PRESCALE_MAX 0xff 90 91 /* 92 * The PCA9685 pulse counter has a 12-bit resolution (4096 ticks). 93 */ 94 #define PCA9685_PWM_TICKS 4096 95 96 /* 97 * PCA9685 register definitions. 98 */ 99 100 /* Mode register 1 */ 101 #define PCA9685_MODE1 0x00 102 #define MODE1_ALLCALL 0x01 /* responds to LED All Call address */ 103 #define MODE1_SUB3 0x02 /* responds to subaddress 3 */ 104 #define MODE1_SUB2 0x04 /* responds to subaddress 2 */ 105 #define MODE1_SUB1 0x08 /* responds to subaddress 1 */ 106 #define MODE1_SLEEP 0x10 /* 1 = low power mode, oscillator off */ 107 #define MODE1_AI 0x20 /* register auto-increment enabled */ 108 #define MODE1_EXTCLK 0x40 /* external oscillatior enable */ 109 #define MODE1_RESTART 0x80 /* restart enabled */ 110 111 /* Mode register 2 */ 112 #define PCA9685_MODE2 0x01 113 #define MODE2_OUTNE_MASK 0x03 /* see data sheet */ 114 #define MODE2_OUTDRV 0x04 /* 0 = open-drain, 1 = totem pole */ 115 #define MODE2_OCH 0x08 /* outputs change: 0 = STOP, 1 = ACK */ 116 #define MODE2_INVRT 0x10 /* Output logic state inverted */ 117 118 /* I2C subaddress 1 */ 119 #define PCA9685_SUBADR1 0x02 120 121 /* I2C subaddress 2 */ 122 #define PCA9685_SUBADR2 0x03 123 124 /* I2C subaddress 3 */ 125 #define PCA9685_SUBADR3 0x04 126 127 /* LED All Call address */ 128 #define PCA9685_ALLCALLADR 0x05 129 130 /* LEDx output and brightness control byte 0 */ 131 #define PCA9685_LEDx_ON_L(x) (0x06 + ((x) * 4)) 132 133 /* LEDx output and brightness control byte 1 */ 134 #define PCA9685_LEDx_ON_H(x) (0x07 + ((x) * 4)) 135 136 /* LEDx output and brightness control byte 2 */ 137 #define PCA9685_LEDx_OFF_L(x) (0x08 + ((x) * 4)) 138 139 /* LEDx output and brightness control byte 3 */ 140 #define PCA9685_LEDx_OFF_H(x) (0x09 + ((x) * 4)) 141 142 /* Load all LEDx_ON registers byte 0 */ 143 #define PCA9685_ALL_LED_ON_L 0xfa 144 145 /* Load all LEDx_ON registers byte 1 */ 146 #define PCA9685_ALL_LED_ON_H 0xfb 147 148 /* Load all LEDx_OFF registers byte 0 */ 149 #define PCA9685_ALL_LED_OFF_L 0xfc 150 151 /* Load all LEDx_OFF registers byte 1 */ 152 #define PCA9685_ALL_LED_OFF_H 0xfd 153 154 /* Prescaler for PWM output frequency */ 155 #define PCA9685_PRE_SCALE 0xfe 156 157 /* Test mode */ 158 #define PCA9685_TEST_MODE 0xff 159 160 #endif /* pca9685reg_h_included */ 161
Indexes created Wed Sep 24 05:09:52 GMT 2025