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      1 /*	$NetBSD: zynq_uartreg.h,v 1.1 2019/06/11 13:01:48 skrll Exp $	*/
      2 /*-
      3  * Copyright (c) 2015  Genetec Corporation.  All rights reserved.
      4  * Written by Hashimoto Kenichi for Genetec Corporation.
      5  *
      6  * Redistribution and use in source and binary forms, with or without
      7  * modification, are permitted provided that the following conditions
      8  * are met:
      9  * 1. Redistributions of source code must retain the above copyright
     10  *    notice, this list of conditions and the following disclaimer.
     11  * 2. Redistributions in binary form must reproduce the above copyright
     12  *    notice, this list of conditions and the following disclaimer in the
     13  *    documentation and/or other materials provided with the distribution.
     14  *
     15  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     16  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     17  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     18  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     19  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     20  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     21  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     22  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     23  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     24  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     25  * POSSIBILITY OF SUCH DAMAGE.
     26  */
     27 
     28 #ifndef	_ARM_XILINX_ZYNQ_UARTREG_H
     29 #define	_ARM_XILINX_ZYNQ_UARTREG_H
     30 
     31 /* register offset address */
     32 #define UART_CONTROL		0x00000000	/* UART Control Register */
     33 #define  CR_STPBRK		__BIT(8)
     34 #define  CR_STTBRK		__BIT(7)
     35 #define  CR_RSTTO		__BIT(6)
     36 #define  CR_TXDIS		__BIT(5)
     37 #define  CR_TXEN		__BIT(4)
     38 #define  CR_RXDIS		__BIT(3)
     39 #define  CR_RXEN		__BIT(2)
     40 #define  CR_TXRES		__BIT(1)
     41 #define  CR_RXRES		__BIT(0)
     42 #define UART_MODE		0x00000004	/* UART Mode Register */
     43 #define  MR_CHMODE		__BITS(9, 8)
     44 #define  MR_NBSTOP		__BITS(7, 6)
     45 #define   NBSTOP_1		__SHIFTIN(0, MR_NBSTOP)
     46 #define   NBSTOP_15		__SHIFTIN(1, MR_NBSTOP)
     47 #define   NBSTOP_2		__SHIFTIN(2, MR_NBSTOP)
     48 #define  MR_PAR			__BITS(5, 3)
     49 #define   PAR_EVEN		__SHIFTIN(0, MR_PAR)
     50 #define   PAR_ODD		__SHIFTIN(1, MR_PAR)
     51 #define   PAR_ZERO		__SHIFTIN(2, MR_PAR)
     52 #define   PAR_ONE		__SHIFTIN(3, MR_PAR)
     53 #define   PAR_NONE		__SHIFTIN(4, MR_PAR)
     54 #define  MR_CHRL		__BITS(2, 1)
     55 #define   CHRL_6BIT		__SHIFTIN(3, MR_CHRL)
     56 #define   CHRL_7BIT		__SHIFTIN(2, MR_CHRL)
     57 #define   CHRL_8BIT		__SHIFTIN(1, MR_CHRL)
     58 #define  MR_CLKS		__BIT(0)
     59 #define UART_INTRPT_EN		0x00000008	/* Interrupt Enable Register */
     60 #define UART_INTRPT_DIS		0x0000000C	/* Interrupt Disable Register */
     61 #define UART_INTRPT_MASK	0x00000010	/* Interrupt Mask Register */
     62 #define UART_CHNL_INT_STS	0x00000014	/* Channel Interrupt Status Register */
     63 #define  INT_TOVR		__BIT(12)
     64 #define  INT_TNFUL		__BIT(11)
     65 #define  INT_TTRIG		__BIT(10)
     66 #define  INT_DMSI		__BIT(9)
     67 #define  INT_TIMEOUT		__BIT(8)
     68 #define  INT_PARE		__BIT(7)
     69 #define  INT_FRAME		__BIT(6)
     70 #define  INT_ROVR		__BIT(5)
     71 #define  INT_TFUL		__BIT(4)
     72 #define  INT_TEMPTY		__BIT(3)
     73 #define  INT_RFUL		__BIT(2)
     74 #define  INT_REMPTY		__BIT(1)
     75 #define  INT_RTRIG		__BIT(0)
     76 #define UART_BAUD_RATE_GEN	0x00000018	/* Baud Rate Generator Register. */
     77 #define UART_RCVR_TIMEOUT	0x0000001C	/* Receiver Timeout Register */
     78 #define UART_RCVR_FIFO_TRIGGER	0x00000020	/* Receiver FIFO Trigger Level Register */
     79 #define UART_MODEM_CTRL		0x00000024	/* Modem Control Register */
     80 #define  MODEMCR_FCM		__BIT(5)
     81 #define  MODEMCR_RTS		__BIT(1)
     82 #define  MODEMCR_DTR		__BIT(0)
     83 #define UART_MODEM_STS		0x00000028	/* Modem Status Register */
     84 #define  MODEMSR_FCMS		__BIT(8)
     85 #define  MODEMSR_DCD		__BIT(7)
     86 #define  MODEMSR_RI		__BIT(6)
     87 #define  MODEMSR_DSR		__BIT(5)
     88 #define  MODEMSR_CTS		__BIT(4)
     89 #define  MODEMSR_DDCD		__BIT(3)
     90 #define  MODEMSR_TERI		__BIT(2)
     91 #define  MODEMSR_DDSR		__BIT(1)
     92 #define  MODEMSR_DCTS		__BIT(0)
     93 #define UART_CHANNEL_STS	0x0000002C	/* Channel Status Register */
     94 #define  STS_TNFUL		__BIT(14)
     95 #define  STS_TTRIG		__BIT(13)
     96 #define  STS_FDELT		__BIT(12)
     97 #define  STS_TAVTIVE		__BIT(11)
     98 #define  STS_RACTIVE		__BIT(10)
     99 #define  STS_TFUL		__BIT(4)
    100 #define  STS_TEMPTY		__BIT(3)
    101 #define  STS_RFUL		__BIT(2)
    102 #define  STS_REMPTY		__BIT(1)
    103 #define  STS_RTRIG		__BIT(0)
    104 #define UART_TX_RX_FIFO		0x00000030	/* Transmit and Receive FIFO */
    105 #define UART_BAUD_RATE_DIVIDER	0x00000034	/* Baud Rate Divider Register */
    106 #define UART_FLOW_DELAY		0x00000038	/* Flow Control Delay Register */
    107 #define UART_TX_FIFO_TRIGGER	0x00000044	/* Transmitter FIFO Trigger */
    108 
    109 #endif /* _ARM_XILINX_ZYNQ_UARTREG_H */
    110 
    111