1 /* $NetBSD: rv730d.h,v 1.4 2021/12/18 23:45:43 riastradh Exp $ */ 2 3 /* 4 * Copyright 2011 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 #ifndef RV730_H 26 #define RV730_H 27 28 #define CG_SPLL_FUNC_CNTL 0x600 29 #define SPLL_RESET (1 << 0) 30 #define SPLL_SLEEP (1 << 1) 31 #define SPLL_DIVEN (1 << 2) 32 #define SPLL_BYPASS_EN (1 << 3) 33 #define SPLL_REF_DIV(x) ((x) << 4) 34 #define SPLL_REF_DIV_MASK (0x3f << 4) 35 #define SPLL_HILEN(x) ((x) << 12) 36 #define SPLL_HILEN_MASK (0xf << 12) 37 #define SPLL_LOLEN(x) ((x) << 16) 38 #define SPLL_LOLEN_MASK (0xf << 16) 39 #define CG_SPLL_FUNC_CNTL_2 0x604 40 #define SCLK_MUX_SEL(x) ((x) << 0) 41 #define SCLK_MUX_SEL_MASK (0x1ff << 0) 42 #define CG_SPLL_FUNC_CNTL_3 0x608 43 #define SPLL_FB_DIV(x) ((x) << 0) 44 #define SPLL_FB_DIV_MASK (0x3ffffff << 0) 45 #define SPLL_DITHEN (1 << 28) 46 47 #define CG_MPLL_FUNC_CNTL 0x624 48 #define MPLL_RESET (1 << 0) 49 #define MPLL_SLEEP (1 << 1) 50 #define MPLL_DIVEN (1 << 2) 51 #define MPLL_BYPASS_EN (1 << 3) 52 #define MPLL_REF_DIV(x) ((x) << 4) 53 #define MPLL_REF_DIV_MASK (0x3f << 4) 54 #define MPLL_HILEN(x) ((x) << 12) 55 #define MPLL_HILEN_MASK (0xf << 12) 56 #define MPLL_LOLEN(x) ((x) << 16) 57 #define MPLL_LOLEN_MASK (0xf << 16) 58 #define CG_MPLL_FUNC_CNTL_2 0x628 59 #define MCLK_MUX_SEL(x) ((x) << 0) 60 #define MCLK_MUX_SEL_MASK (0x1ff << 0) 61 #define CG_MPLL_FUNC_CNTL_3 0x62c 62 #define MPLL_FB_DIV(x) ((x) << 0) 63 #define MPLL_FB_DIV_MASK (0x3ffffff << 0) 64 #define MPLL_DITHEN (1 << 28) 65 66 #define CG_TCI_MPLL_SPREAD_SPECTRUM 0x634 67 #define CG_TCI_MPLL_SPREAD_SPECTRUM_2 0x638 68 #define GENERAL_PWRMGT 0x63c 69 # define GLOBAL_PWRMGT_EN (1 << 0) 70 # define STATIC_PM_EN (1 << 1) 71 # define THERMAL_PROTECTION_DIS (1 << 2) 72 # define THERMAL_PROTECTION_TYPE (1 << 3) 73 # define ENABLE_GEN2PCIE (1 << 4) 74 # define ENABLE_GEN2XSP (1 << 5) 75 # define SW_SMIO_INDEX(x) ((x) << 6) 76 # define SW_SMIO_INDEX_MASK (3 << 6) 77 # define LOW_VOLT_D2_ACPI (1 << 8) 78 # define LOW_VOLT_D3_ACPI (1 << 9) 79 # define VOLT_PWRMGT_EN (1 << 10) 80 # define BACKBIAS_PAD_EN (1 << 18) 81 # define BACKBIAS_VALUE (1 << 19) 82 # define DYN_SPREAD_SPECTRUM_EN (1 << 23) 83 # define AC_DC_SW (1 << 24) 84 85 #define SCLK_PWRMGT_CNTL 0x644 86 # define SCLK_PWRMGT_OFF (1 << 0) 87 # define SCLK_LOW_D1 (1 << 1) 88 # define FIR_RESET (1 << 4) 89 # define FIR_FORCE_TREND_SEL (1 << 5) 90 # define FIR_TREND_MODE (1 << 6) 91 # define DYN_GFX_CLK_OFF_EN (1 << 7) 92 # define GFX_CLK_FORCE_ON (1 << 8) 93 # define GFX_CLK_REQUEST_OFF (1 << 9) 94 # define GFX_CLK_FORCE_OFF (1 << 10) 95 # define GFX_CLK_OFF_ACPI_D1 (1 << 11) 96 # define GFX_CLK_OFF_ACPI_D2 (1 << 12) 97 # define GFX_CLK_OFF_ACPI_D3 (1 << 13) 98 99 #define TCI_MCLK_PWRMGT_CNTL 0x648 100 # define MPLL_PWRMGT_OFF (1 << 5) 101 # define DLL_READY (1 << 6) 102 # define MC_INT_CNTL (1 << 7) 103 # define MRDCKA_SLEEP (1 << 8) 104 # define MRDCKB_SLEEP (1 << 9) 105 # define MRDCKC_SLEEP (1 << 10) 106 # define MRDCKD_SLEEP (1 << 11) 107 # define MRDCKE_SLEEP (1 << 12) 108 # define MRDCKF_SLEEP (1 << 13) 109 # define MRDCKG_SLEEP (1 << 14) 110 # define MRDCKH_SLEEP (1 << 15) 111 # define MRDCKA_RESET (1 << 16) 112 # define MRDCKB_RESET (1 << 17) 113 # define MRDCKC_RESET (1 << 18) 114 # define MRDCKD_RESET (1 << 19) 115 # define MRDCKE_RESET (1 << 20) 116 # define MRDCKF_RESET (1 << 21) 117 # define MRDCKG_RESET (1 << 22) 118 # define MRDCKH_RESET (1 << 23) 119 # define DLL_READY_READ (1 << 24) 120 # define USE_DISPLAY_GAP (1 << 25) 121 # define USE_DISPLAY_URGENT_NORMAL (1 << 26) 122 # define MPLL_TURNOFF_D2 (1 << 28) 123 #define TCI_DLL_CNTL 0x64c 124 125 #define CG_PG_CNTL 0x858 126 # define PWRGATE_ENABLE (1 << 0) 127 128 #define CG_AT 0x6d4 129 #define CG_R(x) ((x) << 0) 130 #define CG_R_MASK (0xffff << 0) 131 #define CG_L(x) ((x) << 16) 132 #define CG_L_MASK (0xffff << 16) 133 134 #define CG_SPLL_SPREAD_SPECTRUM 0x790 135 #define SSEN (1 << 0) 136 #define CLK_S(x) ((x) << 4) 137 #define CLK_S_MASK (0xfff << 4) 138 #define CG_SPLL_SPREAD_SPECTRUM_2 0x794 139 #define CLK_V(x) ((x) << 0) 140 #define CLK_V_MASK (0x3ffffff << 0) 141 142 #define MC_ARB_DRAM_TIMING 0x2774 143 #define MC_ARB_DRAM_TIMING2 0x2778 144 145 #define MC_ARB_RFSH_RATE 0x27b0 146 #define POWERMODE0(x) ((x) << 0) 147 #define POWERMODE0_MASK (0xff << 0) 148 #define POWERMODE1(x) ((x) << 8) 149 #define POWERMODE1_MASK (0xff << 8) 150 #define POWERMODE2(x) ((x) << 16) 151 #define POWERMODE2_MASK (0xff << 16) 152 #define POWERMODE3(x) ((x) << 24) 153 #define POWERMODE3_MASK (0xffU << 24) 154 155 #define MC_ARB_DRAM_TIMING_1 0x27f0 156 #define MC_ARB_DRAM_TIMING_2 0x27f4 157 #define MC_ARB_DRAM_TIMING_3 0x27f8 158 #define MC_ARB_DRAM_TIMING2_1 0x27fc 159 #define MC_ARB_DRAM_TIMING2_2 0x2800 160 #define MC_ARB_DRAM_TIMING2_3 0x2804 161 162 #define MC4_IO_DQ_PAD_CNTL_D0_I0 0x2978 163 #define MC4_IO_DQ_PAD_CNTL_D0_I1 0x297c 164 #define MC4_IO_QS_PAD_CNTL_D0_I0 0x2980 165 #define MC4_IO_QS_PAD_CNTL_D0_I1 0x2984 166 167 #endif 168
Indexes created Sat Sep 20 22:09:52 GMT 2025