1 /* $NetBSD: mq200reg.h,v 1.12 2024/05/23 08:30:51 andvar Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2001 TAKEMURA Shin 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 */ 31 32 #define MQ200_VENDOR_ID 0x4d51 33 #define MQ200_PRODUCT_ID 0x0200 34 #define MQ200_MAPSIZE 0x800000 35 36 #define MQ200_POWERSTATE_D0 0 37 #define MQ200_POWERSTATE_D1 1 38 #define MQ200_POWERSTATE_D2 2 39 #define MQ200_POWERSTATE_D3 3 40 41 #define MQ200_CLOCK_BUS 0 42 #define MQ200_CLOCK_PLL1 1 43 #define MQ200_CLOCK_PLL2 2 44 #define MQ200_CLOCK_PLL3 3 45 46 #define MQ200_REGADDR 0x600000 /* register base address */ 47 #define MQ200_PM 0x000000 /* power management */ 48 #define MQ200_CC 0x002000 /* CPU interface */ 49 #define MQ200_MM 0x004000 /* memory interface unit */ 50 #define MQ200_IN 0x008000 /* interrupt controller */ 51 #define MQ200_GC(n) (0x00a000+0x80*(n)) 52 #define MQ200_GE 0x00c000 /* graphics engine */ 53 #define MQ200_FP 0x00e000 /* flat panel controller*/ 54 #define MQ200_CP1 0x010000 /* color palette 1 */ 55 #define MQ200_DC 0x014000 /* device configuration */ 56 #define MQ200_PC 0x016000 /* PCI configuration */ 57 58 /* 59 * Power Management 60 */ 61 62 /* 63 * CPU Interface 64 */ 65 66 /* 67 * Memory Interface Unit 68 */ 69 #define MQ200_MMR(n) (MQ200_MM+(n)*4) 70 # define MQ200_MM00_ENABLE (1<<0) 71 # define MQ200_MM00_RESET (1<<1) 72 # define MQ200_MM00_DRAM_RESET (1<<2) 73 # define MQ200_MM01_CLK_PLL1 (0<<0) 74 # define MQ200_MM01_CLK_BUS (1<<0) 75 # define MQ200_MM01_CLK_PLL2 (1<<0) 76 # define MQ200_MM01_SLOW_REFRESH_EN (1<<1) 77 # define MQ200_MM01_CPU_PB_EN (1<<2) 78 # define MQ200_MM01_GC1_PB_EN (1<<3) 79 # define MQ200_MM01_GC2_PB_EN (1<<4) 80 # define MQ200_MM01_STN_READ_PB_EN (1<<5) 81 # define MQ200_MM01_STN_WRITE_PB_EN (1<<6) 82 # define MQ200_MM01_GE_PB_EN (1<<7) 83 /* bits 11-8 is reserved */ 84 # define MQ200_MM01_REFRESH_SHIFT 12 85 # define MQ200_MM01_REFRESH_MASK 0x03fff000 86 /* bits 29 is reserved */ 87 # define MQ200_MM01_DRAM_AUTO_REFRESH_EN (1<<30) 88 # define MQ200_MM01_DRAM_STANDBY_EN (1<<31) 89 90 /* 91 * Interrupt Controller 92 */ 93 94 /* 95 * Graphics Controller 1/2 96 */ 97 #define MQ200_GC1 0 /* graphice controller 1*/ 98 #define MQ200_GC2 1 /* graphice controller 2*/ 99 #define MQ200_GCR(n) (MQ200_GC(0)+(n)*4) 100 /* GC Control (GC00R and GC20R) */ 101 #define MQ200_GCCR(n) (MQ200_GC(n)+0x00) 102 # define MQ200_GCC_ENABLE (1<<0) 103 # define MQ200_GCC_HCRESET (1<<1) 104 # define MQ200_GCC_VCRESET (1<<2) 105 # define MQ200_GCC_WINEN (1<<3) 106 # define MQ200_GCC_DEPTH_SHIFT 4 107 # define MQ200_GCC_DEPTH_MASK 0x000000f0 108 # define MQ200_GCC_HCEN (1<<8) 109 /* bits 10-9 is reserved */ 110 # define MQ200_GCC_ALTEN (1<<11) 111 # define MQ200_GCC_ALTDEPTH_SHIFT 12 112 # define MQ200_GCC_ALTDEPTH_MASK 0x0000f000 113 # define MQ200_GCC_RCLK_SHIFT 16 114 # define MQ200_GCC_RCLK_MASK 0x00030000 115 # define MQ200_GCC_RCLK_BUS 0x00000000 116 # define MQ200_GCC_RCLK_PLL1 0x00010000 117 # define MQ200_GCC_RCLK_PLL2 0x00020000 118 # define MQ200_GCC_RCLK_PLL3 0x00030000 119 # define MQ200_GCC_TESTMODE0 (1<<18) 120 # define MQ200_GCC_TESTMODE1 (1<<19) 121 /* FD(first clock divisor) is 1, 1.5, 2.5, 3.5, 4.5, 5.6 or 6.5 */ 122 # define MQ200_GCC_MCLK_FD_SHIFT 20 123 # define MQ200_GCC_MCLK_FD_MASK 0x00700000 124 # define MQ200_GCC_MCLK_FD_1 0x00000000 125 # define MQ200_GCC_MCLK_FD_1_5 0x00100000 126 # define MQ200_GCC_MCLK_FD_2_5 0x00200000 127 # define MQ200_GCC_MCLK_FD_3_5 0x00300000 128 # define MQ200_GCC_MCLK_FD_4_5 0x00400000 129 # define MQ200_GCC_MCLK_FD_5_5 0x00500000 130 # define MQ200_GCC_MCLK_FD_6_5 0x00600000 131 /* bit 23 is reserved */ 132 /* SD(second close divisor) is 1-255. 0 means disable */ 133 # define MQ200_GCC_MCLK_SD_SHIFT 24 134 # define MQ200_GCC_MCLK_SD_MASK 0xff000000 135 /* GCCR_DEPTH and GCCR_ALTDEPTH values */ 136 # define MQ200_GCC_1BPP 0x0 137 # define MQ200_GCC_2BPP 0x1 138 # define MQ200_GCC_4BPP 0x2 139 # define MQ200_GCC_8BPP 0x3 140 # define MQ200_GCC_16BPP 0x4 141 # define MQ200_GCC_24BPP 0x5 142 # define MQ200_GCC_ARGB888 0x6 143 # define MQ200_GCC_PALBGR 0x6 144 # define MQ200_GCC_ABGR888 0x7 145 # define MQ200_GCC_PALRGB 0x7 146 # define MQ200_GCC_16BPP_DIRECT 0xc 147 # define MQ200_GCC_24BPP_DIRECT 0xd 148 # define MQ200_GCC_ARGB888_DIRECT 0xe 149 # define MQ200_GCC_PALBGR_DIRECT 0xe 150 # define MQ200_GCC_ABGR888_DIRECT 0xf 151 # define MQ200_GCC_PALRGB_DIRECT 0xf 152 153 /* GC CRT Control (GC1only) */ 154 #define MQ200_GC1CRTCR MQ200_GCR(0x01) 155 # define MQ200_GC1CRTC_DACEN (1<<0) 156 # define MQ200_GC1CRTC_HSYNC_PMCLK (1<<2) 157 # define MQ200_GC1CRTC_VSYNC_PMCLK (1<<3) 158 # define MQ200_GC1CRTC_HSYNC_PMMASK 0x00000030 159 # define MQ200_GC1CRTC_HSYNC_PMNORMAL 0x00000000 160 # define MQ200_GC1CRTC_HSYNC_PMLOW 0x00000010 161 # define MQ200_GC1CRTC_HSYNC_PMHIGH 0x00000020 162 # define MQ200_GC1CRTC_VSYNC_PMMASK 0x000000c0 163 # define MQ200_GC1CRTC_VSYNC_PMNORMAL 0x00000000 164 # define MQ200_GC1CRTC_VSYNC_PMLOW 0x00000040 165 # define MQ200_GC1CRTC_VSYNC_PMHIGH 0x00000080 166 # define MQ200_GC1CRTC_HSYNC_ACTVHIGH (0<<8) 167 # define MQ200_GC1CRTC_HSYNC_ACTVLOW (1<<8) 168 # define MQ200_GC1CRTC_VSYNC_ACTVHIGH (0<<9) 169 # define MQ200_GC1CRTC_VSYNC_ACTVLOW (1<<9) 170 # define MQ200_GC1CRTC_SYNC_PEDESTAL_EN (1<<10) 171 # define MQ200_GC1CRTC_BLANK_PEDESTAL_EN (1<<11) 172 # define MQ200_GC1CRTC_COMPOSITE_SYNC_EN (1<<12) 173 # define MQ200_GC1CRTC_VREF_INTR (0<<13) 174 # define MQ200_GC1CRTC_VREF_EXTR (1<<13) 175 # define MQ200_GC1CRTC_MONITOR_SENCE_EN (1<<14) 176 # define MQ200_GC1CRTC_CONSTANT_OUTPUT_EN (1<<15) 177 # define MQ200_GC1CRTC_OUTPUT_LEVEL_MASK 0x00ff0000 178 # define MQ200_GC1CRTC_OUTPUT_LEVEL_SHIFT 16 179 # define MQ200_GC1CRTC_BLUE_NOTLOADED (1<<24) 180 # define MQ200_GC1CRTC_RED_NOTLOADED (1<<25) 181 # define MQ200_GC1CRTC_GREEN_NOTLOADED (1<<26) 182 /* bit 27 is reserved */ 183 # define MQ200_GC1CRTC_COLOR (0<<28) 184 # define MQ200_GC1CRTC_MONO (1<<28) 185 /* bits 31-29 are reserved */ 186 187 /* GC CRC Control (GC2 only) */ 188 #define MQ200_GC2CRCCR MQ200_GCR(0x21) 189 # define MQ200_GC2CRCC_ENABLE (1<<0) 190 # define MQ200_GC2CRCC_WAIT1VSYNC (0<<1) 191 # define MQ200_GC2CRCC_WAIT2VSYNC (1<<1) 192 # define MQ200_GC2CRCC_BLUE (0x0<<2) 193 # define MQ200_GC2CRCC_GREEN (0x1<<2) 194 # define MQ200_GC2CRCC_RED (0x2<<2) 195 # define MQ200_GC2CRCC_RESULT_SHIFT 8 196 # define MQ200_GC2CRCC_RESULT_MASK 0x3fffff00 197 198 /* GC Horizontal Display Control (GC02R and GC22R) */ 199 #define MQ200_GCHDCR(n) (MQ200_GC(n)+0x08) 200 # define MQ200_GC1HDC_TOTAL_MASK 0x00000fff 201 # define MQ200_GC1HDC_TOTAL_SHIFT 0 202 /* bits 15-12 are reserved */ 203 # define MQ200_GCHDC_END_MASK 0x0fff0000 204 # define MQ200_GCHDC_END_SHIFT 16 205 /* bits 31-28 are reserved */ 206 207 /* GC Vertical Display Control (GC03R and GC23R) */ 208 #define MQ200_GCVDCR(n) (MQ200_GC(n)+0x0c) 209 # define MQ200_GC1VDC_TOTAL_MASK 0x00000fff 210 # define MQ200_GC1VDC_TOTAL_SHIFT 0 211 /* bits 15-12 are reserved */ 212 # define MQ200_GCVDC_END_MASK 0x0fff0000 213 # define MQ200_GCVDC_END_SHIFT 16 214 /* bits 31-28 are reserved */ 215 216 /* GC Horizontal Sync Control (GC04R and GC24R) */ 217 #define MQ200_GCHSCR(n) (MQ200_GC(n)+0x10) 218 # define MQ200_GCHSC_START_MASK 0x00000fff 219 # define MQ200_GCHSC_START_SHIFT 0 220 /* bits 15-12 are reserved */ 221 # define MQ200_GCHSC_END_MASK 0x0fff0000 222 # define MQ200_GCHSC_END_SHIFT 16 223 /* bits 31-28 are reserved */ 224 225 /* GC Vertical Sync Control (GC05R and GC25R) */ 226 #define MQ200_GCVSCR(n) (MQ200_GC(n)+0x14) 227 # define MQ200_GCVSC_START_MASK 0x00000fff 228 # define MQ200_GCVSC_START_SHIFT 0 229 /* bits 15-12 are reserved */ 230 # define MQ200_GCVSC_END_MASK 0x0fff0000 231 # define MQ200_GCVSC_END_SHIFT 16 232 /* bits 31-28 are reserved */ 233 234 /* GC Vertical Display Count (GC07R) */ 235 #define MQ200_GC1VDCNTR MQ200_GCR(0x07) 236 # define MQ200_GC1VDCNT_MASK 0x00000fff 237 /* bits 31-12 are reserved */ 238 239 /* GC Window Horizontal Control (GC08R and GC28R) */ 240 #define MQ200_GCWHCR(n) (MQ200_GC(n)+0x20) 241 # define MQ200_GCWHC_START_MASK 0x00000fff 242 # define MQ200_GCWHC_START_SHIFT 0 243 /* bits 15-12 are reserved */ 244 # define MQ200_GCWHC_WIDTH_MASK 0x0fff0000 245 # define MQ200_GCWHC_WIDTH_SHIFT 16 246 /* ALD: Additional Line Delta (GC1 only) */ 247 # define MQ200_GC1WHC_ALD_MASK 0xf0000000 248 # define MQ200_GC1WHC_ALD_SHIFT 28 249 250 /* GC Window Vertical Control (GC09R and GC29R) */ 251 #define MQ200_GCWVCR(n) (MQ200_GC(n)+0x24) 252 # define MQ200_GCWVC_START_MASK 0x00000fff 253 # define MQ200_GCWVC_START_SHIFT 0 254 /* bits 15-12 are reserved */ 255 # define MQ200_GCWVC_HEIGHT_MASK 0x0fff0000 256 # define MQ200_GCWVC_HEIGHT_SHIFT 16 257 /* bits 31-28 are reserved */ 258 259 /* GC Altarnate Window Horizontal Control (GC0AR and GC2AR) */ 260 #define MQ200_GCAWHCR(n) (MQ200_GC(n)+0x28) 261 # define MQ200_GCAWHC_START_MASK 0x00000fff 262 # define MQ200_GCAWHC_START_SHIFT 0 263 /* bits 15-12 are reserved */ 264 # define MQ200_GCAWHC_WIDTH_MASK 0x0fff0000 265 # define MQ200_GCAWHC_WIDTH_SHIFT 16 266 /* ALD: Additional Line Delta (GC1 only) */ 267 # define MQ200_GC1AWHC_ALD_MASK 0xf0000000 268 # define MQ200_GC1AWHC_ALD_SHIFT 28 269 270 /* GC Alternate Window Vertical Control (GC0BR and GC2BR) */ 271 #define MQ200_GCAWVCR(n) (MQ200_GC(n)+0x2C) 272 # define MQ200_GCAWVC_START_MASK 0x00000fff 273 # define MQ200_GCAWVC_START_SHIFT 0 274 /* bits 15-12 are reserved */ 275 # define MQ200_GCAWVC_HEIGHT_MASK 0x0fff0000 276 # define MQ200_GCAWVC_HEIGHT_SHIFT 16 277 /* bits 31-28 are reserved */ 278 279 /* GC Window Start Address (GC0CR and GC2CR) */ 280 #define MQ200_GCWSAR(n) (MQ200_GC(n)+0x30) 281 # define MQ200_GCWSA_MASK 0x000fffff 282 /* bits 31-21 are reserved */ 283 284 /* GC Alternate Window Start Address (GC0DR and GC2DR) */ 285 #define MQ200_GCAWSAR(n) (MQ200_GC(n)+0x34) 286 # define MQ200_GCAWSA_MASK 0x000fffff 287 /* bits 24-21 are reserved */ 288 # define MQ200_GCAWPI_MASK 0xfe000000 289 # define MQ200_GCAWPI_SHIFT 24 /* XXX, 24 could be useful 290 than 23 */ 291 292 /* GC Window Stride (GC0ER and GC2ER) */ 293 #define MQ200_GCWSTR(n) (MQ200_GC(n)+0x38) 294 # define MQ200_GCWST_MASK 0x0000ffff 295 # define MQ200_GCWST_SHIFT 0 296 # define MQ200_GCAWST_MASK 0xffff0000 297 # define MQ200_GCAWST_SHIFT 16 298 299 /* GC2 Line Size (GC2 only, GC2FR) */ 300 #define MQ200_GC2LSR MQ200_GCR(0x2f) 301 # define MQ200_GC2WLS_MASK 0x00003fff 302 # define MQ200_GC2WLS_SHIFT 0 303 # define MQ200_GC2AWLS_MASK 0x3fff0000 304 # define MQ200_GC2AWLS_SHIFT 16 305 306 307 /* GC Hardware Cursor Position (GC10R and GC30R) */ 308 #define MQ200_GCHCPR(n) (MQ200_GC(n)+0x40) 309 # define MQ200_GCHCP_HSTART_MASK 0x00000fff 310 # define MQ200_GCHCP_HSTART_SHIFT 0 311 /* bits 15-12 are reserved */ 312 # define MQ200_GCHCP_VSTART_MASK 0x0fff0000 313 # define MQ200_GCHCP_VSTART_SHIFT 16 314 /* bits 31-28 are reserved */ 315 316 /* GC Hardware Start Address and Offset (GC11R and GC31R) */ 317 #define MQ200_GCHCAOR(n) (MQ200_GC(n)+0x44) 318 # define MQ200_GCHCAO_ADDR_MASK 0x00000fff 319 # define MQ200_GCHCAO_ADDR_SHIFT 0 320 /* bits 15-12 are reserved */ 321 # define MQ200_GCHCAO_HOFFSET_MASK 0x003f0000 322 # define MQ200_GCHCAO_HOFFSET_SHIFT 16 323 /* bits 23-22 are reserved */ 324 # define MQ200_GCHCAO_VOFFSET_MASK 0x3f000000 325 # define MQ200_GCHCAO_VOFFSET_SHIFT 24 326 /* bits 31-30 are reserved */ 327 328 /* GC Hardware Cursor Foreground Color (GC13R and GC33R) */ 329 #define MQ200_GCHCFCR(n) (MQ200_GC(n)+0x48) 330 # define MQ200_GCHCFC_MASK 0x00ffffff 331 /* you can use MQ200_GC_RGB macro */ 332 /* bits 31-24 are reserved */ 333 334 /* GC Hardware Cursor Background Color (GC14R and GC34R) */ 335 #define MQ200_GCHCBCR(n) (MQ200_GC(n)+0x4c) 336 # define MQ200_GCHCBC_MASK 0x00ffffff 337 /* you can use MQ200_GC_RGB macro */ 338 /* bits 31-24 are reserved */ 339 340 #define MQ200_GC1CR MQ200_GCCR(0) 341 #define MQ200_GC1HDCR MQ200_GCHDCR(0) 342 #define MQ200_GC1VDCR MQ200_GCVDCR(0) 343 #define MQ200_GC1HSCR MQ200_GCHSCR(0) 344 #define MQ200_GC1VSCR MQ200_GCVSCR(0) 345 #define MQ200_GC1HWCR MQ200_GCHWCR(0) 346 #define MQ200_GC1VWCR MQ200_GCVWCR(0) 347 #define MQ200_GC1HAWCR MQ200_GCHAWCR(0) 348 #define MQ200_GC1AVWCR MQ200_GCAVWCR(0) 349 #define MQ200_GC1WSAR MQ200_GCWSAR(0) 350 #define MQ200_GC1AWSAR MQ200_GCAWSAR(0) 351 #define MQ200_GC1WSTR MQ200_GCWSTR(0) 352 #define MQ200_GC1HCPR MQ200_GCHCPR(0) 353 #define MQ200_GC1HCAOR MQ200_GCHCAOR(0) 354 #define MQ200_GC1HCFCR MQ200_GCHCFCR(0) 355 #define MQ200_GC1HCBCR MQ200_GCHCBCR(0) 356 357 #define MQ200_GC2CR MQ200_GCCR(1) 358 #define MQ200_GC2HDCR MQ200_GCHDCR(1) 359 #define MQ200_GC2VDCR MQ200_GCVDCR(1) 360 #define MQ200_GC2HSCR MQ200_GCHSCR(1) 361 #define MQ200_GC2VSCR MQ200_GCVSCR(1) 362 #define MQ200_GC2HWCR MQ200_GCHWCR(1) 363 #define MQ200_GC2VWCR MQ200_GCVWCR(1) 364 #define MQ200_GC2HAWCR MQ200_GCHAWCR(1) 365 #define MQ200_GC2AVWCR MQ200_GCAVWCR(1) 366 #define MQ200_GC2WSAR MQ200_GCWSAR(1) 367 #define MQ200_GC2AWSAR MQ200_GCAWSAR(1) 368 #define MQ200_GC2WSTR MQ200_GCWSTR(1) 369 #define MQ200_GC2HCPR MQ200_GCHCPR(1) 370 #define MQ200_GC2HCAOR MQ200_GCHCAOR(1) 371 #define MQ200_GC2HCFCR MQ200_GCHCFCR(1) 372 #define MQ200_GC2HCBCR MQ200_GCHCBCR(1) 373 374 /* 375 * Graphics Engine 376 */ 377 378 /* 379 * Flat Pannel Controller 380 */ 381 #define MQ200_FPR(n) (MQ200_FP + (n)*4) 382 /* FP Control (FP00R) */ 383 #define MQ200_FPCR MQ200_FPR(0) 384 # define MQ200_FPC_ENABLE (1<<0) 385 # define MQ200_FPC_GC1 (0<<1) 386 # define MQ200_FPC_GC2 (1<<1) 387 # define MQ200_FPC_TYPE_MASK 0x000000fc 388 # define MQ200_FPC_TYPE_SHIFT 2 389 390 # define MQ200_FPC_TFT (0<<2) 391 # define MQ200_FPC_SSTN (1<<2) 392 # define MQ200_FPC_DSTN (2<<2) 393 394 # define MQ200_FPC_COLOR (0<<4) 395 # define MQ200_FPC_MONO (1<<4) 396 397 # define MQ200_FPC_TFTCOLOR (MQ200_FPC_TFT|MQ200_FPC_COLOR) 398 # define MQ200_FPC_SSTNCOLOR (MQ200_FPC_SSTN|MQ200_FPC_COLOR) 399 # define MQ200_FPC_DSTNCOLOR (MQ200_FPC_DSTN|MQ200_FPC_COLOR) 400 401 # define MQ200_FPC_TFTMONO (MQ200_FPC_TFT|MQ200_FPC_MONO) 402 # define MQ200_FPC_SSTNMONO (MQ200_FPC_SSTN|MQ200_FPC_MONO) 403 # define MQ200_FPC_DSTNMONO (MQ200_FPC_DSTN|MQ200_FPC_MONO) 404 405 # define MQ200_FPC_TFT4MONO ((0<<5)|MQ200_FPC_TFTMONO) 406 # define MQ200_FPC_TFT12 ((0<<5)|MQ200_FPC_TFTCOLOR) 407 # define MQ200_FPC_SSTN4 ((0<<5)|MQ200_FPC_SSTNCOLOR) 408 # define MQ200_FPC_DSTN8 ((0<<5)|MQ200_FPC_DSTNCOLOR) 409 # define MQ200_FPC_TFT6MONO ((1<<5)|MQ200_FPC_TFTMONO) 410 # define MQ200_FPC_TFT18 ((1<<5)|MQ200_FPC_TFTCOLOR) 411 # define MQ200_FPC_SSTN8 ((1<<5)|MQ200_FPC_SSTNCOLOR) 412 # define MQ200_FPC_DSTN16 ((1<<5)|MQ200_FPC_DSTNCOLOR) 413 # define MQ200_FPC_TFT8MONO ((2<<5)|MQ200_FPC_TFTMONO) 414 # define MQ200_FPC_TFT24 ((2<<5)|MQ200_FPC_TFTCOLOR) 415 # define MQ200_FPC_SSTN12 ((2<<5)|MQ200_FPC_SSTNCOLOR) 416 # define MQ200_FPC_DSTN24 ((2<<5)|MQ200_FPC_DSTNCOLOR) 417 # define MQ200_FPC_SSTN16 ((3<<5)|MQ200_FPC_SSTNCOLOR) 418 # define MQ200_FPC_SSTN24 ((4<<5)|MQ200_FPC_SSTNCOLOR) 419 # define MQ200_FPC_DITH_DISABLE (0<<8) 420 # define MQ200_FPC_DITH_PTRN1 (1<<8) 421 # define MQ200_FPC_DITH_PTRN2 (2<<8) 422 # define MQ200_FPC_DITH_PTRN3 (3<<8) 423 /* bits 11-10 are reserved */ 424 # define MQ200_FPC_DITH_BC_MASK 0x00007000 425 # define MQ200_FPC_DITH_BC_SHIFT 12 426 # define MQ200_FPC_FRC_DISABLE_ALTWIN (1<<15) 427 # define MQ200_FPC_FRC_2LEVEL (0<<16) 428 # define MQ200_FPC_FRC_4LEVEL (1<<16) 429 # define MQ200_FPC_FRC_8LEVEL (2<<16) 430 # define MQ200_FPC_FRC_16LEVEL (3<<16) 431 # define MQ200_FPC_DITH_ADJ_MASK 0x0ffc0000 432 # define MQ200_FPC_DITH_ADJ_SHIFT 18 433 # define MQ200_FPC_DITH_ADJ_VAL 0x018 434 # define MQ200_FPC_DITH_ADJ1_MASK 0x00fc0000 435 # define MQ200_FPC_DITH_ADJ1_SHIFT 18 436 # define MQ200_FPC_DITH_ADJ1_VAL 0x18 437 # define MQ200_FPC_DITH_ADJ2_MASK 0x07000000 438 # define MQ200_FPC_DITH_ADJ2_SHIFT 24 439 # define MQ200_FPC_DITH_ADJ2_VAL 0x0 440 # define MQ200_FPC_DITH_ADJ3_MASK 0x08000000 441 # define MQ200_FPC_DITH_ADJ3_SHIFT 27 442 # define MQ200_FPC_DITH_ADJ3_VAL 0x0 443 # define MQ200_FPC_TESTMODE0 (1<<28) 444 # define MQ200_FPC_TESTMODE1 (1<<29) 445 # define MQ200_FPC_TESTMODE2 (1<<30) 446 # define MQ200_FPC_TESTMODE3 (1<<31) 447 448 /* FP Output Pin Control (FP01R) */ 449 #define MQ200_FPPCR MQ200_FPR(1) 450 # define MQ200_FPPC_PIN_LOW (1<<0) 451 # define MQ200_FPPC_INVERSION_EN (1<<1) 452 # define MQ200_FPPC_FDE_COMPOSITE (0<<2) 453 # define MQ200_FPPC_FDE_HORIZONTAL (1<<2) 454 # define MQ200_FPPC_FDE_FMOD_EN (1<<3) 455 # define MQ200_FPPC_FD2_DATAK (0<<4) 456 # define MQ200_FPPC_FD2_SHIFTCLK (1<<4) 457 # define MQ200_FPPC_FSCLK_EN (1<<5) 458 # define MQ200_FPPC_SHIFTCLK_DIV2 (1<<6) 459 # define MQ200_FPPC_SHIFTCLK_MASK (1<<7) 460 # define MQ200_FPPC_STNLP_BLANK (1<<8) 461 # define MQ200_FPPC_SHIFTCLK_BLANK (1<<9) 462 # define MQ200_FPPC_STNEXLP_EN (1<<10) 463 /* bit 11 is reserved */ 464 # define MQ200_FPPC_FD2_MAX (0<<12) 465 # define MQ200_FPPC_FD2_MID (1<<12) 466 # define MQ200_FPPC_FD2_MID2 (2<<12) 467 # define MQ200_FPPC_FD2_MIN (3<<12) 468 # define MQ200_FPPC_DRV_MAX (0<<12) 469 # define MQ200_FPPC_DRV_MID (1<<12) 470 # define MQ200_FPPC_DRV_MID2 (2<<12) 471 # define MQ200_FPPC_DRV_MIN (3<<12) 472 # define MQ200_FPPC_FD2_ACTVHIGH (0<<16) 473 # define MQ200_FPPC_FD2_ACTVLOW (1<<16) 474 # define MQ200_FPPC_ACTVHIGH (0<<17) 475 # define MQ200_FPPC_ACTVLOW (1<<17) 476 # define MQ200_FPPC_FDE_ACTVHIGH (0<<18) 477 # define MQ200_FPPC_FDE_ACTVLOW (1<<18) 478 # define MQ200_FPPC_FHSYNC_ACTVHIGH (0<<19) 479 # define MQ200_FPPC_FHSYNC_ACTVLOW (1<<19) 480 # define MQ200_FPPC_FVSYNC_ACTVHIGH (0<<20) 481 # define MQ200_FPPC_FVSYNC_ACTVLOW (1<<20) 482 # define MQ200_FPPC_FSCLK_ACTVHIGH (0<<21) 483 # define MQ200_FPPC_FSCLK_ACTVLOW (1<<21) 484 # define MQ200_FPPC_FSCLK_MAX (0<<22) 485 # define MQ200_FPPC_FSCLK_MID (1<<22) 486 # define MQ200_FPPC_FSCLK_MID2 (2<<22) 487 # define MQ200_FPPC_FSCLK_MIN (3<<22) 488 # define MQ200_FPPC_FSCLK_DELAY_MASK 0x07000000 489 # define MQ200_FPPC_FSCLK_DELAY_SHIFT 24 490 /* bits 31-27 are reserved */ 491 492 /* FP General Purpose Output Port Control (FP02R) */ 493 #define MQ200_FPGPOCR MQ200_FPR(2) 494 # define MQ200_FPGPOC_ENCTL_EN (0<<0) 495 # define MQ200_FPGPOC_GPO0_EN (1<<0) 496 # define MQ200_FPGPOC_OSCCLK_EN (2<<0) 497 # define MQ200_FPGPOC_PLL3_EN (3<<0) 498 # define MQ200_FPGPOC_ENVEE_EN (0<<2) 499 # define MQ200_FPGPOC_GPO1_EN (1<<2) 500 # define MQ200_FPGPOC_PWM0_EN (0<<4) 501 # define MQ200_FPGPOC_GPO2_EN (1<<4) 502 # define MQ200_FPGPOC_PWM1_EN (0<<6) 503 # define MQ200_FPGPOC_GPO3_EN (1<<6) 504 # define MQ200_FPGPOC_ENVDD_EN (0<<8) 505 # define MQ200_FPGPOC_GPO4_EN (1<<9) 506 # define MQ200_FPGPOC_PWM_MAX (0<<10) 507 # define MQ200_FPGPOC_PWM_MID (1<<10) 508 # define MQ200_FPGPOC_PWM_MID2 (2<<10) 509 # define MQ200_FPGPOC_PWM_MIN (3<<10) 510 # define MQ200_FPGPOC_GPO_MAX (0<<12) 511 # define MQ200_FPGPOC_GPO_MID (1<<12) 512 # define MQ200_FPGPOC_GPO_MID2 (2<<12) 513 # define MQ200_FPGPOC_GPO_MIN (3<<12) 514 # define MQ200_FPGPOC_DRV_MAX (0<<14) 515 # define MQ200_FPGPOC_DRV_MID (1<<14) 516 # define MQ200_FPGPOC_DRV_MID2 (2<<14) 517 # define MQ200_FPGPOC_DRV_MIN (3<<14) 518 # define MQ200_FPGPOC_GPO0 (1<<16) 519 # define MQ200_FPGPOC_GPO1 (1<<17) 520 # define MQ200_FPGPOC_GPO2 (1<<18) 521 # define MQ200_FPGPOC_GPO3 (1<<19) 522 # define MQ200_FPGPOC_GPO4 (1<<20) 523 /* bits 31-21 are reserved */ 524 525 /* FP General Purpose I/O Port Control (FP03R) */ 526 #define MQ200_FPGPOICR MQ200_FPR(3) 527 # define MQ200_FPGPIOC_INPUT0_EN (0<<0) 528 # define MQ200_FPGPIOC_OUTPUT0_EN (1<<0 529 # define MQ200_FPGPIOC_PLL1_EN (2<<0) 530 # define MQ200_FPGPIOC_CRCBLUE_EN (3<<0) 531 # define MQ200_FPGPIOC_INPUT1_EN (0<<2) 532 # define MQ200_FPGPIOC_OUTPUT1_EN (1<<2 533 # define MQ200_FPGPIOC_PLL2_EN (2<<2) 534 # define MQ200_FPGPIOC_CRCGREEN_EN (3<<2) 535 # define MQ200_FPGPIOC_INPUT2_EN (0<<4) 536 # define MQ200_FPGPIOC_OUTPUT2_EN (1<<4 537 # define MQ200_FPGPIOC_PMCLK_EN (2<<4) 538 # define MQ200_FPGPIOC_CRCRED_EN (3<<4) 539 /* bits 15-6 are reserved */ 540 # define MQ200_FPGPIOC_OUTPUT0 (1<<16) 541 # define MQ200_FPGPIOC_OUTPUT1 (1<<17) 542 # define MQ200_FPGPIOC_OUTPUT2 (1<<18) 543 /* bits 23-19 are reserved */ 544 # define MQ200_FPGPIOC_INPUT0 (1<<24) 545 # define MQ200_FPGPIOC_INPUT1 (1<<25) 546 # define MQ200_FPGPIOC_INPUT2 (1<<26) 547 /* bits 31-27 are reserved */ 548 549 /* FP STN Panel Control (FP04R) */ 550 #define MQ200_FPSTNCR MQ200_FPR(4) 551 # define MQ200_FPSTNC_FRCPRM0_MASK 0x000000ff 552 # define MQ200_FPSTNC_FRCPRM0_SHIFT 0 553 # define MQ200_FPSTNC_FRCPRM1_MASK 0x0000ff00 554 # define MQ200_FPSTNC_FRCPRM1_SHIFT 8 555 # define MQ200_FPSTNC_FRCPRM2_MASK 0x00ff0000 556 # define MQ200_FPSTNC_FRCPRM2_SHIFT 16 557 # define MQ200_FPSTNC_FMOD_MASK 0x7f000000 558 # define MQ200_FPSTNC_FMOD_SHIFT 24 559 # define MQ200_FPSTNC_FMOD_FRAMECLK (0<<31) 560 # define MQ200_FPSTNC_FMOD_LINECLK (0<<31) 561 562 /* FP D-STN Half-Frame Buffer Control (FP05R) */ 563 #define MQ200_FPHFBCR MQ200_FPR(5) 564 # define MQ200_FPHFBC_START_MASK 0x00003fff 565 # define MQ200_FPHFBC_START_SHIFT -7 /* XXX, does this work? */ 566 /* bits 15-14 are reserved */ 567 # define MQ200_FPHFBC_END_MASK 0xffff0000 568 # define MQ200_FPHFBC_END_SHIFT (16-4) /* XXX, does this work? */ 569 570 /* FP Pulse Width Modulation Control (FP0FR) */ 571 #define MQ200_FPPWMCR MQ200_FPR(0xf) 572 # define MQ200_FPPWMC_PWM0_OSCCLK (0<<0) 573 # define MQ200_FPPWMC_PWM0_BUSCLK (1<<0) 574 # define MQ200_FPPWMC_PWM0_PMCLK (2<<0) 575 # define MQ200_FPPWMC_PWM0_PWSEQ_EN (0<<2) 576 # define MQ200_FPPWMC_PWM0_PWSEQ_DISABLE (1<<2) 577 /* bit 3 is reserved */ 578 # define MQ200_FPPWMC_PWM0_DIV_MASK 0x000000f0 579 # define MQ200_FPPWMC_PWM0_DIV_SHIFT 4 580 # define MQ200_FPPWMC_PWM0_DCYCLE_MASK 0x0000ff00 581 # define MQ200_FPPWMC_PWM0_DCYCLE_SHIFT 8 582 # define MQ200_FPPWMC_PWM1_OSCCLK (0<<16) 583 # define MQ200_FPPWMC_PWM1_BUSCLK (1<<16) 584 # define MQ200_FPPWMC_PWM1_PMCLK (2<<16) 585 # define MQ200_FPPWMC_PWM1_PWSEQ_EN (0<<18) 586 # define MQ200_FPPWMC_PWM1_PWSEQ_DISABLE (1<<18) 587 /* bit 19 is reserved */ 588 # define MQ200_FPPWMC_PWM1_DIV_MASK 0x00f00000 589 # define MQ200_FPPWMC_PWM1_DIV_SHIFT 20 590 # define MQ200_FPPWMC_PWM1_DCYCLE_MASK 0xff000000 591 # define MQ200_FPPWMC_PWM1_DCYCLE_SHIFT 24 592 593 /* FP Frame Rate Control Pattern (FP10R to FP2FR) */ 594 #define MQ200_FPFRCPR(n) MQ200_FPR(0x10+n) 595 596 /* FP Frame Rate Control Weight (FP30R to FP37R) */ 597 #define MQ200_FPFRCWR(n) MQ200_FPR(0x30+n) 598 599 /* 600 * Color Palette 1 601 */ 602 #define MQ200_CP(cp, idx) (MQ200_CP1 + (idx) * 4) */ 603 # define MQ200_GC_BLUE_MASK 0x00ff0000 604 # define MQ200_GC_BLUE_SHIFT 16 605 # define MQ200_GC_GREEN_MASK 0x0000ff00 606 # define MQ200_GC_GREEN_SHIFT 8 607 # define MQ200_GC_RED_MASK 0x000000ff 608 # define MQ200_GC_RED_SHIFT 0 609 # define MQ200_GC_RGB(r, g, b) \ 610 (((((unsigned long)(r))&0xff)<<0) | \ 611 ((((unsigned long)(g))&0xff)<<8) | \ 612 ((((unsigned long)(b))&0xff)<<16)) 613 614 /* 615 * Device Configuration 616 */ 617 618 /* 619 * PCI configuration space 620 */ 621 #define MQ200_PC00R (MQ200_PC+0x00) /* device/vendor ID */ 622 #define MQ200_PC04R (MQ200_PC+0x04) /* command/status */ 623 #define MQ200_PC08R (MQ200_PC+0x04) /* calss code/revision */ 624 625 #define MQ200_PMR (MQ200_PC+0x40) /* power management */ 626 #define MQ200_PMCSR (MQ200_PC+0x44) /* control/status */ 627 628 /* 629 * Power Management 630 */ 631 #define MQ200_PMCR (MQ200_PM + 0x00) 632 # define MQ200_PMC_PLL1_N (1<<0) 633 # define MQ200_PMC_PLL1_N_SHIFT 5 634 # define MQ200_PMC_PLL2_ENABLE (1<<2) 635 # define MQ200_PMC_PLL3_ENABLE (1<<3) 636 # define MQ200_PMC_IMMEDIATELY (1<<5) 637 # define MQ200_PMC_GE_ENABLE (1<<8) 638 # define MQ200_PMC_GE_FORCE_BUSY (1<<9) 639 # define MQ200_PMC_GE_FORCE_BUSY_LOCAL (1<<10) 640 # define MQ200_PMC_GE_CLK_MASK 0x00001800 641 # define MQ200_PMC_GE_CLK_SHIFT 11 642 # define MQ200_PMC_GE_CLK_BUS (0<<11) 643 # define MQ200_PMC_GE_CLK_PLL1 (1<<11) 644 # define MQ200_PMC_GE_CLK_PLL2 (2<<11) 645 # define MQ200_PMC_GE_CLK_PLL3 (3<<11) 646 # define MQ200_PMC_GE_COMMAND_RESET (1<<13) 647 # define MQ200_PMC_GE_SOURCE_RESET (1<<14) 648 # define MQ200_PMC_MIU_SEQ_ENABLE (1<<15) 649 # define MQ200_PMC_D3_REFRESH (1<<16) 650 # define MQ200_PMC_D4_REFRESH (1<<17) 651 # define MQ200_PMC_SEQINTVL_MASK (3<<18) 652 # define MQ200_PMC_SEQINTVL_SHIFT 18 653 # define MQ200_PMC_SEQINTVL_4 (0<<18) 654 # define MQ200_PMC_SEQINTVL_8 (0<<18) 655 # define MQ200_PMC_SEQINTVL_16 (0<<18) 656 # define MQ200_PMC_SEQINTVL_2048 (0<<18) 657 # define MQ200_PMC_FP_SEQINTVL_MASK (3<<20) 658 # define MQ200_PMC_FP_SEQINTVL_SHIFT 20 659 # define MQ200_PMC_FP_SEQINTVL_512 (0<<20) 660 # define MQ200_PMC_FP_SEQINTVL_1024 (1<<20) 661 # define MQ200_PMC_FP_SEQINTVL_2048 (2<<20) 662 # define MQ200_PMC_FP_SEQINTVL_128K (3<<20) 663 # define MQ200_PMC_SEQINTVL_ALL (1<<22) 664 # define MQ200_PMC_TESTMODE (1<<23) 665 # define MQ200_PMC_STATE_MASK (3<<24) 666 # define MQ200_PMC_STATE_SHIFT 24 667 # define MQ200_PMC_SEQPROGRESS (1<<26) 668 #define MQ200_PMD1CR (MQ200_PM + 0x04) 669 #define MQ200_PMD2CR (MQ200_PM + 0x08) 670 671 #define MQ200_DCMISCR (MQ200_DC + 0x00) 672 # define MQ200_DCMISC_OSC_BYPASS (1<<0) 673 # define MQ200_DCMISC_OSC_ENABLE (1<<1) 674 # define MQ200_DCMISC_PLL1_BYPASS (1<<2) 675 # define MQ200_DCMISC_PLL1_ENABLE (1<<3) 676 # define MQ200_DCMISC_SA_SLOWBUS (1<<13) 677 # define MQ200_DCMISC_CHIP_RESET (1<<14) 678 # define MQ200_DCMISC_MEMSTANDBY_DISABLE (1<<15) 679 # define MQ200_DCMISC_OSCSHAPER_DISABLE (1<<24) 680 # define MQ200_DCMISC_FASTPOWSEQ_DISABLE (1<<25) 681 # define MQ200_DCMISC_OSCFREQ_MASK (3<<26) 682 # define MQ200_DCMISC_OSCFREQ_12_25 (3<<26) 683 684 /* 685 * Fout = Fref*(M+1)/(N+1)/(2^P) 686 * Fout: PLL output frequency 687 * Fref: reference frequency(internal oscillator or external clock) 688 */ 689 #define MQ200_PLL1R (MQ200_DC + 0x00) 690 #define MQ200_PLL2R (MQ200_PM + 0x18) 691 #define MQ200_PLL3R (MQ200_PM + 0x1c) 692 #define MQ200_PLL_EXTCLK (1<<0) 693 #define MQ200_PLL_BYPASS (1<<1) 694 #define MQ200_PLL_P_MASK 0x00000070 695 #define MQ200_PLL_P_SHIFT 4 696 #define MQ200_PLL_N_MASK 0x00001f00 697 #define MQ200_PLL_N_SHIFT 8 698 #define MQ200_PLL_M_MASK 0x00ff0000 699 #define MQ200_PLL_M_SHIFT 16 700 #define MQ200_PLL_PARAM_MASK (MQ200_PLL_P_MASK|MQ200_PLL_N_MASK|MQ200_PLL_M_MASK) 701 #define MQ200_PLL_TRIM_MASK 0xf0000000 702 #define MQ200_PLL_TRIM_SHIFT 28 703
Indexes created Tue Sep 23 20:09:58 GMT 2025