1 /* $NetBSD: rv770_dpm.h,v 1.3 2021/12/18 23:45:43 riastradh Exp $ */ 2 3 /* 4 * Copyright 2011 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 #ifndef __RV770_DPM_H__ 26 #define __RV770_DPM_H__ 27 28 #include "radeon.h" 29 #include "rv770_smc.h" 30 31 struct rv770_clock_registers { 32 u32 cg_spll_func_cntl; 33 u32 cg_spll_func_cntl_2; 34 u32 cg_spll_func_cntl_3; 35 u32 cg_spll_spread_spectrum; 36 u32 cg_spll_spread_spectrum_2; 37 u32 mpll_ad_func_cntl; 38 u32 mpll_ad_func_cntl_2; 39 u32 mpll_dq_func_cntl; 40 u32 mpll_dq_func_cntl_2; 41 u32 mclk_pwrmgt_cntl; 42 u32 dll_cntl; 43 u32 mpll_ss1; 44 u32 mpll_ss2; 45 }; 46 47 struct rv730_clock_registers { 48 u32 cg_spll_func_cntl; 49 u32 cg_spll_func_cntl_2; 50 u32 cg_spll_func_cntl_3; 51 u32 cg_spll_spread_spectrum; 52 u32 cg_spll_spread_spectrum_2; 53 u32 mclk_pwrmgt_cntl; 54 u32 dll_cntl; 55 u32 mpll_func_cntl; 56 u32 mpll_func_cntl2; 57 u32 mpll_func_cntl3; 58 u32 mpll_ss; 59 u32 mpll_ss2; 60 }; 61 62 union r7xx_clock_registers { 63 struct rv770_clock_registers rv770; 64 struct rv730_clock_registers rv730; 65 }; 66 67 struct vddc_table_entry { 68 u16 vddc; 69 u8 vddc_index; 70 u8 high_smio; 71 u32 low_smio; 72 }; 73 74 #define MAX_NO_OF_MVDD_VALUES 2 75 #define MAX_NO_VREG_STEPS 32 76 77 struct rv7xx_power_info { 78 /* flags */ 79 bool mem_gddr5; 80 bool pcie_gen2; 81 bool dynamic_pcie_gen2; 82 bool acpi_pcie_gen2; 83 bool boot_in_gen2; 84 bool voltage_control; /* vddc */ 85 bool mvdd_control; 86 bool sclk_ss; 87 bool mclk_ss; 88 bool dynamic_ss; 89 bool gfx_clock_gating; 90 bool mg_clock_gating; 91 bool mgcgtssm; 92 bool power_gating; 93 bool thermal_protection; 94 bool display_gap; 95 bool dcodt; 96 bool ulps; 97 /* registers */ 98 union r7xx_clock_registers clk_regs; 99 u32 s0_vid_lower_smio_cntl; 100 /* voltage */ 101 u32 vddc_mask_low; 102 u32 mvdd_mask_low; 103 u32 mvdd_split_frequency; 104 u32 mvdd_low_smio[MAX_NO_OF_MVDD_VALUES]; 105 u16 max_vddc; 106 u16 max_vddc_in_table; 107 u16 min_vddc_in_table; 108 struct vddc_table_entry vddc_table[MAX_NO_VREG_STEPS]; 109 u8 valid_vddc_entries; 110 /* dc odt */ 111 u32 mclk_odt_threshold; 112 u8 odt_value_0[2]; 113 u8 odt_value_1[2]; 114 /* stored values */ 115 u32 boot_sclk; 116 u16 acpi_vddc; 117 u32 ref_div; 118 u32 active_auto_throttle_sources; 119 u32 mclk_stutter_mode_threshold; 120 u32 mclk_strobe_mode_threshold; 121 u32 mclk_edc_enable_threshold; 122 u32 bsp; 123 u32 bsu; 124 u32 pbsp; 125 u32 pbsu; 126 u32 dsp; 127 u32 psp; 128 u32 asi; 129 u32 pasi; 130 u32 vrc; 131 u32 restricted_levels; 132 u32 rlp; 133 u32 rmp; 134 u32 lhp; 135 u32 lmp; 136 /* smc offsets */ 137 u16 state_table_start; 138 u16 soft_regs_start; 139 u16 sram_end; 140 /* scratch structs */ 141 RV770_SMC_STATETABLE smc_statetable; 142 }; 143 144 struct rv7xx_pl { 145 u32 sclk; 146 u32 mclk; 147 u16 vddc; 148 u16 vddci; /* eg+ only */ 149 u32 flags; 150 enum radeon_pcie_gen pcie_gen; /* si+ only */ 151 }; 152 153 struct rv7xx_ps { 154 struct rv7xx_pl high; 155 struct rv7xx_pl medium; 156 struct rv7xx_pl low; 157 bool dc_compatible; 158 }; 159 160 #define RV770_RLP_DFLT 10 161 #define RV770_RMP_DFLT 25 162 #define RV770_LHP_DFLT 25 163 #define RV770_LMP_DFLT 10 164 #define RV770_VRC_DFLT 0x003f 165 #define RV770_ASI_DFLT 1000 166 #define RV770_HASI_DFLT 200000 167 #define RV770_MGCGTTLOCAL0_DFLT 0x00100000 168 #define RV7XX_MGCGTTLOCAL0_DFLT 0 169 #define RV770_MGCGTTLOCAL1_DFLT 0xFFFF0000 170 #define RV770_MGCGCGTSSMCTRL_DFLT 0x55940000 171 172 #define MVDD_LOW_INDEX 0 173 #define MVDD_HIGH_INDEX 1 174 175 #define MVDD_LOW_VALUE 0 176 #define MVDD_HIGH_VALUE 0xffff 177 178 #define RV770_DEFAULT_VCLK_FREQ 53300 /* 10 khz */ 179 #define RV770_DEFAULT_DCLK_FREQ 40000 /* 10 khz */ 180 181 /* rv730/rv710 */ 182 int rv730_populate_sclk_value(struct radeon_device *rdev, 183 u32 engine_clock, 184 RV770_SMC_SCLK_VALUE *sclk); 185 int rv730_populate_mclk_value(struct radeon_device *rdev, 186 u32 engine_clock, u32 memory_clock, 187 LPRV7XX_SMC_MCLK_VALUE mclk); 188 void rv730_read_clock_registers(struct radeon_device *rdev); 189 int rv730_populate_smc_acpi_state(struct radeon_device *rdev, 190 RV770_SMC_STATETABLE *table); 191 int rv730_populate_smc_initial_state(struct radeon_device *rdev, 192 struct radeon_ps *radeon_initial_state, 193 RV770_SMC_STATETABLE *table); 194 void rv730_program_memory_timing_parameters(struct radeon_device *rdev, 195 struct radeon_ps *radeon_state); 196 void rv730_power_gating_enable(struct radeon_device *rdev, 197 bool enable); 198 void rv730_start_dpm(struct radeon_device *rdev); 199 void rv730_stop_dpm(struct radeon_device *rdev); 200 void rv730_program_dcodt(struct radeon_device *rdev, bool use_dcodt); 201 void rv730_get_odt_values(struct radeon_device *rdev); 202 203 /* rv740 */ 204 int rv740_populate_sclk_value(struct radeon_device *rdev, u32 engine_clock, 205 RV770_SMC_SCLK_VALUE *sclk); 206 int rv740_populate_mclk_value(struct radeon_device *rdev, 207 u32 engine_clock, u32 memory_clock, 208 RV7XX_SMC_MCLK_VALUE *mclk); 209 void rv740_read_clock_registers(struct radeon_device *rdev); 210 int rv740_populate_smc_acpi_state(struct radeon_device *rdev, 211 RV770_SMC_STATETABLE *table); 212 void rv740_enable_mclk_spread_spectrum(struct radeon_device *rdev, 213 bool enable); 214 u8 rv740_get_mclk_frequency_ratio(u32 memory_clock); 215 u32 rv740_get_dll_speed(bool is_gddr5, u32 memory_clock); 216 u32 rv740_get_decoded_reference_divider(u32 encoded_ref); 217 218 /* rv770 */ 219 u32 rv770_map_clkf_to_ibias(struct radeon_device *rdev, u32 clkf); 220 int rv770_populate_vddc_value(struct radeon_device *rdev, u16 vddc, 221 RV770_SMC_VOLTAGE_VALUE *voltage); 222 int rv770_populate_mvdd_value(struct radeon_device *rdev, u32 mclk, 223 RV770_SMC_VOLTAGE_VALUE *voltage); 224 u8 rv770_get_seq_value(struct radeon_device *rdev, 225 struct rv7xx_pl *pl); 226 int rv770_populate_initial_mvdd_value(struct radeon_device *rdev, 227 RV770_SMC_VOLTAGE_VALUE *voltage); 228 u32 rv770_calculate_memory_refresh_rate(struct radeon_device *rdev, 229 u32 engine_clock); 230 void rv770_program_response_times(struct radeon_device *rdev); 231 int rv770_populate_smc_sp(struct radeon_device *rdev, 232 struct radeon_ps *radeon_state, 233 RV770_SMC_SWSTATE *smc_state); 234 int rv770_populate_smc_t(struct radeon_device *rdev, 235 struct radeon_ps *radeon_state, 236 RV770_SMC_SWSTATE *smc_state); 237 void rv770_read_voltage_smio_registers(struct radeon_device *rdev); 238 void rv770_get_memory_type(struct radeon_device *rdev); 239 void r7xx_start_smc(struct radeon_device *rdev); 240 u8 rv770_get_memory_module_index(struct radeon_device *rdev); 241 void rv770_get_max_vddc(struct radeon_device *rdev); 242 void rv770_get_pcie_gen2_status(struct radeon_device *rdev); 243 void rv770_enable_acpi_pm(struct radeon_device *rdev); 244 void rv770_restore_cgcg(struct radeon_device *rdev); 245 bool rv770_dpm_enabled(struct radeon_device *rdev); 246 void rv770_enable_voltage_control(struct radeon_device *rdev, 247 bool enable); 248 void rv770_enable_backbias(struct radeon_device *rdev, 249 bool enable); 250 void rv770_enable_thermal_protection(struct radeon_device *rdev, 251 bool enable); 252 void rv770_enable_auto_throttle_source(struct radeon_device *rdev, 253 enum radeon_dpm_auto_throttle_src source, 254 bool enable); 255 void rv770_setup_bsp(struct radeon_device *rdev); 256 void rv770_program_git(struct radeon_device *rdev); 257 void rv770_program_tp(struct radeon_device *rdev); 258 void rv770_program_tpp(struct radeon_device *rdev); 259 void rv770_program_sstp(struct radeon_device *rdev); 260 void rv770_program_engine_speed_parameters(struct radeon_device *rdev); 261 void rv770_program_vc(struct radeon_device *rdev); 262 void rv770_clear_vc(struct radeon_device *rdev); 263 int rv770_upload_firmware(struct radeon_device *rdev); 264 void rv770_stop_dpm(struct radeon_device *rdev); 265 void r7xx_stop_smc(struct radeon_device *rdev); 266 void rv770_reset_smio_status(struct radeon_device *rdev); 267 int rv770_restrict_performance_levels_before_switch(struct radeon_device *rdev); 268 int rv770_dpm_force_performance_level(struct radeon_device *rdev, 269 enum radeon_dpm_forced_level level); 270 int rv770_halt_smc(struct radeon_device *rdev); 271 int rv770_resume_smc(struct radeon_device *rdev); 272 int rv770_set_sw_state(struct radeon_device *rdev); 273 int rv770_set_boot_state(struct radeon_device *rdev); 274 int rv7xx_parse_power_table(struct radeon_device *rdev); 275 void rv770_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev, 276 struct radeon_ps *new_ps, 277 struct radeon_ps *old_ps); 278 void rv770_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev, 279 struct radeon_ps *new_ps, 280 struct radeon_ps *old_ps); 281 void rv770_get_engine_memory_ss(struct radeon_device *rdev); 282 283 /* smc */ 284 int rv770_write_smc_soft_register(struct radeon_device *rdev, 285 u16 reg_offset, u32 value); 286 287 #endif 288
Indexes created Sat Sep 27 22:09:54 GMT 2025