1 /* $NetBSD: mvgbereg.h,v 1.10 2024/02/02 22:39:10 andvar Exp $ */ 2 /* 3 * Copyright (c) 2007, 2013 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 #ifndef _MVGBEREG_H_ 28 #define _MVGBEREG_H_ 29 30 /* 31 * For ARMEB, peripheral is configured to little-endian mode, even if 32 * CPU itself is in big-endian mode... 33 */ 34 35 #if BYTE_ORDER == BIG_ENDIAN && !defined(__arm__) 36 #define MVGBE_BIG_ENDIAN 37 #endif 38 39 /* 40 * ... therefore, we need byte-swapping descriptor fields. 41 */ 42 43 #if BYTE_ORDER == BIG_ENDIAN && defined(__arm__) 44 #define H2MVGBE16(x) htole16(x) 45 #define H2MVGBE32(x) htole32(x) 46 #define MVGBE2H16(x) le16toh(x) 47 #define MVGBE2H32(x) le32toh(x) 48 #else 49 #define H2MVGBE16(x) (x) 50 #define H2MVGBE32(x) (x) 51 #define MVGBE2H16(x) (x) 52 #define MVGBE2H32(x) (x) 53 #endif 54 55 #define MVGBE_SIZE 0x4000 56 57 #define MVGBE_NWINDOW 6 58 #define MVGBE_NREMAP 4 59 60 #define MVGBE_PHY_TIMEOUT 10000 /* msec */ 61 62 /* 63 * Ethernet Unit Registers 64 */ 65 66 #define MVGBE_PRXC(q) (0x1400 + ((q) << 2)) /*Port RX queues Config*/ 67 #define MVGBE_PRXSNP(q) (0x1420 + ((q) << 2)) /* Port RX queues Snoop */ 68 #define MVGBE_PRXF01(q) (0x1440 + ((q) << 2)) /* Port RX Prefetch 0_1 */ 69 #define MVGBE_PRXF23(q) (0x1460 + ((q) << 2)) /* Port RX Prefetch 2_3 */ 70 #define MVGBE_PRXDQA(q) (0x1480 + ((q) << 2)) /*P RXqueues desc Q Addr*/ 71 #define MVGBE_PRXDQS(q) (0x14a0 + ((q) << 2)) /*P RXqueues desc Q Size*/ 72 #define MVGBE_PRXDQTH(q) (0x14c0 + ((q) << 2)) /*P RXqueues desc Q Thrs*/ 73 #define MVGBE_PRXS(q) (0x14e0 + ((q) << 2)) /*Port RX queues Status */ 74 #define MVGBE_PRXSU(q) (0x1500 + ((q) << 2)) /*P RXqueues Stat Update*/ 75 #define MVGBE_PPLBSZ(q) (0x1700 + ((q) << 2)) /* P Pool n Buffer Size */ 76 #define MVGBE_PRXFC 0x1710 /* Port RX Flow Control */ 77 #define MVGBE_PRXTXP 0x1714 /* Port RX_TX Pause */ 78 #define MVGBE_PRXFCG 0x1718 /* Port RX Flow Control Generation */ 79 #define MVGBE_PRXINIT 0x1cc0 /* Port RX Initialization */ 80 #define MVGBE_RXCTRL 0x1d00 /* RX Control */ 81 #define MVGBE_RXHWFWD(n) (0x1d10 + (((n) & ~0x1) << 1)) 82 /* RX Hardware Forwarding (0_1, 2_3,..., 8_9) */ 83 #define MVGBE_RXHWFWDPTR 0x1d30 /* RX Hardware Forwarding Pointer */ 84 #define MVGBE_RXHWFWDTH 0x1d40 /* RX Hardware Forwarding Threshold */ 85 #define MVGBE_RXHWFWDDQA 0x1d44 /* RX Hw Fwd Descriptors Queue Address*/ 86 #define MVGBE_RXHWFWDQS 0x1d48 /* RX Hw Fwd Descriptors Queue Size */ 87 #define MVGBE_RXHWFWDQENB 0x1d4c /* RX Hw Fwd Queue Enable */ 88 #define MVGBE_RXHWFWDACPT 0x1d50 /* RX Hw Forwarding Accepted Counter */ 89 #define MVGBE_RXHWFWDYDSCRD 0x1d54 /* RX Hw Fwd Yellow Discarded Counter */ 90 #define MVGBE_RXHWFWDGDSCRD 0x1d58 /* RX Hw Fwd Green Discarded Counter */ 91 #define MVGBE_RXHWFWDTHDSCRD 0x1d5c /*RX HwFwd Threshold Discarded Counter*/ 92 #define MVGBE_RXHWFWDTXGAP 0x1d6c /*RX Hardware Forwarding TX Access Gap*/ 93 94 /* Ethernet Unit Global Registers */ 95 #define MVGBE_PHYADDR 0x2000 96 #if defined(MV88W8660) 97 #define MVGBE_SMI 0x8010 98 #else 99 #define MVGBE_SMI 0x2004 100 #endif 101 #define MVGBE_EUDA 0x2008 /* Ethernet Unit Default Address */ 102 #define MVGBE_EUDID 0x200c /* Ethernet Unit Default ID */ 103 #define MVGBE_EU 0x2014 /* Ethernet Unit Reserved */ 104 #define MVGBE_EUIC 0x2080 /* Ethernet Unit Interrupt Cause */ 105 #define MVGBE_EUIM 0x2084 /* Ethernet Unit Interrupt Mask */ 106 #define MVGBE_EUEA 0x2094 /* Ethernet Unit Error Address */ 107 #define MVGBE_EUIAE 0x2098 /* Ethernet Unit Internal Addr Error */ 108 #define MVGBE_EUPCR 0x20a0 /* EthernetUnit Port Pads Calibration */ 109 #define MVGBE_EUC 0x20b0 /* Ethernet Unit Control */ 110 111 #define MVGBE_BASEADDR(n) (0x2200 + ((n) << 3)) /* Base Address */ 112 #define MVGBE_S(n) (0x2204 + ((n) << 3)) /* Size */ 113 #define MVGBE_HA(n) (0x2280 + ((n) << 2)) /* High Address Remap */ 114 #define MVGBE_BARE 0x2290 /* Base Address Enable */ 115 #define MVGBE_EPAP 0x2294 /* Ethernet Port Access Protect */ 116 117 /* Ethernet Unit Port Registers */ 118 #define MVGBE_PORTR_BASE 0x2400 119 #define MVGBE_PORTR_SIZE 0x400 120 121 #define MVGBE_PXC 0x000 /* Port Configuration */ 122 #define MVGBE_PXCX 0x004 /* Port Configuration Extend */ 123 #define MVGBE_MIISP 0x008 /* MII Serial Parameters */ 124 #define MVGBE_GMIISP 0x00c /* GMII Serial Params */ 125 #define MVGBE_EVLANE 0x010 /* VLAN EtherType */ 126 #define MVGBE_MACAL 0x014 /* MAC Address Low */ 127 #define MVGBE_MACAH 0x018 /* MAC Address High */ 128 #define MVGBE_SDC 0x01c /* SDMA Configuration */ 129 #define MVGBE_DSCP(n) (0x020 + ((n) << 2)) 130 #define MVGBE_PSC 0x03c /* Port Serial Control0 */ 131 #define MVGBE_VPT2P 0x040 /* VLAN Priority Tag to Priority */ 132 #define MVGBE_PS 0x044 /* Ethernet Port Status */ 133 #define MVGBE_TQC 0x048 /* Transmit Queue Command */ 134 #define MVGBE_PSC1 0x04c /* Port Serial Control1 */ 135 #define MVGBE_MH 0x054 /* Marvell Header */ 136 #define MVGBE_MTU 0x058 /* Max Transmit Unit */ 137 #define MVGBE_IC 0x060 /* Port Interrupt Cause */ 138 #define MVGBE_ICE 0x064 /* Port Interrupt Cause Extend */ 139 #define MVGBE_PIM 0x068 /* Port Interrupt Mask */ 140 #define MVGBE_PEIM 0x06c /* Port Extend Interrupt Mask */ 141 #define MVGBE_PRFUT 0x070 /* Port Rx FIFO Urgent Threshold */ 142 #define MVGBE_PTFUT 0x074 /* Port Tx FIFO Urgent Threshold */ 143 #define MVGBE_PXTFTT 0x078 /* Port Tx FIFO Threshold */ 144 #define MVGBE_PMFS 0x07c /* Port Rx Minimal Frame Size */ 145 #define MVGBE_PXDFC 0x084 /* Port Rx Discard Frame Counter */ 146 #define MVGBE_POFC 0x088 /* Port Overrun Frame Counter */ 147 #define MVGBE_PIAE 0x094 /* Port Internal Address Error */ 148 #define MVGBE_AIP0ADR 0x098 /* Arp IP0 Address */ 149 #define MVGBE_AIP1ADR 0x09c /* Arp IP1 Address */ 150 #define MVGBE_SERDESCFG 0x0a0 /* Serdes Configuration */ 151 #define MVGBE_SERDESSTS 0x0a4 /* Serdes Status */ 152 #define MVGBE_ETP 0x0bc /* Ethernet Type Priority */ 153 #define MVGBE_TQFPC 0x0dc /* Transmit Queue Fixed Priority Cfg */ 154 #define MVGBE_OMSCD 0x0f4 /* One mS Clock Divider */ 155 #define MVGBE_PFCCD 0x0f8 /* Periodic Flow Control Clock Divider*/ 156 #define MVGBE_PACC 0x100 /* Port Acceleration Mode */ 157 #define MVGBE_PBMADDR 0x104 /* Port BM Address */ 158 #define MVGBE_PV 0x1bc /* Port Version */ 159 #define MVGBE_CRDP(n) (0x20c + ((n) << 4)) 160 /* Ethernet Current Receive Descriptor Pointers */ 161 #define MVGBE_RQC 0x280 /* Receive Queue Command */ 162 #define MVGBE_TCSDP 0x284 /* Tx Current Served Desc Pointer */ 163 #define MVGBE_TCQDP 0x2c0 /* Tx Current Queue Desc Pointer */ 164 #define MVGBE_TQTBCOUNT(q) (0x300 + ((q) << 4)) 165 /* Transmit Queue Token-Bucket Counter */ 166 #define MVGBE_TQTBCONFIG(q) (0x304 + ((q) << 4)) 167 /* Transmit Queue Token-Bucket Configuration */ 168 #define MVGBE_TQAC(q) (0x308 + ((q) << 4)) 169 /* Transmit Queue Arbiter Configuration */ 170 171 #define MVGBE_PCP2Q(cpu) (0x2540 + ((cpu) << 2)) /* Port CPUn to Queue */ 172 #define MVGBE_PRXITTH(q) (0x2540 + ((q) << 2) /* Port RX Intr Threshold*/ 173 #define MVGBE_PRXTXTIC 0x25a0 /*Port RX_TX Threshold Interrupt Cause*/ 174 #define MVGBE_PRXTXTIM 0x25a4 /*Port RX_TX Threshold Interrupt Mask */ 175 #define MVGBE_PRXTXIC 0x25a8 /* Port RX_TX Interrupt Cause */ 176 #define MVGBE_PRXTXIM 0x25ac /* Port RX_TX Interrupt Mask */ 177 #define MVGBE_PMIC 0x25b0 /* Port Misc Interrupt Cause */ 178 #define MVGBE_PMIM 0x25b4 /* Port Misc Interrupt Mask */ 179 #define MVGBE_PIE 0x25b8 /* Port Interrupt Enable */ 180 181 #define MVGBE_PMACC0 0x2c00 /* Port MAC Control 0 */ 182 #define MVGBE_PMACC1 0x2c04 /* Port MAC Control 1 */ 183 #define MVGBE_PMACC2 0x2c08 /* Port MAC Control 2 */ 184 #define MVGBE_PANC 0x2c0c /* Port Auto-Negotiation Configuration*/ 185 #define MVGBE_PS0 0x2c10 /* Port Status 0 */ 186 #define MVGBE_PSPC 0x2c14 /* Port Serial Parameters Config */ 187 #define MVGBE_PIC_2 0x2c20 /* Port Interrupt Cause */ 188 #define MVGBE_PIM_2 0x2c24 /* Port Interrupt Mask */ 189 #define MVGBE_PPRBSS 0x2c38 /* Port PRBS Status */ 190 #define MVGBE_PPRBSEC 0x2c3c /* Port PRBS Error Counter */ 191 #define MVGBE_PMACC3 0x2c48 /* Port MAC Control 3 */ 192 #define MVGBE_CCFCPST(p) (0x2c58 + ((p) << 2)) /*CCFC Port Speed Timerp*/ 193 #define MVGBE_PMACC4 0x2c90 /* Port MAC Control 4 */ 194 #define MVGBE_PSP1C 0x2c94 /* Port Serial Parameters 1 Config */ 195 #define MVGBE_LPIC0 0x2cc0 /* LowPowerIdle control 0 */ 196 #define MVGBE_LPIC1 0x2cc4 /* LPI control 1 */ 197 #define MVGBE_LPIC2 0x2cc8 /* LPI control 2 */ 198 #define MVGBE_LPIS 0x2ccc /* LPI status */ 199 #define MVGBE_LPIC 0x2cd0 /* LPI counter */ 200 201 #define MVGBE_PPLLC 0x2e04 /* Power and PLL Control */ 202 #define MVGBE_DLE 0x2e8c /* Digital Loopback Enable */ 203 #define MVGBE_RCS 0x2f18 /* Reference Clock Select */ 204 205 /* MAC MIB Counters 0x3000 - 0x307c */ 206 207 /* Rx DMA Wake on LAN Registers 0x3690 - 0x36b8 */ 208 209 #define MVGBE_PORTDAFR_BASE 0x3400 210 #define MVGBE_PORTDAFR_SIZE 0x400 211 212 #define MVGBE_NDFSMT 0x40 213 #define MVGBE_DFSMT 0x000 214 /* Destination Address Filter Special Multicast Table */ 215 #define MVGBE_NDFOMT 0x40 216 #define MVGBE_DFOMT 0x100 217 /* Destination Address Filter Other Multicast Table */ 218 #define MVGBE_NDFUT 0x4 219 #define MVGBE_DFUT 0x200 220 /* Destination Address Filter Unicast Table */ 221 222 #define MVGBE_PTXDQA(q) (0x3c00 + ((q) << 2)) /*P TXqueues desc Q Addr*/ 223 #define MVGBE_PTXDQS(q) (0x3c20 + ((q) << 2)) /*P TXqueues desc Q Size*/ 224 #define MVGBE_PTXS(q) (0x3c40 + ((q) << 2)) /* Port TX queues Status*/ 225 #define MVGBE_PTXSU(q) (0x3c60 + ((q) << 2)) /*P TXqueues Stat Update*/ 226 #define MVGBE_PTXDI(q) (0x3c80 + ((q) << 2)) /* P TXqueues Desc Index*/ 227 #define MVGBE_TXTBC(q) (0x3ca0 + ((q) << 2)) /* TX Trans-ed Buf Count*/ 228 #define MVGBE_PTXINIT 0x3cf0 /* Port TX Initialization */ 229 #define MVGBE_PTXDOSD 0x3cf4 /* Port TX Disable Outstanding Reads */ 230 231 #define MVGBE_TXBADFCS 0x3cc0 /*Tx Bad FCS Transmitted Pckts Counter*/ 232 #define MVGBE_TXDROPPED 0x3cc4 /* Tx Dropped Packets Counter */ 233 #define MVGBE_TXNB 0x3cfc /* Tx Number of New Bytes */ 234 #define MVGBE_TXGB 0x3d00 /* Tx Green Number of Bytes */ 235 #define MVGBE_TXYB 0x3d04 /* Tx Yellow Number of Bytes */ 236 237 /* Tx DMA Packet Modification Registers 0x3d00 - 0x3dff */ 238 239 /* Tx DMA Queue Arbiter Registers 0x3e00 - 0x3eff */ 240 241 242 /* PHY Address (MVGBE_PHYADDR) */ 243 #define MVGBE_PHYADDR_PHYAD_MASK 0x1f 244 #define MVGBE_PHYADDR_PHYAD(port, phy) ((phy) << ((port) * 5)) 245 246 /* SMI register fields (MVGBE_SMI) */ 247 #define MVGBE_SMI_DATA_MASK 0x0000ffff 248 #define MVGBE_SMI_PHYAD(phy) (((phy) & 0x1f) << 16) 249 #define MVGBE_SMI_REGAD(reg) (((reg) & 0x1f) << 21) 250 #define MVGBE_SMI_OPCODE_WRITE (0 << 26) 251 #define MVGBE_SMI_OPCODE_READ (1 << 26) 252 #define MVGBE_SMI_READVALID (1 << 27) 253 #define MVGBE_SMI_BUSY (1 << 28) 254 255 /* Ethernet Unit Default ID (MVGBE_EUDID) */ 256 #define MVGBE_EUDID_DIDR_MASK 0x0000000f 257 #define MVGBE_EUDID_DATTR_MASK 0x00000ff0 258 259 /* Ethernet Unit Reserved (MVGBE_EU) */ 260 #define MVGBE_EU_FASTMDC (1 << 0) 261 #define MVGBE_EU_ACCS (1 << 1) 262 263 /* Ethernet Unit Interrupt Cause (MVGBE_EUIC) */ 264 #define MVGBE_EUIC_ETHERINTSUM (1 << 0) 265 #define MVGBE_EUIC_PARITY (1 << 1) 266 #define MVGBE_EUIC_ADDRVIOL (1 << 2) 267 #define MVGBE_EUIC_ADDRVNOMATCH (1 << 3) 268 #define MVGBE_EUIC_SMIDONE (1 << 4) 269 #define MVGBE_EUIC_COUNTWA (1 << 5) 270 #define MVGBE_EUIC_INTADDRERR (1 << 7) 271 #define MVGBE_EUIC_PORT0DPERR (1 << 9) 272 #define MVGBE_EUIC_TOPDPERR (1 << 12) 273 274 /* Ethernet Unit Internal Addr Error (MVGBE_EUIAE) */ 275 #define MVGBE_EUIAE_INTADDR_MASK 0x000001ff 276 277 /* Ethernet Unit Port Pads Calibration (MVGBE_EUPCR) */ 278 #define MVGBE_EUPCR_DRVN_MASK 0x0000001f 279 #define MVGBE_EUPCR_TUNEEN (1 << 16) 280 #define MVGBE_EUPCR_LOCKN_MASK 0x003e0000 281 #define MVGBE_EUPCR_OFFSET_MASK 0x1f000000 /* Reserved */ 282 #define MVGBE_EUPCR_WREN (1 << 31) 283 284 /* Ethernet Unit Control (MVGBE_EUC) */ 285 #define MVGBE_EUC_PORT0DPPAR (1 << 0) 286 #define MVGBE_EUC_POLLING (1 << 1) 287 #define MVGBE_EUC_TOPDPPAR (1 << 3) 288 #define MVGBE_EUC_PORT0PW (1 << 16) 289 #define MVGBE_EUC_PORTRESET (1 << 24) 290 #define MVGBE_EUC_RAMSINITIALIZATIONCOMPLETED (1 << 25) 291 292 /* Base Address (MVGBE_BASEADDR) */ 293 #define MVGBE_BASEADDR_TARGET(target) ((target) & 0xf) 294 #define MVGBE_BASEADDR_ATTR(attr) (((attr) & 0xff) << 8) 295 #define MVGBE_BASEADDR_BASE(base) ((base) & 0xffff0000) 296 297 /* Size (MVGBE_S) */ 298 #define MVGBE_S_SIZE(size) (((size) - 1) & 0xffff0000) 299 300 /* Base Address Enable (MVGBE_BARE) */ 301 #define MVGBE_BARE_EN_MASK ((1 << MVGBE_NWINDOW) - 1) 302 #define MVGBE_BARE_EN(win) ((1 << (win)) & MVGBE_BARE_EN_MASK) 303 304 /* Ethernet Port Access Protect (MVGBE_EPAP) */ 305 #define MVGBE_EPAP_AC_NAC 0x0 /* No access allowed */ 306 #define MVGBE_EPAP_AC_RO 0x1 /* Read Only */ 307 #define MVGBE_EPAP_AC_FA 0x3 /* Full access (r/w) */ 308 #define MVGBE_EPAP_EPAR(win, ac) ((ac) << ((win) * 2)) 309 310 /* Port Configuration (MVGBE_PXC) */ 311 #define MVGBE_PXC_UPM (1 << 0) /* Uni Promisc mode */ 312 #define MVGBE_PXC_RXQ(q) ((q) << 1) 313 #define MVGBE_PXC_RXQ_MASK MVGBE_PXC_RXQ(7) 314 #define MVGBE_PXC_RXQARP(q) ((q) << 4) 315 #define MVGBE_PXC_RXQARP_MASK MVGBE_PXC_RXQARP(7) 316 #define MVGBE_PXC_RB (1 << 7) /* Rej mode of MAC */ 317 #define MVGBE_PXC_RBIP (1 << 8) 318 #define MVGBE_PXC_RBARP (1 << 9) 319 #define MVGBE_PXC_AMNOTXES (1 << 12) 320 #define MVGBE_PXC_RBARPF (1 << 13) 321 #define MVGBE_PXC_TCPCAPEN (1 << 14) 322 #define MVGBE_PXC_UDPCAPEN (1 << 15) 323 #define MVGBE_PXC_TCPQ(q) ((q) << 16) 324 #define MVGBE_PXC_TCPQ_MASK MVGBE_PXC_TCPQ(7) 325 #define MVGBE_PXC_UDPQ(q) ((q) << 19) 326 #define MVGBE_PXC_UDPQ_MASK MVGBE_PXC_UDPQ(7) 327 #define MVGBE_PXC_BPDUQ(q) ((q) << 22) 328 #define MVGBE_PXC_BPDUQ_MASK MVGBE_PXC_BPDUQ(7) 329 #define MVGBE_PXC_RXCS (1 << 25) 330 331 /* Port Configuration Extend (MVGBE_PXCX) */ 332 #define MVGBE_PXCX_SPAN (1 << 1) 333 #define MVGBE_PXCX_TXCRCDIS (1 << 3) 334 335 /* MII Serial Parameters (MVGBE_MIISP) */ 336 #define MVGBE_MIISP_JAMLENGTH_12KBIT 0x00000000 337 #define MVGBE_MIISP_JAMLENGTH_24KBIT 0x00000001 338 #define MVGBE_MIISP_JAMLENGTH_32KBIT 0x00000002 339 #define MVGBE_MIISP_JAMLENGTH_48KBIT 0x00000003 340 #define MVGBE_MIISP_JAMIPG(x) (((x) & 0x7c) << 0) 341 #define MVGBE_MIISP_IPGJAMTODATA(x) (((x) & 0x7c) << 5) 342 #define MVGBE_MIISP_IPGDATA(x) (((x) & 0x7c) << 10) 343 #define MVGBE_MIISP_DATABLIND(x) (((x) & 0x1f) << 17) 344 345 /* GMII Serial Parameters (MVGBE_GMIISP) */ 346 #define MVGBE_GMIISP_IPGDATA(x) (((x) >> 4) & 0x7) 347 348 /* SDMA Configuration (MVGBE_SDC) */ 349 #define MVGBE_SDC_RIFB (1 << 0) 350 #define MVGBE_SDC_RXBSZ(x) ((x) << 1) 351 #define MVGBE_SDC_RXBSZ_MASK MVGBE_SDC_RXBSZ(7) 352 #define MVGBE_SDC_RXBSZ_1_64BITWORDS MVGBE_SDC_RXBSZ(0) 353 #define MVGBE_SDC_RXBSZ_2_64BITWORDS MVGBE_SDC_RXBSZ(1) 354 #define MVGBE_SDC_RXBSZ_4_64BITWORDS MVGBE_SDC_RXBSZ(2) 355 #define MVGBE_SDC_RXBSZ_8_64BITWORDS MVGBE_SDC_RXBSZ(3) 356 #define MVGBE_SDC_RXBSZ_16_64BITWORDS MVGBE_SDC_RXBSZ(4) 357 #define MVGBE_SDC_BLMR (1 << 4) 358 #define MVGBE_SDC_BLMT (1 << 5) 359 #define MVGBE_SDC_SWAPMODE (1 << 6) 360 #define MVGBE_SDC_IPGINTRX_V1_MASK __BITS(21, 8) 361 #define MVGBE_SDC_IPGINTRX_V2_MASK (__BIT(25) | __BITS(21, 7)) 362 #define MVGBE_SDC_IPGINTRX_V1(x) (((x) << 4) \ 363 & MVGBE_SDC_IPGINTRX_V1_MASK) 364 #define MVGBE_SDC_IPGINTRX_V2(x) ((((x) & 0x8000) << 10) \ 365 | (((x) & 0x7fff) << 7)) 366 #define MVGBE_SDC_IPGINTRX_V1_MAX 0x3fff 367 #define MVGBE_SDC_IPGINTRX_V2_MAX 0xffff 368 #define MVGBE_SDC_TXBSZ(x) ((x) << 22) 369 #define MVGBE_SDC_TXBSZ_MASK MVGBE_SDC_TXBSZ(7) 370 #define MVGBE_SDC_TXBSZ_1_64BITWORDS MVGBE_SDC_TXBSZ(0) 371 #define MVGBE_SDC_TXBSZ_2_64BITWORDS MVGBE_SDC_TXBSZ(1) 372 #define MVGBE_SDC_TXBSZ_4_64BITWORDS MVGBE_SDC_TXBSZ(2) 373 #define MVGBE_SDC_TXBSZ_8_64BITWORDS MVGBE_SDC_TXBSZ(3) 374 #define MVGBE_SDC_TXBSZ_16_64BITWORDS MVGBE_SDC_TXBSZ(4) 375 376 /* Port Serial Control (MVGBE_PSC) */ 377 #define MVGBE_PSC_PORTEN (1 << 0) 378 #define MVGBE_PSC_FLP (1 << 1) /* Force_Link_Pass */ 379 #define MVGBE_PSC_ANDUPLEX (1 << 2) /* auto nego */ 380 #define MVGBE_PSC_ANFC (1 << 3) 381 #define MVGBE_PSC_PAUSEADV (1 << 4) 382 #define MVGBE_PSC_FFCMODE (1 << 5) /* Force FC */ 383 #define MVGBE_PSC_FBPMODE (1 << 7) /* Back pressure */ 384 #define MVGBE_PSC_RESERVED (1 << 9) /* Must be set to 1 */ 385 #define MVGBE_PSC_FLFAIL (1 << 10) /* Force Link Fail */ 386 #define MVGBE_PSC_ANSPEED (1 << 13) 387 #define MVGBE_PSC_DTEADVERT (1 << 14) 388 #define MVGBE_PSC_MRU(x) ((x) << 17) 389 #define MVGBE_PSC_MRU_MASK MVGBE_PSC_MRU(7) 390 #define MVGBE_PSC_MRU_1518 0 391 #define MVGBE_PSC_MRU_1522 1 392 #define MVGBE_PSC_MRU_1552 2 393 #define MVGBE_PSC_MRU_9022 3 394 #define MVGBE_PSC_MRU_9192 4 395 #define MVGBE_PSC_MRU_9700 5 396 #define MVGBE_PSC_SETFULLDX (1 << 21) 397 #define MVGBE_PSC_SETFCEN (1 << 22) 398 #define MVGBE_PSC_SETGMIISPEED (1 << 23) 399 #define MVGBE_PSC_SETMIISPEED (1 << 24) 400 401 /* Ethernet Port Status (MVGBE_PS) */ 402 #define MVGBE_PS_LINKUP (1 << 1) 403 #define MVGBE_PS_FULLDX (1 << 2) 404 #define MVGBE_PS_ENFC (1 << 3) 405 #define MVGBE_PS_GMIISPEED (1 << 4) 406 #define MVGBE_PS_MIISPEED (1 << 5) 407 #define MVGBE_PS_TXINPROG (1 << 7) 408 #define MVGBE_PS_TXFIFOEMP (1 << 10) /* FIFO Empty */ 409 #define MVGBE_PS_RXFIFOEMPTY (1 << 16) 410 /* Armada XP */ 411 #define MVGBE_PS_TXINPROG_MASK (0xff << 0) 412 #define MVGBE_PS_TXINPROG_(q) (1 << ((q) + 0)) 413 #define MVGBE_PS_TXFIFOEMP_MASK (0xff << 8) 414 #define MVGBE_PS_TXFIFOEMP_(q) (1 << ((q) + 8)) 415 416 /* Transmit Queue Command (MVGBE_TQC) */ 417 #define MVGBE_TQC_ENQ(q) (1 << ((q) + 0))/* Enable Q */ 418 #define MVGBE_TQC_DISQ(q) (1 << ((q) + 8))/* Disable Q */ 419 420 /* Port Serial Control 1 (MVGBE_PSC1) */ 421 #define MVGBE_PSC1_PCSLB (1 << 1) 422 #define MVGBE_PSC1_RGMIIEN (1 << 3) /* RGMII */ 423 #define MVGBE_PSC1_PRST (1 << 4) /* Port Reset */ 424 425 /* Port Interrupt Cause (MVGBE_IC) */ 426 #define MVGBE_IC_RXBUF (1 << 0) 427 #define MVGBE_IC_EXTEND (1 << 1) 428 #define MVGBE_IC_RXBUFQ_MASK (0xff << 2) 429 #define MVGBE_IC_RXBUFQ(q) (1 << ((q) + 2)) 430 #define MVGBE_IC_RXERROR (1 << 10) 431 #define MVGBE_IC_RXERRQ_MASK (0xff << 11) 432 #define MVGBE_IC_RXERRQ(q) (1 << ((q) + 11)) 433 #define MVGBE_IC_TXEND(q) (1 << ((q) + 19)) 434 #define MVGBE_IC_ETHERINTSUM (1 << 31) 435 436 /* Port Interrupt Cause Extend (MVGBE_ICE) */ 437 #define MVGBE_ICE_TXBUF_MASK (0xff << + 0) 438 #define MVGBE_ICE_TXBUF(q) (1 << ((q) + 0)) 439 #define MVGBE_ICE_TXERR_MASK (0xff << + 8) 440 #define MVGBE_ICE_TXERR(q) (1 << ((q) + 8)) 441 #define MVGBE_ICE_PHYSTC (1 << 16) 442 #define MVGBE_ICE_PTP (1 << 17) 443 #define MVGBE_ICE_RXOVR (1 << 18) 444 #define MVGBE_ICE_TXUDR (1 << 19) 445 #define MVGBE_ICE_LINKCHG (1 << 20) 446 #define MVGBE_ICE_SERDESREALIGN (1 << 21) 447 #define MVGBE_ICE_INTADDRERR (1 << 23) 448 #define MVGBE_ICE_SYNCCHANGED (1 << 24) 449 #define MVGBE_ICE_PRBSERROR (1 << 25) 450 #define MVGBE_ICE_ETHERINTSUM (1 << 31) 451 452 /* Port Tx FIFO Urgent Threshold (MVGBE_PTFUT) */ 453 #define MVGBE_PTFUT_IPGINTTX_V1_MASK __BITS(17, 4) 454 #define MVGBE_PTFUT_IPGINTTX_V2_MASK __BITS(19, 4) 455 #define MVGBE_PTFUT_IPGINTTX_V1(x) __SHIFTIN(x, MVGBE_PTFUT_IPGINTTX_V1_MASK) 456 #define MVGBE_PTFUT_IPGINTTX_V2(x) __SHIFTIN(x, MVGBE_PTFUT_IPGINTTX_V2_MASK) 457 #define MVGBE_PTFUT_IPGINTTX_V1_MAX 0x3fff 458 #define MVGBE_PTFUT_IPGINTTX_V2_MAX 0xffff 459 460 /* Port Rx Minimal Frame Size (MVGBE_PMFS) */ 461 #define MVGBE_PMFS_RXMFS(rxmfs) (((rxmfs) - 40) & 0x7c) 462 /* RxMFS = 40,44,48,52,56,60,64 bytes */ 463 464 /* Transmit Queue Fixed Priority Configuration */ 465 #define MVGBE_TQFPC_EN(q) (1 << (q)) 466 467 /* Receive Queue Command (MVGBE_RQC) */ 468 #define MVGBE_RQC_ENQ_MASK (0xff << 0) /* Enable Q */ 469 #define MVGBE_RQC_ENQ(n) (1 << (0 + (n))) 470 #define MVGBE_RQC_DISQ_MASK (0xff << 8) /* Disable Q */ 471 #define MVGBE_RQC_DISQ(n) (1 << (8 + (n))) 472 #define MVGBE_RQC_DISQ_DISABLE(q) ((q) << 8) 473 474 /* Destination Address Filter Registers (MVGBE_DF{SM,OM,U}T) */ 475 #define MVGBE_DF(n, x) ((x) << (8 * (n))) 476 #define MVGBE_DF_PASS (1 << 0) 477 #define MVGBE_DF_QUEUE(q) ((q) << 1) 478 #define MVGBE_DF_QUEUE_MASK ((7) << 1) 479 480 481 /* Port Acceleration Mode (MVGBE_PACC) */ 482 #define MVGVE_PACC_ACCELERATIONMODE_MASK 0x7 483 #define MVGVE_PACC_ACCELERATIONMODE_BM 0x0 /* Basic Mode */ 484 #define MVGVE_PACC_ACCELERATIONMODE_EDM 0x1 /* Enhanced Desc Mode */ 485 #define MVGVE_PACC_ACCELERATIONMODE_EDMBM 0x2 /* with BM */ 486 #define MVGVE_PACC_ACCELERATIONMODE_EDMPNC 0x3 /* with PnC */ 487 #define MVGVE_PACC_ACCELERATIONMODE_EDMBPMNC 0x4 /* with BM & PnC */ 488 489 /* Port BM Address (MVGBE_PBMADDR) */ 490 #define MVGBE_PBMADDR_BMADDRESS_MASK 0xfffff800 491 492 /* Ether Type Priority (MVGBE_ETP) */ 493 #define MVGBE_ETP_ETHERTYPEPRIEN (1 << 0) /* EtherType Prio Ena */ 494 #define MVGBE_ETP_ETHERTYPEPRIFRSTEN (1 << 1) 495 #define MVGBE_ETP_ETHERTYPEPRIQ (0x7 << 2) /*EtherType Prio Queue*/ 496 #define MVGBE_ETP_ETHERTYPEPRIVAL (0xffff << 5) /*EtherType Prio Value*/ 497 #define MVGBE_ETP_FORCEUNICSTHIT (1 << 21) /* Force Unicast hit */ 498 499 /* RX Hardware Forwarding (0_1, 2_3,..., 8_9) (MVGBE_RXHWFWD) */ 500 #define MVGBE_RXHWFWD_PORT_BASEADDRESS(p, x) xxxxx 501 502 /* RX Hardware Forwarding Pointer (MVGBE_RXHWFWDPTR) */ 503 #define MVGBE_RXHWFWDPTR_QUEUENO(q) ((q) << 8) /* Queue Number */ 504 #define MVGBE_RXHWFWDPTR_PORTNO(p) ((p) << 11) /* Port Number */ 505 506 /* RX Hardware Forwarding Threshold (MVGBE_RXHWFWDTH) */ 507 #define MVGBE_RXHWFWDTH_DROPRNDGENBITS(n) (((n) & 0x3ff) << 0) 508 #define MVGBE_RXHWFWDTH_DROPTHRESHOLD(n) (((n) & 0xf) << 16) 509 510 /* RX Control (MVGBE_RXCTRL) */ 511 #define MVGBE_RXCTRL_PACKETCOLORSRCSELECT(x) (1 << 0) 512 #define MVGBE_RXCTRL_GEMPORTIDSRCSEL(x) ((x) << 4) 513 #define MVGBE_RXCTRL_TXHWFRWMQSRC(x) (1 << 8) 514 #define MVGBE_RXCTRL_RX_MH_SELECT(x) ((x) << 12) 515 #define MVGBE_RXCTRL_RX_TX_SRC_SELECT (1 << 16) 516 #define MVGBE_RXCTRL_HWFRWDENB (1 << 17) 517 #define MVGBE_RXCTRL_HWFRWDSHORTPOOLID(id) (((id) & 0x3) << 20) 518 #define MVGBE_RXCTRL_HWFRWDLONGPOOLID(id) (((id) & 0x3) << 22) 519 520 /* Port RX queues Configuration (MVGBE_PRXC) */ 521 #define MVGBE_PRXC_POOLIDSHORT(i) (((i) & 0x3) << 4) 522 #define MVGBE_PRXC_POOLIDLONG(i) (((i) & 0x3) << 6) 523 #define MVGBE_PRXC_PACKETOFFSET(o) (((o) & 0xf) << 8) 524 #define MVGBE_PRXC_USERPREFETCHCMND0 (1 << 16) 525 526 /* Port RX queues Snoop (MVGBE_PRXSNP) */ 527 #define MVGBE_PRXSNP_SNOOPNOOFBYTES(b) (((b) & 0x3fff) << 0) 528 #define MVGBE_PRXSNP_L2DEPOSITNOOFBYTES(b) (((b) & 0x3fff) << 16) 529 530 /* Port RX queues Snoop (MVGBE_PRXSNP) */ 531 #define MVGBE_PRXF01_PREFETCHCOMMAND0(c) (((c) & 0xffff) << 0) xxxx 532 #define MVGBE_PRXF01_PREFETCHCOMMAND1(c) (((c) & 0xffff) << 16) xxxx 533 534 /* Port RX queues Descriptors Queue Size (MVGBE_PRXDQS) */ 535 #define MVGBE_PRXDQS_DESCRIPTORSQUEUESIZE(s) (((s) & 0x0003fff) << 0) 536 #define MVGBE_PRXDQS_BUFFERSIZE(s) (((s) & 0xfff80000) << 19) 537 538 /* Port RX queues Descriptors Queue Threshold (MVGBE_PRXDQTH) */ 539 /* Occupied Descriptors Threshold */ 540 #define MVGBE_PRXDQTH_ODT(x) (((x) & 0x3fff) << 0) 541 /* Non Occupied Descriptors Threshold */ 542 #define MVGBE_PRXDQTH_NODT(x) (((x) & 0x3fff) << 16) 543 544 /* Port RX queues Status (MVGBE_PRXS) */ 545 /* Occupied Descriptors Counter */ 546 #define MVGBE_PRXS_ODC(x) (((x) & 0x3fff) << 0) 547 /* Non Occupied Descriptors Counter */ 548 #define MVGBE_PRXS_NODC(x) (((x) & 0x3fff) << 16) 549 550 /* Port RX queues Status Update (MVGBE_PRXSU) */ 551 #define MVGBE_PRXSU_NOOFPROCESSEDDESCRIPTORS(x) (((x) & 0xff) << 0) 552 #define MVGBE_PRXSU_NOOFNEWDESCRIPTORS(x) (((x) & 0xff) << 16) 553 554 /* Port RX Flow Control (MVGBE_PRXFC) */ 555 #define MVGBE_PRXFC_PERPRIOFCGENCONTROL (1 << 0) 556 #define MVGBE_PRXFC_TXPAUSECONTROL (1 << 1) 557 558 /* Port RX_TX Pause (MVGBE_PRXTXP) */ 559 #define MVGBE_PRXTXP_TXPAUSE(x) ((x) & 0xff) 560 561 /* Port RX Flow Control Generation (MVGBE_PRXFCG) */ 562 #define MVGBE_PRXFCG_PERPRIOFCGENDATA (1 << 0) 563 #define MVGBE_PRXFCG_PERPRIOFCGENQNO(x) (((x) & 0x7) << 4) 564 565 /* Port RX Initialization (MVGBE_PRXINIT) */ 566 #define MVGBE_PRXINIT_RXDMAINIT (1 << 0) 567 568 /* TX Number of New Bytes (MVGBE_TXNB) */ 569 #define MVGBE_TXNB_NOOFNEWBYTES(b) (((b) & 0xffff) << 0) 570 #define MVGBE_TXNB_PKTQNO(q) (((q) & 0x7) << 28) 571 #define MVGBE_TXNB_PKTCOLOR (1 << 31) 572 573 /* Port TX queues Descriptors Queue Size (MVGBE_PTXDQS) */ 574 /* Descriptors Queue Size */ 575 #define MVGBE_PTXDQS_DQS(x) (((x) & 0x3fff) << 0) 576 /* Transmitted Buffer Threshold */ 577 #define MVGBE_PTXDQS_TBT(x) (((x) & 0x3fff) << 16) 578 579 /* Port TX queues Status (MVGBE_PTXS) */ 580 /* Pending Descriptors Counter */ 581 #define MVGBE_PTXDQS_PDC(x) (((x) & 0x3fff) << 0) 582 /* Transmitted Buffer Counter */ 583 #define MVGBE_PTXS_TBC(x) (((x) & 0x3fff) << 16) 584 585 /* Port TX queues Status Update (MVGBE_PTXSU) */ 586 /* Number Of Written Descriptors */ 587 #define MVGBE_PTXSU_NOWD(x) (((x) & 0xff) << 0) 588 /* Number Of Released Buffers */ 589 #define MVGBE_PTXSU_NORB(x) (((x) & 0xff) << 16) 590 591 /* TX Transmitted Buffers Counter (MVGBE_TXTBC) */ 592 /* Transmitted Buffers Counter */ 593 #define MVGBE_TXTBC_TBC(x) (((x) & 0x3fff) << 16) 594 595 /* Port TX Initialization (MVGBE_PTXINIT) */ 596 #define MVGBE_PTXINIT_TXDMAINIT (1 << 0) 597 598 /* Marvell Header (MVGBE_MH) */ 599 #define MVGBE_MH_MHEN (1 << 0) 600 #define MVGBE_MH_DAPREFIX (0x3 << 1) 601 #define MVGBE_MH_SPID (0xf << 4) 602 #define MVGBE_MH_MHMASK (0x3 << 8) 603 #define MVGBE_MH_MHMASK_8QUEUES (0x0 << 8) 604 #define MVGBE_MH_MHMASK_4QUEUES (0x1 << 8) 605 #define MVGBE_MH_MHMASK_2QUEUES (0x3 << 8) 606 #define MVGBE_MH_DSAEN_MASK (0x3 << 10) 607 #define MVGBE_MH_DSAEN_DISABLE (0x0 << 10) 608 #define MVGBE_MH_DSAEN_NONEXTENDED (0x1 << 10) 609 #define MVGBE_MH_DSAEN_EXTENDED (0x2 << 10) 610 611 /* Port Auto-Negotiation Configuration (MVGBE_PANC) */ 612 #define MVGBE_PANC_FORCELINKFAIL (1 << 0) 613 #define MVGBE_PANC_FORCELINKPASS (1 << 1) 614 #define MVGBE_PANC_INBANDANEN (1 << 2) 615 #define MVGBE_PANC_INBANDANBYPASSEN (1 << 3) 616 #define MVGBE_PANC_INBANDRESTARTAN (1 << 4) 617 #define MVGBE_PANC_SETMIISPEED (1 << 5) 618 #define MVGBE_PANC_SETGMIISPEED (1 << 6) 619 #define MVGBE_PANC_ANSPEEDEN (1 << 7) 620 #define MVGBE_PANC_SETFCEN (1 << 8) 621 #define MVGBE_PANC_PAUSEADV (1 << 9) 622 #define MVGBE_PANC_ANFCEN (1 << 11) 623 #define MVGBE_PANC_SETFULLDX (1 << 12) 624 #define MVGBE_PANC_ANDUPLEXEN (1 << 13) 625 #define MVGBE_PANC_RESERVED (1 << 15) 626 627 /* Port MAC Control 0 (MVGBE_PMACC0) */ 628 #define MVGBE_PMACC0_PORTEN (1 << 0) 629 #define MVGBE_PMACC0_PORTTYPE (1 << 1) 630 #define MVGBE_PMACC0_FRAMESIZELIMIT(x) ((((x) >> 1) & 0x7ffc) << 2) 631 #define MVGBE_PMACC0_RESERVED (1 << 15) 632 633 /* Port MAC Control 1 (MVGBE_PMACC1) */ 634 #define MVGBE_PMACC1_PCSLB (1 << 6) 635 636 /* Port MAC Control 2 (MVGBE_PMACC2) */ 637 #define MVGBE_PMACC2_PCSEN (1 << 3) 638 #define MVGBE_PMACC2_RGMIIEN (1 << 4) 639 #define MVGBE_PMACC2_PADDINGDIS (1 << 5) 640 #define MVGBE_PMACC2_PORTMACRESET (1 << 6) 641 #define MVGBE_PMACC2_PRBSCHECKEN (1 << 10) 642 #define MVGBE_PMACC2_PRBSGENEN (1 << 11) 643 #define MVGBE_PMACC2_SDTT_MASK (3 << 12) /* Select Data To Transmit */ 644 #define MVGBE_PMACC2_SDTT_RM (0 << 12) /* Regular Mode */ 645 #define MVGBE_PMACC2_SDTT_PRBS (1 << 12) /* PRBS Mode */ 646 #define MVGBE_PMACC2_SDTT_ZC (2 << 12) /* Zero Constant */ 647 #define MVGBE_PMACC2_SDTT_OC (3 << 12) /* One Constant */ 648 #define MVGBE_PMACC2_RESERVED (3 << 14) 649 650 /* Port MAC Control 3 (MVGBE_PMACC3) */ 651 #define MVGBE_PMACC3_IPG_MASK 0x7f80 652 653 /* Port Interrupt Cause/Mask (MVGBE_PIC_2/MVGBE_PIM_2) */ 654 #define MVGBE_PI_2_INTSUM (1 << 0) 655 #define MVGBE_PI_2_LSC (1 << 1) /* LinkStatus Change */ 656 #define MVGBE_PI_2_ACOP (1 << 2) /* AnCompleted OnPort */ 657 #define MVGBE_PI_2_AOOR (1 << 5) /* AddressOut Of Range */ 658 #define MVGBE_PI_2_SSC (1 << 6) /* SyncStatus Change */ 659 #define MVGBE_PI_2_PRBSEOP (1 << 7) /* QSGMII PRBS error */ 660 #define MVGBE_PI_2_MIBCWA (1 << 15) /* MIB counter wrap around */ 661 #define MVGBE_PI_2_QSGMIIPRBSE (1 << 10) /* QSGMII PRBS error */ 662 #define MVGBE_PI_2_PCSRXPRLPI (1 << 11) /* PCS Rx path received LPI*/ 663 #define MVGBE_PI_2_PCSTXPRLPI (1 << 12) /* PCS Tx path received LPI*/ 664 #define MVGBE_PI_2_MACRXPRLPI (1 << 13) /* MAC Rx path received LPI*/ 665 #define MVGBE_PI_2_MIBCCD (1 << 14) /* MIB counters copy done */ 666 667 /* LPI Control 0 (MVGBE_LPIC0) */ 668 #define MVGBE_LPIC0_LILIMIT(x) (((x) & 0xff) << 0) 669 #define MVGBE_LPIC0_TSLIMIT(x) (((x) & 0xff) << 8) 670 671 /* LPI Control 1 (MVGBE_LPIC1) */ 672 #define MVGBE_LPIC1_LPIRE (1 << 0) /* LPI request enable */ 673 #define MVGBE_LPIC1_LPIRF (1 << 1) /* LPI request force */ 674 #define MVGBE_LPIC1_LPIMM (1 << 2) /* LPI manual mode */ 675 #define MVGBE_LPIC1_TWLIMIT (((x) & 0xfff) << 4) 676 677 /* LPI Status (MVGBE_LPIS) */ 678 #define MVGBE_LPIS_PCSRXPLPIS (1 << 0) /* PCS Rx path LPI status */ 679 #define MVGBE_LPIS_PCSTXPLPIS (1 << 1) /* PCS Tx path LPI status */ 680 #define MVGBE_LPIS_MACRXPLPIS (1 << 2)/* MAC Rx path LP idle status */ 681 #define MVGBE_LPIS_MACTXPLPWS (1 << 3)/* MAC Tx path LP wait status */ 682 #define MVGBE_LPIS_MACTXPLPIS (1 << 4)/* MAC Tx path LP idle status */ 683 684 /* Port PRBS Status (MVGBE_PPRBSS) */ 685 #define MVGBE_PPRBSS_PRBSCHECKLOCKED (1 << 0) 686 #define MVGBE_PPRBSS_PRBSCHECKRDY (1 << 1) 687 688 /* Port Status 0 (MVGBE_PS0) */ 689 #define MVGBE_PS0_LINKUP (1 << 0) 690 #define MVGBE_PS0_GMIISPEED (1 << 1) 691 #define MVGBE_PS0_MIISPEED (1 << 2) 692 #define MVGBE_PS0_FULLDX (1 << 3) 693 #define MVGBE_PS0_RXFCEN (1 << 4) 694 #define MVGBE_PS0_TXFCEN (1 << 5) 695 #define MVGBE_PS0_PRP (1 << 6) /* Port Rx Pause */ 696 #define MVGBE_PS0_PTP (1 << 7) /* Port Tx Pause */ 697 #define MVGBE_PS0_PDP (1 << 8) /*Port is Doing Back-Pressure*/ 698 #define MVGBE_PS0_SYNCFAIL10MS (1 << 10) 699 #define MVGBE_PS0_ANDONE (1 << 11) 700 #define MVGBE_PS0_IBANBA (1 << 12) /* InBand AutoNeg BypassAct */ 701 #define MVGBE_PS0_SYNCOK (1 << 14) 702 703 /* Port CPUn to Queue (MVGBE_PCP2Q) */ 704 #define MVGBE_PCP2Q_RXQAE(q) (1 << ((q) + << 0))/*QueueAccessEnable*/ 705 #define MVGBE_PCP2Q_TXQAE(q) (1 << ((q) + << 8))/*QueueAccessEnable*/ 706 707 /* Port RX_TX Threshold Interrupt Cause/Mask (MVGBE_PRXTXTIC/MVGBE_PRXTXTIM) */ 708 #define MVGBE_PRXTXTI_TBTCQ(q) (1 << ((q) + 0)) 709 #define MVGBE_PRXTXTI_RBICTAPQ(q) (1 << ((q) + 8)) 710 #define MVGBE_PRXTXTI_RDTAQ(q) (1 << ((q) + 16)) 711 #define MVGBE_PRXTXTI_PRXTXICSUMMARY (1 << 29) 712 #define MVGBE_PRXTXTI_PTXERRORSUMMARY (1 << 30) 713 #define MVGBE_PRXTXTI_PMISCICSUMMARY (1 << 31) 714 715 /* Port RX_TX Interrupt Cause/Mask (MVGBE_PRXTXIC/MVGBE_PRXTXIM) */ 716 #define MVGBE_PRXTXI_TBRQ(q) (1 << ((q) + 0)) 717 #define MVGBE_PRXTXI_RPQ(q) (1 << ((q) + 8)) 718 #define MVGBE_PRXTXI_RREQ(q) (1 << ((q) + 16)) 719 #define MVGBE_PRXTXI_PRXTXTHICSUMMARY (1 << 29) 720 #define MVGBE_PRXTXI_PTXERRORSUMMARY (1 << 30) 721 #define MVGBE_PRXTXI_PMISCICSUMMARY (1 << 31) 722 723 /* Port Misc Interrupt Cause/Mask (MVGBE_PMIC/MVGBE_PMIM) */ 724 #define MVGBE_PMI_PHYSTATUSCHNG (1 << 0) 725 #define MVGBE_PMI_LINKCHANGE (1 << 1) 726 #define MVGBE_PMI_PTP (1 << 4) 727 #define MVGBE_PMI_PME (1 << 6) /* Packet Modification Error */ 728 #define MVGBE_PMI_IAE (1 << 7) /* Internal Address Error */ 729 #define MVGBE_PMI_RXOVERRUN (1 << 8) 730 #define MVGBE_PMI_RXCRCERROR (1 << 9) 731 #define MVGBE_PMI_RXLARGEPACKET (1 << 10) 732 #define MVGBE_PMI_TXUNDRN (1 << 11) 733 #define MVGBE_PMI_PRBSERROR (1 << 12) 734 #define MVGBE_PMI_SRSE (1 << 14) /* SerdesRealignSyncError */ 735 #define MVGBE_PMI_RNBTP(q) (1 << ((q) + 16)) /* RxNoBuffersToPool*/ 736 #define MVGBE_PMI_TREQ(q) (1 << ((q) + 24)) /* TxResourceErrorQ */ 737 738 /* Port Interrupt Enable (MVGBE_PIE) */ 739 #define MVGBE_PIE_RXPKTINTRPTENB(q) (1 << ((q) + 0)) 740 #define MVGBE_PIE_TXPKTINTRPTENB(q) (1 << ((q) + 8)) 741 742 /* Power and PLL Control (MVGBE_PPLLC) */ 743 #define MVGBE_PPLLC_REF_FREF_SEL_MASK (0xf << 0) 744 #define MVGBE_PPLLC_PHY_MODE_MASK (7 << 5) 745 #define MVGBE_PPLLC_PHY_MODE_SATA (0 << 5) 746 #define MVGBE_PPLLC_PHY_MODE_SAS (1 << 5) 747 #define MVGBE_PPLLC_PLL_LOCK (1 << 8) 748 #define MVGBE_PPLLC_PU_DFE (1 << 10) 749 #define MVGBE_PPLLC_PU_TX_INTP (1 << 11) 750 #define MVGBE_PPLLC_PU_TX (1 << 12) 751 #define MVGBE_PPLLC_PU_RX (1 << 13) 752 #define MVGBE_PPLLC_PU_PLL (1 << 14) 753 754 /* Digital Loopback Enable (MVGBE_DLE) */ 755 #define MVGBE_DLE_LOCAL_SEL_BITS_MASK (3 << 10) 756 #define MVGBE_DLE_LOCAL_SEL_BITS_10BITS (0 << 10) 757 #define MVGBE_DLE_LOCAL_SEL_BITS_20BITS (1 << 10) 758 #define MVGBE_DLE_LOCAL_SEL_BITS_40BITS (2 << 10) 759 #define MVGBE_DLE_LOCAL_RXPHER_TO_TX_EN (1 << 12) 760 #define MVGBE_DLE_LOCAL_ANA_TX2RX_LPBK_EN (1 << 13) 761 #define MVGBE_DLE_LOCAL_DIG_TX2RX_LPBK_EN (1 << 14) 762 #define MVGBE_DLE_LOCAL_DIG_RX2TX_LPBK_EN (1 << 15) 763 764 /* Reference Clock Select (MVGBE_RCS) */ 765 #define MVGBE_RCS_REFCLK_SEL (1 << 10) 766 767 768 /* 769 * Set the chip's packet size limit to 9022. 770 * (ETHER_MAX_LEN_JUMBO + ETHER_VLAN_ENCAP_LEN) 771 */ 772 #define MVGBE_MRU 9022 773 774 #define MVGBE_RXBUF_ALIGN 32 /* Cache line size */ 775 #define MVGBE_RXBUF_MASK (MVGBE_RXBUF_ALIGN - 1) 776 #define MVGBE_HWHEADER_SIZE 2 777 778 779 /* 780 * DMA descriptors 781 * Despite the documentation saying these descriptors only need to be 782 * aligned to 16-byte boundaries, 32-byte alignment seems to be required 783 * by the hardware. We'll just pad them out to that to make it easier. 784 */ 785 struct mvgbe_tx_desc { 786 #ifdef MVGBE_BIG_ENDIAN 787 uint16_t bytecnt; /* Descriptor buffer byte count */ 788 uint16_t l4ichk; /* CPU provided TCP Checksum */ 789 uint32_t cmdsts; /* Descriptor command status */ 790 uint32_t nextdescptr; /* Next descriptor pointer */ 791 uint32_t bufptr; /* Descriptor buffer pointer */ 792 #else 793 uint32_t cmdsts; /* Descriptor command status */ 794 uint16_t l4ichk; /* CPU provided TCP Checksum */ 795 uint16_t bytecnt; /* Descriptor buffer byte count */ 796 uint32_t bufptr; /* Descriptor buffer pointer */ 797 uint32_t nextdescptr; /* Next descriptor pointer */ 798 #endif 799 uint32_t _padding[4]; 800 } __packed; 801 802 struct mvgbe_rx_desc { 803 #ifdef MVGBE_BIG_ENDIAN 804 uint16_t bytecnt; /* Descriptor buffer byte count */ 805 uint16_t bufsize; /* Buffer size */ 806 uint32_t cmdsts; /* Descriptor command status */ 807 uint32_t nextdescptr; /* Next descriptor pointer */ 808 uint32_t bufptr; /* Descriptor buffer pointer */ 809 #else 810 uint32_t cmdsts; /* Descriptor command status */ 811 uint16_t bufsize; /* Buffer size */ 812 uint16_t bytecnt; /* Descriptor buffer byte count */ 813 uint32_t bufptr; /* Descriptor buffer pointer */ 814 uint32_t nextdescptr; /* Next descriptor pointer */ 815 #endif 816 uint32_t _padding[4]; 817 } __packed; 818 819 #define MVGBE_ERROR_SUMMARY (1 << 0) 820 #define MVGBE_BUFFER_OWNED_MASK (1 << 31) 821 #define MVGBE_BUFFER_OWNED_BY_HOST (0 << 31) 822 #define MVGBE_BUFFER_OWNED_BY_DMA (1 << 31) 823 824 #define MVGBE_TX_ERROR_CODE_MASK (3 << 1) 825 #define MVGBE_TX_LATE_COLLISION_ERROR (0 << 1) 826 #define MVGBE_TX_UNDERRUN_ERROR (1 << 1) 827 #define MVGBE_TX_EXCESSIVE_COLLISION_ERRO (2 << 1) 828 #define MVGBE_TX_LLC_SNAP_FORMAT (1 << 9) 829 #define MVGBE_TX_IP_NO_FRAG (1 << 10) 830 #define MVGBE_TX_IP_HEADER_LEN(len) ((len) << 11) 831 #define MVGBE_TX_VLAN_TAGGED_FRAME (1 << 15) 832 #define MVGBE_TX_L4_TYPE_TCP (0 << 16) 833 #define MVGBE_TX_L4_TYPE_UDP (1 << 16) 834 #define MVGBE_TX_GENERATE_L4_CHKSUM (1 << 17) 835 #define MVGBE_TX_GENERATE_IP_CHKSUM (1 << 18) 836 #define MVGBE_TX_ZERO_PADDING (1 << 19) 837 #define MVGBE_TX_LAST_DESC (1 << 20) 838 #define MVGBE_TX_FIRST_DESC (1 << 21) 839 #define MVGBE_TX_GENERATE_CRC (1 << 22) 840 #define MVGBE_TX_ENABLE_INTERRUPT (1 << 23) 841 #define MVGBE_TX_AUTO_MODE (1 << 30) 842 843 #define MVGBE_RX_ERROR_CODE_MASK (3 << 1) 844 #define MVGBE_RX_CRC_ERROR (0 << 1) 845 #define MVGBE_RX_OVERRUN_ERROR (1 << 1) 846 #define MVGBE_RX_MAX_FRAME_LEN_ERROR (2 << 1) 847 #define MVGBE_RX_RESOURCE_ERROR (3 << 1) 848 #define MVGBE_RX_L4_CHECKSUM_MASK (0xffff << 3) 849 #define MVGBE_RX_VLAN_TAGGED_FRAME (1 << 19) 850 #define MVGBE_RX_BPDU_FRAME (1 << 20) 851 #define MVGBE_RX_L4_TYPE_MASK (3 << 21) 852 #define MVGBE_RX_L4_TYPE_TCP (0 << 21) 853 #define MVGBE_RX_L4_TYPE_UDP (1 << 21) 854 #define MVGBE_RX_L4_TYPE_OTHER (2 << 21) 855 #define MVGBE_RX_NOT_LLC_SNAP_FORMAT (1 << 23) 856 #define MVGBE_RX_IP_FRAME_TYPE (1 << 24) 857 #define MVGBE_RX_IP_HEADER_OK (1 << 25) 858 #define MVGBE_RX_LAST_DESC (1 << 26) 859 #define MVGBE_RX_FIRST_DESC (1 << 27) 860 #define MVGBE_RX_UNKNOWN_DA (1 << 28) 861 #define MVGBE_RX_ENABLE_INTERRUPT (1 << 29) 862 #define MVGBE_RX_L4_CHECKSUM_OK (1 << 30) 863 864 #define MVGBE_RX_IP_FRAGMENT (1 << 2) 865 866 #endif /* _MVGEREG_H_ */ 867
Indexes created Wed Oct 01 18:09:54 GMT 2025