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    Searched defs:N3 (Results 1 - 12 of 12) sorted by relevancy

  /src/external/gpl3/gdb.old/dist/gdb/testsuite/gdb.compile/
compile-cplus-namespace.cc 20 namespace N3
45 using namespace N1::N2::N3::N4;
  /src/external/gpl3/gdb/dist/gdb/testsuite/gdb.compile/
compile-cplus-namespace.cc 20 namespace N3
45 using namespace N1::N2::N3::N4;
  /src/sys/external/isc/libsodium/dist/test/default/
pwhash_scrypt_ll.c 19 static const uint64_t N3 = 16384U;
56 tv(passwd3, salt3, N3, r3, p3);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUInstructionSelector.h 242 // g_ptr_add (n0, (n1 = g_ptr_add n2, n3))
244 Register N0, N2, N3;
AMDGPUISelDAGToDAG.cpp 1415 // (add N2, N3) -> addr64, or
1416 // (add (add N2, N3), C1) -> addr64
1418 SDValue N3 = N0.getOperand(1);
1422 if (N3->isDivergent()) {
1423 // Both N2 and N3 are divergent. Use N0 (the result of the add) as the
1428 // N2 is divergent, N3 is not.
1429 Ptr = N3;
1435 VAddr = N3;
  /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/
BPFISelDAGToDAG.cpp 215 SDValue N3 = Node->getOperand(3);
219 Node = CurDAG->UpdateNodeOperands(Node, Chain, N1, R6Reg, N3);
  /src/external/apache2/llvm/dist/llvm/lib/Target/XCore/
XCoreISelLowering.cpp 1710 SDValue N3 = N->getOperand(3);
1719 N1, N0, N2, N3);
1725 SDValue Lo = DAG.getNode(ISD::ADD, dl, VT, N2, N3);
1731 DAG.getNode(XCoreISD::LADD, dl, DAG.getVTList(VT, VT), N2, N3, N1);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelDAGToDAG.cpp 3302 SDNode *N3 = CurDAG->getMachineNode(
3306 ReplaceNode(N, N3);
  /src/external/bsd/ntp/dist/ntpd/
refclock_wwv.c 427 #define N3 (N15 / 2) /* space (-1) */
430 {N3, N3, 0, 0}, /* 0 */
431 {P3, N3, 0, 0}, /* 1 */
432 {N3, P3, 0, 0}, /* 2 */
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelDAGToDAG.cpp 3907 SDValue N3 = N->getOperand(3);
3911 assert(N3.getOpcode() == ISD::Register);
3964 SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
ARMISelLowering.cpp 9138 SDValue N2, N3;
9146 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
9154 N2 = LowerSDIV_v4i8(N2, N3, dl, DAG); // v4i16
9175 SDValue N2, N3;
9183 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
9191 N2 = LowerSDIV_v4i16(N2, N3, dl, DAG); // v4i16
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
DAGCombiner.cpp 541 SDValue N2, SDValue N3, ISD::CondCode CC,
544 const SDLoc &DL, SDValue N0, SDValue N1, SDValue N2, SDValue N3,
548 SDValue N2, SDValue N3, ISD::CondCode CC);
10088 SDValue N3 = N->getOperand(3);
10093 if (N2 == N3)
10105 return N3; // cond always false -> false val
10114 SCC.getOperand(1), N2, N3, SCC.getOperand(2));
10121 if (SimplifySelectOps(N, N2, N3))
10125 return SimplifySelectCC(SDLoc(N), N0, N1, N2, N3, CC);
22117 /// Try to fold an expression of the form (N0 cond N1) ? N2 : N3 to a shift an
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