1 /* $NetBSD: if_snvar.h,v 1.15 2021/11/10 17:19:29 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 1991 Algorithmics Ltd (http://www.algor.co.uk) 5 * You may use, copy, and modify this program so long as you retain the 6 * copyright line. 7 */ 8 9 /* 10 * if_snvar.h -- National Semiconductor DP8393X (SONIC) NetBSD/newsmips vars 11 */ 12 13 /* 14 * Memory access macros. Since we handle SONIC in 16 bit mode (PB5X0) 15 * and 32 bit mode (everything else) using a single GENERIC kernel 16 * binary, all structures have to be accessed using macros which can 17 * adjust the offsets appropriately. 18 */ 19 #define SWO(m, a, o, x) (*(uint32_t *)((uint32_t *)(a) + (o)) = (x)) 20 #define SRO(m, a, o) (*(uint32_t *)((uint32_t *)(a) + (o)) & 0xffff) 21 22 /* 23 * Register access macros. We use bus_space_* to talk to the Sonic 24 * registers. A mapping table is used in case a particular configuration 25 * hooked the regs up at non-word offsets. 26 */ 27 #define NIC_GET(sc, reg) ((sc)->sc_regbase[(reg) * 4 + 3]) 28 #define NIC_PUT(sc, reg, val) ((sc)->sc_regbase[(reg) * 4 + 3] = val) 29 30 #define SONIC_GETDMA(sc, p) (((sc)->sc_flags & F_NWS40S0) == 0 ? \ 31 ((uint32_t)(p)) : (((uint32_t)(p) & 0xffff) | 0xfff00000)) 32 #define SONIC_BUFFER(sc, p) (((sc)->sc_flags & F_NWS40S0) == 0 ? \ 33 (p) : \ 34 (void *)(((uint32_t)((sc)->buffer)) | ((uint32_t)(p) & 0xffff))) 35 36 #define SN_REGSIZE (SN_NREGS * 4) 37 38 #include <mips/locore.h> 39 40 /* 41 * buffer sizes in 32 bit mode 42 * 1 TXpkt is 4 hdr words + (3 * FRAGMAX) + 1 link word == 23 words == 92 bytes 43 * 44 * 1 RxPkt is 7 words == 28 bytes 45 * 1 Rda is 4 words == 16 bytes 46 * 47 * The CDA is 17 words == 68 bytes 48 * 49 * total space in page 0 = NTDA * 92 + NRRA * 16 + NRDA * 28 + 68 50 */ 51 52 #define NRBA 4 /* # receive buffers < NRRA */ 53 #define RBAMASK (NRBA - 1) 54 #define NTDA 4 /* # transmit descriptors */ 55 #define NRRA 8 /* # receive resource descriptors */ 56 #define RRAMASK (NRRA - 1) /* the reason why NRRA must be power of two */ 57 58 #define FCSSIZE 4 /* size of FCS appended to packets */ 59 60 /* 61 * maximum receive packet size plus 2 byte pad to make each 62 * one aligned. 4 byte slop (required for eobc) 63 */ 64 #define RBASIZE(sc) (ETHER_HDR_LEN + ETHERMTU + FCSSIZE + 6) 65 66 /* 67 * transmit buffer area 68 */ 69 #define TXBSIZE 1536 /* 6*2^8 -- the same size as the 8390 TXBUF */ 70 71 #define SN_NPAGES 2 + NRBA + (NTDA / 2) 72 73 typedef struct mtd { 74 void *mtd_txp; 75 uint32_t mtd_vtxp; 76 void *mtd_buf; 77 uint32_t mtd_vbuf; 78 struct mbuf *mtd_mbuf; 79 } mtd_t; 80 81 /* 82 * The sn_softc for NEWS5000 if_sn. 83 */ 84 struct sn_softc { 85 device_t sc_dev; 86 struct ethercom sc_ethercom; 87 #define sc_if sc_ethercom.ec_if /* network visible interface */ 88 89 void * sc_hwbase; /* hardware base address */ 90 volatile uint16_t *sc_regbase; /* register base address */ 91 92 int bitmode; /* 32 bit mode == 1, 16 == 0 */ 93 94 uint16_t snr_dcr; /* DCR for this instance */ 95 uint16_t snr_dcr2; /* DCR2 for this instance */ 96 int slotno; /* Slot number */ 97 98 int sc_rramark; /* index into p_rra of wp */ 99 void *p_rra[NRRA]; /* RX resource descs */ 100 uint32_t v_rra[NRRA]; /* DMA addresses of p_rra */ 101 uint32_t v_rea; /* ptr to the end of the rra space */ 102 103 int sc_rxmark; /* current hw pos in rda ring */ 104 int sc_rdamark; /* current sw pos in rda ring */ 105 int sc_nrda; /* total number of RDAs */ 106 void *p_rda; 107 uint32_t v_rda; 108 109 void *rbuf[NRBA]; 110 111 struct mtd mtda[NTDA]; 112 int mtd_hw; /* idx of first mtd given to hw */ 113 int mtd_prev; /* idx of last mtd given to hardware */ 114 int mtd_free; /* next free mtd to use */ 115 int mtd_tlinko; /* 116 * offset of tlink of last txp given 117 * to SONIC. Need to clear EOL on 118 * this word to add a desc. 119 */ 120 int mtd_pint; /* Counter to set TXP_PINT */ 121 122 void *p_cda; 123 uint32_t v_cda; 124 125 uint8_t *memory; 126 uint8_t *buffer; 127 u_int sc_flags; 128 #define F_NWS40S0 0x0001 129 }; 130 131 /* 132 * Accessing SONIC data structures and registers as 32 bit values 133 * makes code endianness independent. The SONIC is however always in 134 * bigendian mode so it is necessary to ensure that data structures shared 135 * between the CPU and the SONIC are always in bigendian order. 136 */ 137 138 /* 139 * Receive Resource Descriptor 140 * This structure describes the buffers into which packets 141 * will be received. Note that more than one packet may be 142 * packed into a single buffer if constraints permit. 143 */ 144 #define RXRSRC_PTRLO 0 /* buffer address LO */ 145 #define RXRSRC_PTRHI 1 /* buffer address HI */ 146 #define RXRSRC_WCLO 2 /* buffer size (16bit words) LO */ 147 #define RXRSRC_WCHI 3 /* buffer size (16bit words) HI */ 148 149 #define RXRSRC_SIZE(sc) (4 * 4) 150 151 /* 152 * Receive Descriptor 153 * This structure holds information about packets received. 154 */ 155 #define RXPKT_STATUS 0 156 #define RXPKT_BYTEC 1 157 #define RXPKT_PTRLO 2 158 #define RXPKT_PTRHI 3 159 #define RXPKT_SEQNO 4 160 #define RXPKT_RLINK 5 161 #define RXPKT_INUSE 6 162 #define RXPKT_SIZE(sc) (7 * 4) 163 164 #define RBASEQ(x) (((x) >> 8) & 0xff) 165 #define PSNSEQ(x) ((x) & 0xff) 166 167 /* 168 * Transmit Descriptor 169 * This structure holds information about packets to be transmitted. 170 */ 171 #define FRAGMAX 8 /* maximum number of fragments in a packet */ 172 173 #define TXP_STATUS 0 /* + transmitted packet status */ 174 #define TXP_CONFIG 1 /* transmission configuration */ 175 #define TXP_PKTSIZE 2 /* entire packet size in bytes */ 176 #define TXP_FRAGCNT 3 /* # fragments in packet */ 177 178 #define TXP_FRAGOFF 4 /* offset to first fragment */ 179 #define TXP_FRAGSIZE 3 /* size of each fragment desc */ 180 #define TXP_FPTRLO 0 /* ptr to packet fragment LO */ 181 #define TXP_FPTRHI 1 /* ptr to packet fragment HI */ 182 #define TXP_FSIZE 2 /* fragment size */ 183 184 #define TXP_WORDS (TXP_FRAGOFF + (FRAGMAX * TXP_FRAGSIZE) + 1) /* 1 for tlink */ 185 #define TXP_SIZE(sc) (TXP_WORDS*4) 186 187 #define EOL 0x0001 /* end of list marker for link fields */ 188 189 /* 190 * CDA, the CAM descriptor area. The SONIC has a 16 entry CAM to 191 * match incoming addresses against. It is programmed via DMA 192 * from a memory region. 193 */ 194 #define MAXCAM 16 /* number of user entries in CAM */ 195 #define CDA_CAMDESC 4 /* # words i na descriptor */ 196 #define CDA_CAMEP 0 /* CAM Address Port 0 xx-xx-xx-xx-YY-YY */ 197 #define CDA_CAMAP0 1 /* CAM Address Port 1 xx-xx-YY-YY-xx-xx */ 198 #define CDA_CAMAP1 2 /* CAM Address Port 2 YY-YY-xx-xx-xx-xx */ 199 #define CDA_CAMAP2 3 200 #define CDA_ENABLE 64 /* mask enabling CAM entries */ 201 #define CDA_SIZE(sc) ((4 * 16 + 1) * ((sc->bitmode) ? 4 : 2)) 202 203 int snsetup(struct sn_softc *sc, uint8_t *); 204 int snintr(void *); 205 void sn_md_init(struct sn_softc *); 206
Indexes created Sun Sep 21 20:09:37 GMT 2025