1 /* $NetBSD: walnut.h,v 1.2 2006/03/08 23:46:23 lukem Exp $ */ 2 3 /* include/eval.h, openbios_walnut, walnut_bios 8/10/00 14:35:05 */ 4 /*-----------------------------------------------------------------------------+ 5 | 6 | This source code has been made available to you by IBM on an AS-IS 7 | basis. Anyone receiving this source is licensed under IBM 8 | copyrights to use it in any way he or she deems fit, including 9 | copying it, modifying it, compiling it, and redistributing it either 10 | with or without modifications. No license under IBM patents or 11 | patent applications is to be implied by the copyright license. 12 | 13 | Any user of this software should understand that IBM cannot provide 14 | technical support for this software and will not be responsible for 15 | any consequences resulting from the use of this software. 16 | 17 | Any person who transfers this source code or any derivative work 18 | must include the IBM copyright notice, this paragraph, and the 19 | preceding two paragraphs in the transferred software. 20 | 21 | COPYRIGHT I B M CORPORATION 1995 22 | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M 23 +-----------------------------------------------------------------------------*/ 24 /*-----------------------------------------------------------------------------+ 25 | 26 | File Name: eval.h 27 | 28 | Function: Openbios board specific defines. Should contain no 29 | prototypes since this file gets included in assembly files. 30 | 31 | Author: James Burke 32 | 33 | Change Activity- 34 | 35 | Date Description of Change BY 36 | --------- --------------------- --- 37 | 11-May-99 Created for Walnut JWB 38 | 01-Jul-99 Made ROM/SRAM non-cacheable in D_CACHEABLE_REGIONS JWB 39 | 08-Aug-00 Added memory regions and MMIO regions for ROM Monitor debug JWB 40 | 10-Aug-00 Modified PCI memory regions JWB 41 | 42 +-----------------------------------------------------------------------------*/ 43 44 #ifndef _WALNUT_H_ 45 #define _WALNUT_H_ 46 47 /*----------------------------------------------------------------------------+ 48 | 405GP PCI core memory map defines. 49 +----------------------------------------------------------------------------*/ 50 #define MIN_PCI_MEMADDR_NOPREFETCH 0x80000000 51 #define MIN_PCI_MEMADDR_PREFETCH 0xc0000000 52 #define MIN_PCI_MEMADDR_VGA 0x00000000 53 #define MIN_PLB_PCI_IOADDR 0xe8000000 /* PLB side of PCI I/O address space */ 54 #define MIN_PCI_PCI_IOADDR 0x00000000 /* PCI side of PCI I/O address space */ 55 #define MAX_PCI_DEVICES 5 56 57 #define SRAM_START_ADDR 0xfff00000 /* SRAM starting addr */ 58 #define SRAM_SIZE 0x80000 /* SRAM size - 512K */ 59 60 /*----------------------------------------------------------------------------+ 61 | Universal Interrupt Controller (UIC) events for the Walnut board. 62 +----------------------------------------------------------------------------*/ 63 /* Walnut board external IRQs */ 64 #define EXT_IRQ_FPGA UIC_E0IS /* IRQ 25 */ 65 #define EXT_IRQ_SMI UIC_E1IS /* IRQ 26 */ 66 #define EXT_IRQ_UNUSED UIC_E2IS /* IRQ 27 */ 67 #define EXT_IRQ_PCI_SLOT3 UIC_E3IS /* IRQ 28 */ 68 #define EXT_IRQ_PCI_SLOT2 UIC_E4IS /* IRQ 29 */ 69 #define EXT_IRQ_PCI_SLOT1 UIC_E5IS /* IRQ 30 */ 70 #define EXT_IRQ_PCI_SLOT0 UIC_E6IS /* IRQ 31 */ 71 72 #define EXT_IRQ_CASCADE EXT_IRQ_FPGA 73 #define EXT_IRQ_EXPANSION EXT_IRQ_FPGA 74 #define EXT_IRQ_IR EXT_IRQ_FPGA 75 #define EXT_IRQ_KEYBOARD EXT_IRQ_FPGA 76 #define EXT_IRQ_MOUSE EXT_IRQ_FPGA 77 78 /*-----------------------------------------------------------------------------+ 79 | Defines for the RTC/NVRAM. 80 +-----------------------------------------------------------------------------*/ 81 #define NVRAM_BASE 0xf0000000 82 #if 0 83 #define RTC_CONTROL 0x1ff8 84 #define RTC_SECONDS 0x1ff9 85 #define RTC_MINUTES 0x1ffa 86 #define RTC_HOURS 0x1ffb 87 #define RTC_DAY 0x1ffc 88 #define RTC_DATE 0x1ffd 89 #define RTC_MONTH 0x1ffe 90 #define RTC_YEAR 0x1fff 91 #endif 92 93 /*-----------------------------------------------------------------------------+ 94 | Defines for the Keyboard/Mouse controller. 95 +-----------------------------------------------------------------------------*/ 96 #define KEY_MOUSE_BASE 0xf0100000 97 #define KEY_MOUSE_DATA 0x0 98 #define KEY_MOUSE_CMD 0x1 /* write only */ 99 #define KEY_MOUSE_STAT 0x1 /* read only */ 100 101 /*-----------------------------------------------------------------------------+ 102 | Defines for FPGA regs. 103 +-----------------------------------------------------------------------------*/ 104 #define FPGA_BASE 0xf0300000 105 #define FPGA_INT_STATUS 0x00 /* Int status - read only */ 106 #define FPGA_SW_SMI 0x10 /* SW_SMI_N present */ 107 #define FPGA_EXT_IRQ 0x08 /* EXT_IRQ present */ 108 #define FPGA_IRQ_IRDA 0x04 /* IRQ_IRDA present */ 109 #define FPGA_IRQ_KYBD 0x02 /* IRQ_KYBD present */ 110 #define FPGA_IRQ_MOUSE 0x01 /* IRQ_MOUSE present */ 111 #define FPGA_INT_ENABLE 0x01 /* Int enable */ 112 /* FPGA_SW_SMI */ /* enable SW_SMI_N */ 113 /* FPGA_EXT_IRQ */ /* enable FPGA_EXT_IRQ */ 114 /* FPGA_IRQ_IRDA */ /* enable FPGA_IRQ_IRDA */ 115 /* FPGA_IRQ_KYBD */ /* enable FPGA_IRQ_KYBD */ 116 /* FPGA_IRQ_MOUSE */ /* enable FPGA_IRQ_MOUSE */ 117 #define FPGA_INT_POL 0x02 /* Int polarity */ 118 /* FPGA_SW_SMI */ /* SW_SMI_N active high/rising */ 119 /* FPGA_EXT_IRQ */ /* FPGA_EXT_IRQ active high/rising */ 120 /* FPGA_IRQ_IRDA */ /* FPGA_IRQ_IRDA active high/rising */ 121 /* FPGA_IRQ_KYBD */ /* FPGA_IRQ_KYBD active high/rising */ 122 /* FPGA_IRQ_MOUSE */ /* FPGA_IRQ_MOUSE active high/rising */ 123 #define FPGA_INT_TRIG 0x03 /* Int type */ 124 /* FPGA_SW_SMI */ /* SW_SMI_N level */ 125 /* FPGA_EXT_IRQ */ /* FPGA_EXT_IRQ level */ 126 /* FPGA_IRQ_IRDA */ /* FPGA_IRQ_IRDA level */ 127 /* FPGA_IRQ_KYBD */ /* FPGA_IRQ_KYBD level */ 128 /* FPGA_IRQ_MOUSE */ /* FPGA_IRQ_MOUSE level */ 129 #define FPGA_BRDC 0x04 /* Board controls */ 130 #define FPGA_BRDC_INT 0x80 /* IRQ_MOUSE is separate */ 131 #define FPGA_BRDC_TC3 0x10 /* DMA_EOT/TC3 is set to TC */ 132 #define FPGA_BRDC_TC2 0x08 /* DMA_EOT/TC2 is set to TC */ 133 #define FPGA_BRDC_DIS_EI 0x04 /* disable expansion interface */ 134 #define FPGA_BRDC_EN_INV 0x02 /* enable invalid address checking */ 135 #define FPGA_BRDC_UART_CR 0x01 /* UART1 is set to CTS/RTS */ 136 #define FPGA_BRDS1 0x05 /* Board status - read only */ 137 #define FPGA_BRDS1_CLK 0x04 /* 405 SDRAM CLK disabled, MPC972 used */ 138 #define FPGA_BRDS1_FLASH_EN 0x02 /* On board FLASH disabled */ 139 #define FPGA_BRDS1_FLASH_SEL 0x01 /* FLASH at low addr */ 140 #define FPGA_BRDS2 0x06 /* Board status - read only */ 141 #define SW_CLK_SRC1 0x40 /* if async pci, ext or int clk */ 142 #define SW_SEL1 0x20 /* use test clock for master clock */ 143 #define SW_SEL0 0x10 /* use 405GP arbiter */ 144 #define FSEL_B 0x0c /* use for mask */ 145 #define FSEL_SDRAM100 0x01 /* select 100 MHz SDRAM */ 146 #define FSEL_SDRAM66 0x03 /* select 66 MHz SDRAM */ 147 #define FSEL_A 0x03 /* use for mask */ 148 #define FSEL_PCI_66 0x01 /* select 66 MHz async int PCI */ 149 #define FSEL_PCI_33 0x03 /* select 33 MHz async int PCI */ 150 #define FPGA_SPARE1 0x0e /* Spare inputs - read only */ 151 #define FPGA_SPARE2 0x0f /* Spare outputs */ 152 #define FPGA_SIZE FPGA_SPARE2 153 154 #endif /* _WALNUT_H_ */ 155
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